Gabe Black
b84ae9bd40
X86: Update X86_FS stats.
2011-02-27 16:24:54 -08:00
Korey Sewell
8135b81ae4
inorder: bzip2 regression update
2011-02-27 14:17:26 -05:00
Korey Sewell
72fb282ab1
inorder: add 00.gzip and 60.bzip2 regression tests
2011-02-23 16:35:25 -05:00
Ali Saidi
73603c2b17
ARM: Update regression tests for preceeding changes.
2011-02-23 15:10:50 -06:00
Korey Sewell
66bb732c04
m5: merge inorder/release-notes/make_release changes
2011-02-18 14:35:15 -05:00
Korey Sewell
ab9c20cc78
inorder: regr-update: reduce dynamic mem. use to speedup sims
...
previous changesets took a closer look at memory mgmt in the inorder model and sought to avoid
dynamic memory mgmt (for access to pipeline resources) as much as possible. For the regressions
that were run, the sims are about 2x speedup from changeset 7726 which is the last change
since the recent commits in Feb. (note: these regressions now are 4-issue CPUs instead of just 1-issue)
2011-02-18 14:31:37 -05:00
Gabe Black
5ec5794456
X86: Update stats for the improved branch detection/prediction.
2011-02-13 17:46:04 -08:00
Gabe Black
44306e8114
X86: Update stats now that the dest reg isn't read unnecessarily to set flags.
2011-02-13 17:45:30 -08:00
Gabe Black
b046f3feb6
X86: Update stats for the reduced register reads.
2011-02-13 17:44:32 -08:00
Korey Sewell
2971b8401a
inorder:regress: host-inst-rate improved ~58%
...
there are still only a few inorder benchmark but for the lengthier benchmarks (twolf and vortext)
the latest changes to how instruction scheduling (how instructions figure out what they want to
do on each pipeline stage in the inorder model) were able to improve performance by a nice
amount... The latest results for the inorder model process about 100k insts/second
(note: 58% is over the last time run on 64-bit pool machines at UM)
2011-02-12 10:14:52 -05:00
Gabe Black
0851580aad
Stats: Re update stats.
2011-02-07 19:23:13 -08:00
Gabe Black
2107258d24
X86: Add stats for the new x86 fs regressions.
2011-02-07 01:23:16 -08:00
Gabe Black
55df9e348c
X86: Add o3 regressions in SE mode.
...
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-05 00:16:09 -08:00
Korey Sewell
a48fe2729a
imported patch regression_updates
2011-02-04 00:09:22 -05:00
Gabe Black
54f88d84c2
Stats: Update the x86 stats to reflect changing stupd to a store and update.
2011-02-02 19:56:49 -08:00
Ali Saidi
f7885b8f26
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 16:30:06 -06:00
Ali Saidi
9b67f3723e
Stats: Update stats for previous set of patches.
2011-01-18 16:30:06 -06:00
Gabe Black
6fb521faba
SPARC: Update stats for the call r15 as source change.
2011-01-15 15:30:34 -08:00
Ali Saidi
1cfe2c8820
Stats: Fix stats for cumulative flags change.
2010-12-07 16:19:57 -08:00
Gabe Black
0e41d4e5ea
Stats: Update the O3 fetch stats for SPARC.
2010-11-15 19:37:15 -08:00
Ali Saidi
371110fb0a
Regressions: Update regressions for SIMD opclass changes
2010-11-15 14:04:05 -06:00
Ali Saidi
06c5283930
ARM: Update SE stats for TLB stats additions
2010-11-08 13:59:35 -06:00
Ali Saidi
fe300c6de2
ARM: Add full-system regressions
2010-11-08 13:58:25 -06:00
Ali Saidi
b4b6a2338a
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
2010-11-08 13:58:24 -06:00
Gabe Black
b53231e7fe
Ref output: Update refs for PCState change.
2010-10-31 00:07:48 -07:00
Steve Reinhardt
13a15c55a4
stats: update stats for previous cset
...
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
2010-09-21 23:07:35 -07:00
Steve Reinhardt
9e45ada171
stats: update stats for preceding coherence changes
...
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00
Ali Saidi
e6d3fe8a0c
ARM: Update regression tests for ldr/str microcode changes.
2010-08-25 19:10:42 -05:00
Ali Saidi
03584ad439
ALPHA: The previous O3 patch causes a slight stats change with fullsys.
2010-08-23 11:18:42 -05:00
Steve Reinhardt
0f8b5afd7a
tests: update reference config.ini files for previous cset
...
Rename 'responder_set' to 'use_default_range'.
2010-08-17 05:06:22 -07:00
Ali Saidi
1b73376b0b
ARM: Add regression tests
2010-07-27 01:03:44 -04:00
Korey Sewell
f2eba81f50
inorder: update regressions from RAS fix
2010-06-25 17:42:55 -04:00
Korey Sewell
0135cdab8d
inorder: update regressions
2010-06-24 15:34:21 -04:00
Korey Sewell
e17c41c176
inorder: update regressions
2010-06-23 18:21:44 -04:00
Steve Reinhardt
625854785b
stats: update stats for SC protocol change
...
Some subset of UpgradeReq messages shifted to the
new SCUpgradeReq type. Other than that there
are no significant differences.
2010-06-16 15:25:57 -07:00
m5test
744b59d6de
tests: Update O3 ref outputs to reflect Lisa's dist format change.
2010-06-06 18:39:10 -04:00
Ali Saidi
a990335b32
BPRED: Update one missing regression
2010-05-19 00:36:05 -04:00
Ali Saidi
e63c73b45d
BPRED: Update regressions for tournament predictor fix.
2010-05-13 23:45:59 -04:00
Gabe Black
8b0c83008e
X86: Update stats for the updated auxilliary vectors.
2010-05-03 00:45:01 -07:00
Korey Sewell
c90ee27283
inorder: update regressions for fwd-ing patch
2010-04-11 00:21:49 -04:00
Korey Sewell
941399728f
inorder: update twolf/vortex regressions
2010-03-27 02:21:22 -04:00
Korey Sewell
6364fbac39
inorder: update twolf regression
2010-03-23 00:14:52 -04:00
Korey Sewell
ef0fb9bee4
inorder: update vortex regression
2010-03-22 23:39:23 -04:00
Lisa Hsu
ee20a7c0bd
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 10:08:41 -08:00
Korey Sewell
a3c635f777
inorder: vortex alpha regression
2010-01-31 18:31:20 -05:00
Korey Sewell
81c9fdad24
inorder: twolf alpha regression
2010-01-31 18:31:14 -05:00
Nathan Binkert
14b5169750
tests: update statistics for change caused by vsyscall support in x86
...
Caused by a slight change in memory layout.
2009-11-08 20:15:23 -08:00
Nathan Binkert
5fe0762ee4
tests: update test for slight change due to the change in brk.
2009-10-24 10:53:58 -07:00
Nathan Binkert
9a8cb7db7e
python: Move more code into m5.util allow SCons to use that code.
...
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Gabe Black
70251bbb1a
X86: Update stats for new SSE instructions.
2009-08-17 22:27:30 -07:00
