stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
This commit is contained in:
Andreas Hansson
parent
0facc8e1ac
commit
cb9e208a4c
61 changed files with 22398 additions and 21805 deletions
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File diff suppressed because it is too large
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File diff suppressed because it is too large
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@ -4,11 +4,11 @@ sim_seconds 5.204983 # Nu
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sim_ticks 5204982530500 # Number of ticks simulated
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final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 181134 # Simulator instruction rate (inst/s)
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host_op_rate 347511 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 8731335326 # Simulator tick rate (ticks/s)
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host_mem_usage 804468 # Number of bytes of host memory used
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host_seconds 596.13 # Real time elapsed on the host
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host_inst_rate 107235 # Simulator instruction rate (inst/s)
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host_op_rate 205734 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 5169140013 # Simulator tick rate (ticks/s)
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host_mem_usage 810688 # Number of bytes of host memory used
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host_seconds 1006.93 # Real time elapsed on the host
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sim_insts 107979054 # Number of instructions simulated
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sim_ops 207160582 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
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@ -123,26 +123,13 @@ system.physmem.readPktSize::3 298 # Ca
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 512 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 48406 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 46736 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
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@ -175,7 +162,6 @@ system.physmem.rdQLenPdf::28 2 # Wh
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system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
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@ -208,15 +194,14 @@ system.physmem.wrQLenPdf::28 36 # Wh
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system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 40946729 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 52545479 # Sum of mem lat for all requests
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system.physmem.totQLat 40945522 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 52544272 # Sum of mem lat for all requests
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system.physmem.totBusLat 4050000 # Total cycles spent in databus access
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system.physmem.totBankLat 7548750 # Total cycles spent in bank access
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system.physmem.avgQLat 50551.52 # Average queueing delay per request
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system.physmem.avgQLat 50550.03 # Average queueing delay per request
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system.physmem.avgBankLat 9319.44 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 64870.96 # Average memory access latency
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system.physmem.avgMemAccLat 64869.47 # Average memory access latency
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system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
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@ -4,11 +4,11 @@ sim_seconds 0.269672 # Nu
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sim_ticks 269671683500 # Number of ticks simulated
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final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 125294 # Simulator instruction rate (inst/s)
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host_op_rate 125294 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 56139844 # Simulator tick rate (ticks/s)
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host_mem_usage 224468 # Number of bytes of host memory used
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host_seconds 4803.57 # Real time elapsed on the host
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host_inst_rate 149368 # Simulator instruction rate (inst/s)
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host_op_rate 149368 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 66926769 # Simulator tick rate (ticks/s)
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host_mem_usage 224496 # Number of bytes of host memory used
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host_seconds 4029.35 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
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@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 26294 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 1014 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 1014 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
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@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
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@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 384531397 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1096635147 # Sum of mem lat for all requests
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system.physmem.totQLat 383646750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests
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system.physmem.totBusLat 131400000 # Total cycles spent in databus access
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system.physmem.totBankLat 580703750 # Total cycles spent in bank access
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system.physmem.avgQLat 14632.09 # Average queueing delay per request
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system.physmem.avgBankLat 22096.79 # Average bank access latency per request
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system.physmem.totBankLat 580690000 # Total cycles spent in bank access
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system.physmem.avgQLat 14598.43 # Average queueing delay per request
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system.physmem.avgBankLat 22096.27 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 41728.89 # Average memory access latency
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system.physmem.avgMemAccLat 41694.70 # Average memory access latency
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system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
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@ -379,14 +364,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386
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system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 1042 # number of replacements
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system.cpu.l2cache.tagsinuse 22879.116549 # Cycle average of tags in use
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system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::writebacks 21684.482794 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 718.953898 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 475.679858 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor
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system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy
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@ -418,14 +403,14 @@ system.cpu.l2cache.overall_misses::total 26294 # nu
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system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1199043000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1199043000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 1669703000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 1714784000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1669703000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 1714784000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
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@ -453,14 +438,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.057631 #
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56219.195424 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56219.195424 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 65215.790675 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
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system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65599.457824 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 65215.790675 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34645117 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418280186 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452925303 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 933604040 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 933604040 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34645117 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1351884226 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::total 1386529343 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34645117 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1351884226 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::total 1386529343 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -504,25 +489,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41195.145065 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101401.257212 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91205.256343 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43773.632783 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43773.632783 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41195.145065 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53112.962166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52731.776945 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4093.423527 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 332210000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423527 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits
|
||||
|
|
@ -543,12 +528,12 @@ system.cpu.dcache.overall_misses::cpu.data 2179204 #
|
|||
system.cpu.dcache.overall_misses::total 2179204 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23175803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23175803000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29160484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29160484000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29160484000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29160484000 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -567,12 +552,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.014154
|
|||
system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12976.569635 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12976.569635 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13381.254807 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
|
||||
|
|
@ -601,12 +586,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 455395
|
|||
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3783295500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3783295500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6426949500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6426949500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -617,12 +602,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14885.311788 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14885.311788 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14112.911868 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.164572 # Nu
|
|||
sim_ticks 164572262000 # Number of ticks simulated
|
||||
final_tick 164572262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 164809 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 174150 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 47579904 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241928 # Number of bytes of host memory used
|
||||
host_seconds 3458.86 # Real time elapsed on the host
|
||||
host_inst_rate 185108 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 195599 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 53440170 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241944 # Number of bytes of host memory used
|
||||
host_seconds 3079.56 # Real time elapsed on the host
|
||||
sim_insts 570051585 # Number of instructions simulated
|
||||
sim_ops 602359791 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 47424 # Number of bytes read from this memory
|
||||
|
|
@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 27336 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 2538 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 2538 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 14742 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 3442 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
|
||||
|
|
@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 921366434 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1672075184 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 921339250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 1672034250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 136675000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 614033750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 33705.24 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22462.46 # Average bank access latency per request
|
||||
system.physmem.totBankLat 614020000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 33704.25 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 22461.95 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4999.82 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 61167.51 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 61166.02 # Average memory access latency
|
||||
system.physmem.avgRdBW 10.63 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 10.63 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -323,11 +308,11 @@ system.cpu.iq.issued_per_cycle::mean 1.967168 # Nu
|
|||
system.cpu.iq.issued_per_cycle::stdev 1.722204 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 68107234 20.75% 20.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 85141417 25.94% 46.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 76162034 23.21% 69.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 40819071 12.44% 82.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 85141419 25.94% 46.69% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 76162032 23.21% 69.90% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 40819070 12.44% 82.34% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 28853170 8.79% 91.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 14914630 4.54% 95.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 14914631 4.54% 95.68% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 5559324 1.69% 97.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 6732498 2.05% 99.42% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1901914 0.58% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -629,16 +614,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 743 #
|
|||
system.cpu.l2cache.overall_misses::cpu.data 26602 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 27345 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40442500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687360500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 727803000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 687347500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 727790000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1581776500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1581776500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40442500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2269137000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2309579500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 2269124000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 2309566500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40442500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2269137000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2309579500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 2269124000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 2309566500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 831 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 197598 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 198429 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -666,16 +651,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.894103
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.059811 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.061367 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54431.359354 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142872.687591 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 131041.231545 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 142869.985450 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 131038.890889 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72588.522785 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72588.522785 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84460.760651 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84460.285244 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54431.359354 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.488760 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84460.760651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85299.000075 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84460.285244 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -706,17 +691,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27336
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 741 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 26595 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27336 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149679 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627911476 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659061155 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310031171 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310031171 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149679 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937942647 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1969092326 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149679 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937942647 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1969092326 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31149092 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 627893373 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 659042465 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1310013362 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1310013362 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31149092 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1937906735 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1969055827 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31149092 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1937906735 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1969055827 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024312 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.027945 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -728,17 +713,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.061347
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.891697 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.061347 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42037.353576 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130705.969192 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118856.835888 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.992336 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.992336 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42037.353576 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72868.683850 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72032.935543 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42036.561404 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 130702.200874 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118853.465284 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60117.175072 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60117.175072 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42036.561404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72867.333521 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72031.600344 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 440669 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4091.484070 # Cycle average of tags in use
|
||||
|
|
@ -771,16 +756,16 @@ system.cpu.dcache.demand_misses::cpu.data 3718210 # n
|
|||
system.cpu.dcache.demand_misses::total 3718210 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 3718210 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 3718210 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073572500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5073572500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5073533500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5073533500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 40705228766 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 40705228766 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 337500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 337500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 45778801266 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 45778801266 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 45778801266 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 45778801266 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 45778762266 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 45778762266 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 45778762266 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 45778762266 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 131865640 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 131865640 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -803,16 +788,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.018473
|
|||
system.cpu.dcache.demand_miss_rate::total 0.018473 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.018473 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.018473 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.521697 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.521697 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14838.407635 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14838.407635 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12056.196805 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 12056.196805 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15340.909091 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15340.909091 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 12312.053721 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.053721 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 12312.053721 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 12312.043232 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12312.043232 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 12312.043232 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 148065 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 30 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 4947 # number of cycles access was blocked
|
||||
|
|
@ -841,14 +826,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 444768
|
|||
system.cpu.dcache.demand_mshr_misses::total 444768 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 444768 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 444768 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836417500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2836404500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2836404500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096422821 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096422821 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932840321 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6932840321 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932840321 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6932840321 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6932827321 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6932827321 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6932827321 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6932827321 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -857,14 +842,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002210
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002210 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.412219 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.412219 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14354.346429 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14354.346429 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16573.368104 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16573.368104 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.542991 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.542991 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15587.513762 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15587.513762 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.607292 # Nu
|
|||
sim_ticks 607292111000 # Number of ticks simulated
|
||||
final_tick 607292111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 91190 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 168022 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 62928697 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248736 # Number of bytes of host memory used
|
||||
host_seconds 9650.48 # Real time elapsed on the host
|
||||
host_inst_rate 88731 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 163492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 61232046 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 248756 # Number of bytes of host memory used
|
||||
host_seconds 9917.88 # Real time elapsed on the host
|
||||
sim_insts 880025277 # Number of instructions simulated
|
||||
sim_ops 1621493926 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 57664 # Number of bytes read from this memory
|
||||
|
|
@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 27359 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 2534 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 2534 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 26892 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 344 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 100 # What read queue length does an incoming req see
|
||||
|
|
@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 90448613 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 895548613 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 90421500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 895535250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 136795000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 668305000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3305.99 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 24427.25 # Average bank access latency per request
|
||||
system.physmem.totBankLat 668318750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 3305.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 24427.75 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 32733.24 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 32732.75 # Average memory access latency
|
||||
system.physmem.avgRdBW 2.88 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 2.88 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -235,22 +220,22 @@ system.cpu.fetch.rateDist::max_value 8 # Nu
|
|||
system.cpu.fetch.rateDist::total 1214221440 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.130483 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.200203 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 288175293 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 497913619 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 274106217 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 92482436 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.IdleCycles 288175297 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 497913615 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 274106209 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 92482444 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 61543875 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DecodedInsts 2343534245 # Number of instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 61543875 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 336850045 # Number of cycles rename is idle
|
||||
system.cpu.rename.IdleCycles 336850046 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 124204658 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 2567 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 303948664 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 387671631 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RunCycles 303948666 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 387671628 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2247678746 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 360 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 242705543 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 120202916 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.IQFullEvents 242705531 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 120202926 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 2618040036 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 5722358621 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 5722353197 # Number of integer rename lookups
|
||||
|
|
@ -259,11 +244,11 @@ system.cpu.rename.CommittedMaps 1886895258 # Nu
|
|||
system.cpu.rename.UndoneMaps 731144778 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 87 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 731406447 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 731406444 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 531670409 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 219217246 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 342048419 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 144614488 # Number of conflicting stores.
|
||||
system.cpu.memDep0.conflictingStores 144614487 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 1993488562 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 1783952231 # Number of instructions issued
|
||||
|
|
@ -275,12 +260,12 @@ system.cpu.iq.issued_per_cycle::samples 1214221440 # Nu
|
|||
system.cpu.iq.issued_per_cycle::mean 1.469215 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.421905 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 360233763 29.67% 29.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 364161192 29.99% 59.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 234288879 19.30% 78.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 141409866 11.65% 90.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 60623194 4.99% 95.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 39782569 3.28% 98.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 360233765 29.67% 29.67% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 364161190 29.99% 59.66% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 234288875 19.30% 78.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 141409873 11.65% 90.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 60623190 4.99% 95.59% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 39782570 3.28% 98.87% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 11078669 0.91% 99.78% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 2040416 0.17% 99.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 602892 0.05% 100.00% # Number of insts issued each cycle
|
||||
|
|
@ -368,7 +353,7 @@ system.cpu.iq.fp_inst_queue_writes 1776 # Nu
|
|||
system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 1740037802 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 245 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 210029942 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.forwLoads 210029946 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 112628288 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 39424 # Number of memory responses ignored because the instruction is squashed
|
||||
|
|
@ -404,8 +389,8 @@ system.cpu.iew.exec_stores 191706202 # Nu
|
|||
system.cpu.iew.exec_rate 1.454114 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 1725748007 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 1724635217 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1267063012 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1828799696 # num instructions consuming a value
|
||||
system.cpu.iew.wb_producers 1267063011 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 1828799692 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.419939 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.692839 # average fanout of values written-back
|
||||
|
|
@ -583,14 +568,14 @@ system.cpu.l2cache.overall_misses::total 27359 # nu
|
|||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46268500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 330234500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 376503000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134971000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1134971000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1134984000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1134984000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1465205500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1511474000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1465218500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1511487000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46268500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1465205500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1511474000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1465218500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1511487000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 918 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 203811 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 204729 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -620,14 +605,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.060649 #
|
|||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51352.386238 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72403.968428 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68931.343830 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.260127 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.260127 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51832.853816 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51832.853816 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 55245.951972 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 55246.427135 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51352.386238 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55378.543352 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 55245.951972 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55379.034697 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 55246.427135 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -649,17 +634,17 @@ system.cpu.l2cache.demand_mshr_misses::total 27359
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 901 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 26458 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 27359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35083215 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273211469 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308294684 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862598556 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862598556 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35083215 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135810025 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1170893240 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35083215 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135810025 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1170893240 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35082483 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 273207016 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 308289499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 862590617 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 862590617 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35082483 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1135797633 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1170880116 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35082483 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1135797633 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1170880116 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.022379 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.026679 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -671,35 +656,35 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.060649
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.981481 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058772 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060649 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38938.085461 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59901.659504 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56443.552545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.458282 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.458282 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38938.085461 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.793749 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42797.369787 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38937.273030 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59900.683184 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56442.603259 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39393.095721 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39393.095721 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38937.273030 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42928.325384 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42796.890091 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 446086 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4092.713768 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 452307982 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 452307978 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 450182 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1004.722494 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1004.722486 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 861652000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4092.713768 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999198 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999198 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 264368372 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 264368372 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 264368368 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 264368368 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 187939603 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 187939603 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 452307975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 452307975 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 452307975 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 452307975 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 452307971 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 452307971 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 452307971 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 452307971 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 211281 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 211281 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 246455 # number of WriteReq misses
|
||||
|
|
@ -710,20 +695,20 @@ system.cpu.dcache.overall_misses::cpu.data 457736 #
|
|||
system.cpu.dcache.overall_misses::total 457736 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3022618500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3022618500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119755500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4119755500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7142374000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7142374000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7142374000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7142374000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 264579653 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 264579653 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4119768500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4119768500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7142387000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7142387000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7142387000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7142387000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 264579649 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 264579649 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 452765711 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 452765711 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 452765711 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 452765711 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 452765707 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 452765707 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 452765707 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 452765707 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000799 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000799 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001310 # miss rate for WriteReq accesses
|
||||
|
|
@ -734,12 +719,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.001011
|
|||
system.cpu.dcache.overall_miss_rate::total 0.001011 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14306.153890 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 14306.153890 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.055669 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.055669 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15603.697328 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.697328 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15603.697328 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16716.108417 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 16716.108417 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 15603.725728 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 15603.725728 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 15603.725728 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked
|
||||
|
|
@ -768,12 +753,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 450191
|
|||
system.cpu.dcache.overall_mshr_misses::total 450191 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2528414500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2528414500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626209000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626209000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154623500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6154623500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154623500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6154623500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3626222000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3626222000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6154636500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6154636500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6154636500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6154636500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000770 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000770 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -784,12 +769,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000994
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000994 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12405.317025 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12405.317025 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.310374 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.310374 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.138472 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.138472 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14718.363139 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14718.363139 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13671.167349 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13671.167349 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.139855 # Nu
|
|||
sim_ticks 139855372500 # Number of ticks simulated
|
||||
final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 164436 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 164436 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57685897 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230388 # Number of bytes of host memory used
|
||||
host_seconds 2424.43 # Real time elapsed on the host
|
||||
host_inst_rate 118034 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 118034 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 41407532 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230404 # Number of bytes of host memory used
|
||||
host_seconds 3377.53 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 7328 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 47661305 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 197340055 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 47654000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 113038750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6504.00 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6503.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15425.59 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26929.59 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 26928.60 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128897344 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549956 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164447300 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120759327 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120759327 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128897344 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156309283 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 285206627 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128897344 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156309283 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 285206627 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -495,17 +480,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38373.725514 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43143.150485 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39313.244083 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38397.242289 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38397.242289 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38373.725514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39382.535399 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38920.118313 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.077334 # Nu
|
|||
sim_ticks 77333663500 # Number of ticks simulated
|
||||
final_tick 77333663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 196388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 196388 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40437661 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232448 # Number of bytes of host memory used
|
||||
host_seconds 1912.42 # Real time elapsed on the host
|
||||
host_inst_rate 154881 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 154881 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31891174 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232452 # Number of bytes of host memory used
|
||||
host_seconds 2424.92 # Real time elapsed on the host
|
||||
sim_insts 375574808 # Number of instructions simulated
|
||||
sim_ops 375574808 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
|
||||
|
|
@ -78,30 +78,17 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 7448 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2085 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 804 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 307 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4137 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2083 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 53873160 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 207011910 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 53845750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 206984500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 37240000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 115898750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 7233.24 # Average queueing delay per request
|
||||
system.physmem.avgQLat 7229.56 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15561.06 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27794.30 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 27790.61 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -198,18 +183,18 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 101791406 # DTB read hits
|
||||
system.cpu.dtb.read_hits 101791407 # DTB read hits
|
||||
system.cpu.dtb.read_misses 78057 # DTB read misses
|
||||
system.cpu.dtb.read_acv 48605 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 101869463 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 101869464 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 78427886 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1487 # DTB write misses
|
||||
system.cpu.dtb.write_acv 4 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 78429373 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 180219292 # DTB hits
|
||||
system.cpu.dtb.data_hits 180219293 # DTB hits
|
||||
system.cpu.dtb.data_misses 79544 # DTB misses
|
||||
system.cpu.dtb.data_acv 48609 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 180298836 # DTB accesses
|
||||
system.cpu.dtb.data_accesses 180298837 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 50219857 # ITB hits
|
||||
system.cpu.itb.fetch_misses 371 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
|
|
@ -230,23 +215,23 @@ system.cpu.workload.num_syscalls 215 # Nu
|
|||
system.cpu.numCycles 154667329 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 51106120 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 51106123 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 448669005 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 50250166 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 78764977 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 19721587 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 19721562 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 50219857 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 154473509 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::samples 154473487 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75708532 49.01% 49.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 75708510 49.01% 49.01% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -258,11 +243,11 @@ system.cpu.fetch.rateDist::8 35257809 22.82% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154473509 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 154473487 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 56459553 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 15066363 # Number of cycles decode is blocked
|
||||
system.cpu.decode.IdleCycles 56459555 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 15066339 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 74129391 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
|
||||
|
|
@ -271,15 +256,15 @@ system.cpu.decode.BranchMispred 4302 # Nu
|
|||
system.cpu.decode.DecodedInsts 444763327 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 59590768 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4877628 # Number of cycles rename is blocking
|
||||
system.cpu.rename.IdleCycles 59590769 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 403370 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 75043534 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 9691222 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 440325296 # Number of instructions processed by rename
|
||||
system.cpu.rename.UnblockCycles 9691221 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 440325297 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 8008636 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.LSQFullEvents 8008634 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RenamedOperands 287258509 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 578891151 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 306269628 # Number of integer rename lookups
|
||||
|
|
@ -288,35 +273,35 @@ system.cpu.rename.CommittedMaps 259532329 # Nu
|
|||
system.cpu.rename.UndoneMaps 27726180 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 27858963 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 27858970 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 408090088 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 966818 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 32383170 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 154473509 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 154473487 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28241568 18.28% 18.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 25850506 16.73% 35.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25557985 16.55% 51.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 24263587 15.71% 67.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21289313 13.78% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 8473783 5.49% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 28241547 18.28% 18.28% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 24263583 15.71% 67.27% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 21289316 13.78% 81.05% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 15479664 10.02% 91.07% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 8473780 5.49% 96.56% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154473509 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 154473487 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 34109 0.29% 0.29% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
|
||||
|
|
@ -347,12 +332,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5072339 42.83% 74.92% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 5072338 42.83% 74.92% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 155713729 38.76% 38.77% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued
|
||||
|
|
@ -381,21 +366,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 103367731 25.73% 80.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
|
||||
system.cpu.iq.rate 2.597191 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 11841746 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 11841745 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 633918884 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 260111127 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234694704 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_reads 633918862 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 260111129 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 241419354 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 241419353 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 15066516 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -409,10 +394,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 260879 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 2513908 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 367539 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 432875837 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 130046 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
|
||||
|
|
@ -423,42 +408,42 @@ system.cpu.iew.predictedTakenIncorrect 945508 # Nu
|
|||
system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 101918110 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 24785464 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 180347520 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_nop 24785465 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 46544583 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 78429410 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.574493 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 396666494 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 396036593 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 193534236 # num instructions producing a value
|
||||
system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 193534237 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 271064264 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 34241397 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 149606522 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 149606500 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55299818 36.96% 36.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 55299795 36.96% 36.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 22506360 15.04% 52.01% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13038976 8.72% 60.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 8182427 5.47% 73.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 5460458 3.65% 77.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 13038980 8.72% 60.72% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 11456393 7.66% 68.38% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 8182424 5.47% 73.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 3276425 2.19% 83.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 25215066 16.85% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149606522 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 149606500 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -469,12 +454,12 @@ system.cpu.commit.branches 44587533 # Nu
|
|||
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 25215066 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 557294459 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 870687579 # The number of ROB writes
|
||||
system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 193820 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 557294437 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 870687583 # The number of ROB writes
|
||||
system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 193842 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
|
||||
|
|
@ -483,18 +468,18 @@ system.cpu.cpi_total 0.411815 # CP
|
|||
system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 398027050 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 170092718 # number of integer regfile writes
|
||||
system.cpu.int_regfile_writes 170092717 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 2144 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1832.992748 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1832.992783 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 50214380 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 12334.654876 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1832.992748 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1832.992783 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 50214380 # number of ReadReq hits
|
||||
|
|
@ -509,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst 5477 # n
|
|||
system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5477 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 242175000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 242175000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 242175000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 242175000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 242175000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 242175000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 242151500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 242151500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 242151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 242151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 242151500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 242151500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 50219857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 50219857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 50219857 # number of demand (read+write) accesses
|
||||
|
|
@ -527,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000109
|
|||
system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44216.724484 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44216.724484 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44216.724484 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44216.724484 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44216.724484 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.433814 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44212.433814 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44212.433814 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
||||
|
|
@ -553,34 +538,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4071
|
|||
system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185126500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 185126500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185126500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 185126500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185126500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 185126500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 185116500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 185116500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 185116500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45474.453451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45474.453451 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45474.453451 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45474.453451 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.997052 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.997052 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.997052 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 4012.712180 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 4012.712247 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 831 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 4852 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.171270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 372.528713 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2978.555345 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 661.628123 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 372.528715 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2978.555395 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 661.628136 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy
|
||||
|
|
@ -609,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 7448 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3455 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3993 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7448 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174877500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51530000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 226407500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163360500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 174877500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 214890500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 389768000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 174877500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 214890500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 389768000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 174867500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 51533000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 226400500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163361000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 163361000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 174867500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 214894000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 389761500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 174867500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 214894000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 389761500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 990 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 5061 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -644,17 +629,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.902460 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.848686 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.954806 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.902460 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50615.774240 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59849.012776 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.715477 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.524904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.524904 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52331.901182 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50615.774240 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53816.804408 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52331.901182 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50612.879884 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59852.497096 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52456.093605 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52158.684547 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52158.684547 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52331.028464 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50612.879884 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53817.680942 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52331.028464 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7448
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3993 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7448 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131818904 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40942458 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172761362 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125001233 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125001233 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131818904 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943691 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 297762595 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131818904 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943691 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 297762595 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 131805705 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40944982 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 172750687 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 124998745 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 124998745 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131805705 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 165943727 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 297749432 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131805705 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 165943727 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 297749432 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869697 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.852796 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -696,37 +681,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.902460
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.848686 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954806 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.902460 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38153.083647 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47552.216028 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40028.119092 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.993934 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.993934 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38153.083647 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.650388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39978.866139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38149.263386 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47555.147503 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40025.645737 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39910.199553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39910.199553 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38149.263386 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41558.659404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39977.098818 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 780 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3297.047040 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 159960718 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3297.047136 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 159960719 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 38249.813008 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 38249.813247 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3297.047040 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 3297.047136 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.804943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.804943 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86459752 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86459752 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86459753 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86459753 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 73500960 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73500960 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 159960712 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 159960712 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 159960712 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 159960712 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 159960713 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 159960713 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 159960713 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 159960713 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses
|
||||
|
|
@ -735,24 +720,24 @@ system.cpu.dcache.demand_misses::cpu.data 21580 # n
|
|||
system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 21580 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 779488110 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 779488110 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 869475610 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 869475610 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 869475610 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 869475610 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86461563 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86461563 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 89990500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 89990500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566610 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 779566610 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 869557110 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 869557110 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 869557110 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 869557110 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86461564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86461564 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 159982292 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 159982292 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 159982292 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 159982292 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 159982293 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 159982293 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 159982293 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 159982293 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
|
||||
|
|
@ -761,19 +746,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000135
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39429.819920 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 39429.819920 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40290.806766 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40290.806766 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40290.806766 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28165 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49691.054666 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49691.054666 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.790784 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.790784 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40294.583411 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 28158 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.635499 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.624406 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -795,14 +780,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4182
|
|||
system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53863000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53863000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221119500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 221119500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221119500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 221119500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53866000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 53866000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167257000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 167257000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 221123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221123000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 221123000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -811,14 +796,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54407.070707 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54407.070707 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.103300 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.103300 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54410.101010 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54410.101010 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.809524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.809524 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.940220 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.068358 # Nu
|
|||
sim_ticks 68358106500 # Number of ticks simulated
|
||||
final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 148173 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 189432 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37097000 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250340 # Number of bytes of host memory used
|
||||
host_seconds 1842.69 # Real time elapsed on the host
|
||||
host_inst_rate 161957 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 207054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 40547923 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250356 # Number of bytes of host memory used
|
||||
host_seconds 1685.86 # Real time elapsed on the host
|
||||
sim_insts 273036725 # Number of instructions simulated
|
||||
sim_ops 349064449 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 7278 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 2 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 46727256 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 192182256 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 46720000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 36390000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 109065000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6420.34 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6419.35 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14985.57 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 26405.92 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 26404.92 # Average memory access latency
|
||||
system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -584,7 +569,7 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18773.979853
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18773.979853 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 3956.608159 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3956.608160 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 13151 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 5398 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.436273 # Average number of references to valid blocks.
|
||||
|
|
@ -702,19 +687,19 @@ system.cpu.l2cache.demand_mshr_misses::total 7278
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3019 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4259 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115050359 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62984754 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178035113 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115047807 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 62983881 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 178031688 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100922692 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100922692 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115050359 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163907446 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 278957805 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115050359 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163907446 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 278957805 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100921221 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100921221 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115047807 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -728,19 +713,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38108.764160 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42934.392638 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.828578 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36147.095989 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36147.095989 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38108.764160 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.960319 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.909728 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1413 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.627778 # Nu
|
|||
sim_ticks 627777658000 # Number of ticks simulated
|
||||
final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 102547 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 139655 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46502403 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263380 # Number of bytes of host memory used
|
||||
host_seconds 13499.90 # Real time elapsed on the host
|
||||
host_inst_rate 109787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 149515 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 49785649 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262368 # Number of bytes of host memory used
|
||||
host_seconds 12609.61 # Real time elapsed on the host
|
||||
sim_insts 1384370590 # Number of instructions simulated
|
||||
sim_ops 1885325342 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory
|
||||
|
|
@ -36,13 +36,13 @@ system.physmem.bw_total::cpu.data 48174508 # To
|
|||
system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 474966 # Total number of read requests seen
|
||||
system.physmem.writeReqs 66098 # Total number of write requests seen
|
||||
system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 30397824 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize()
|
||||
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
|
||||
system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q
|
||||
system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed
|
||||
system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed
|
||||
system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis
|
||||
system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis
|
||||
|
|
@ -85,26 +85,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 474966 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 66098 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 66098 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
|
||||
|
|
@ -137,7 +124,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2374030000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 15605837500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6703.98 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 32867.82 # Average bank access latency per request
|
||||
system.physmem.totBankLat 15605933750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6703.42 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 32868.02 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 44571.80 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 44571.44 # Average memory access latency
|
||||
system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -192,11 +177,11 @@ system.physmem.writeRowHits 45521 # Nu
|
|||
system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1160264.94 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 438315949 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 438315942 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target.
|
||||
|
|
@ -247,94 +232,94 @@ system.cpu.workload.num_syscalls 1411 # Nu
|
|||
system.cpu.numCycles 1255555317 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch
|
||||
system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename
|
||||
system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups
|
||||
system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed
|
||||
system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued
|
||||
system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available
|
||||
|
|
@ -365,12 +350,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued
|
||||
|
|
@ -393,90 +378,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Ty
|
|||
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued
|
||||
system.cpu.iq.rate 1.941304 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed
|
||||
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed
|
||||
system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 12468 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 322574295 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 423720933 # Number of stores executed
|
||||
system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 322574286 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 423720930 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 1.882449 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1347631532 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value
|
||||
system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 1347631579 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle
|
||||
system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -487,12 +472,12 @@ system.cpu.commit.branches 299634395 # Nu
|
|||
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 3802577661 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5740389540 # The number of ROB writes
|
||||
system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.rob.rob_reads 3802578575 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 5740389473 # The number of ROB writes
|
||||
system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
|
||||
|
|
@ -500,57 +485,57 @@ system.cpu.cpi 0.906950 # CP
|
|||
system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads
|
||||
system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 22740 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 333090009 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 31628 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 333121637 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 333090004 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 31630 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
|
||||
|
|
@ -565,40 +550,40 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 2899
|
|||
system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28729 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 28729 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 28729 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 28729 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 28729 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 28729 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386560499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 386560499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386560499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 386560499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386560499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 386560499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13455.410874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13455.410874 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13455.410874 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13455.410874 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 442184 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 32692.569161 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 1286.526974 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 50.225034 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31355.817153 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy
|
||||
|
|
@ -621,8 +606,8 @@ system.cpu.l2cache.overall_hits::total 1086653 # nu
|
|||
system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4306 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 4306 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses
|
||||
|
|
@ -632,23 +617,23 @@ system.cpu.l2cache.overall_misses::cpu.inst 2425 #
|
|||
system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 474991 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783784000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28917106500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174044000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3174044000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 31957828000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32091150500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 31958057000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 32091379500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 133322500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 31957828000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32091150500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 31958057000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 32091379500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 24421 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464706 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1489127 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 96321 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 96321 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4309 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 4309 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4311 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 4311 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 24421 # number of demand (read+write) accesses
|
||||
|
|
@ -671,16 +656,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099300
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307415 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.304161 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54978.350515 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.384486 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.495564 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48036.988271 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48036.988271 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70810.438607 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70716.549365 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48040.121075 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48040.121075 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67561.596957 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 67562.079071 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54978.350515 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.168620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67561.596957 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67626.653208 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 67562.079071 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -703,8 +688,8 @@ system.cpu.l2cache.overall_mshr_hits::total 25 #
|
|||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2421 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses::total 408891 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4306 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4306 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4308 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4308 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2421 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -713,19 +698,19 @@ system.cpu.l2cache.demand_mshr_misses::total 474966
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832468177 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43064306 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43064306 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2356932012 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2356932012 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103136612 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086263577 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26189400189 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103136612 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086263577 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103134689 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729007693 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832142382 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43084308 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43084308 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2357071286 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2357071286 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103134689 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086078979 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 26189213668 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103134689 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086078979 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 26189213668 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -739,73 +724,73 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.831062 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58379.047814 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58285.626676 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.036762 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58378.251022 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58284.829898 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35672.664185 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35672.664185 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.036762 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.375295 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.133471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 1533127 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 969955365 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 969955365 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 969955365 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 969955365 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 969955346 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2795405 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2795409 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses
|
||||
|
|
@ -816,16 +801,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002874
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked
|
||||
|
|
@ -838,30 +823,30 @@ system.cpu.dcache.writebacks::writebacks 96321 # nu
|
|||
system.cpu.dcache.writebacks::total 96321 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -870,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.042726 # Nu
|
|||
sim_ticks 42726055500 # Number of ticks simulated
|
||||
final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 156388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 156388 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 75637274 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259292 # Number of bytes of host memory used
|
||||
host_seconds 564.88 # Real time elapsed on the host
|
||||
host_inst_rate 89848 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 89848 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43455006 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 257260 # Number of bytes of host memory used
|
||||
host_seconds 983.23 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
|
||||
|
|
@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 165519 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 114011 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 62480 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 76428 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18694 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7913 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3855 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
|
||||
|
|
@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 4956 # Wh
|
|||
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1102 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 1 # Wh
|
|||
system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 7053628221 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9647149471 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 827595000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1765926250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42615.22 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10669.02 # Average bank access latency per request
|
||||
system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 42616.50 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10669.27 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 58284.24 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 58285.77 # Average memory access latency
|
||||
system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -188,7 +173,7 @@ system.physmem.busUtil 3.27 # Da
|
|||
system.physmem.avgRdQLen 0.23 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.42 # Average write queue length over time
|
||||
system.physmem.readRowHits 148856 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 71620 # Number of row buffer hits during writes
|
||||
system.physmem.writeRowHits 71619 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 152857.21 # Average gap between requests
|
||||
|
|
@ -256,9 +241,9 @@ system.cpu.execution_unit.executions 44777871 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 77185122 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 229327 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 81.422683 # Percentage of cycles cpu is active
|
||||
|
|
@ -295,12 +280,12 @@ system.cpu.stage4.idleCycles 39402909 # Nu
|
|||
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 84308 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1908.296965 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.296965 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
|
||||
|
|
@ -315,12 +300,12 @@ system.cpu.icache.demand_misses::cpu.inst 117106 # n
|
|||
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 117106 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1888398500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1888398500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1888398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1888398500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1888398500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1888398500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
|
||||
|
|
@ -333,12 +318,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009468
|
|||
system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16125.548648 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16125.548648 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16125.548648 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
||||
|
|
@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 86354
|
|||
system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336296000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1336296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336296000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1336296000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336921000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336921000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336921000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 1336921000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336921000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 1336921000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15474.627695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15474.627695 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15474.627695 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15481.865345 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15481.865345 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 131595 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30966.013927 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30966.013370 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27281.106507 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513793 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1666.393626 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 27281.106918 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513701 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1666.392751 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
|
||||
|
|
@ -415,17 +400,17 @@ system.cpu.l2cache.demand_misses::total 165519 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 454675000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513576000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1968251000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996247000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11996247000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 454675000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13509823000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13964498000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 454675000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13509823000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13964498000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -450,17 +435,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.569383 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 63975.657802 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54997.129465 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56839.869470 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91650.663529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91650.663529 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84367.945674 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 63975.657802 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85282.825796 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84367.945674 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -482,17 +467,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165519
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366278633 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1171229430 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537508063 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407065579 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407065579 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366278633 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11578295009 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11944573642 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366278633 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11578295009 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11944573642 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -504,17 +489,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51537.728015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42557.662512 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44400.718003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79509.405375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79509.405375 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51537.728015 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73089.759671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72164.365674 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 200249 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use
|
||||
|
|
@ -541,14 +526,14 @@ system.cpu.dcache.demand_misses::cpu.data 1135133 # n
|
|||
system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1135133 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3868219500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3868219500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76703201000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 76703201000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 80571420500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 80571420500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 80571420500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 80571420500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -565,19 +550,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.032535
|
|||
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.666283 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.666283 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73840.834877 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73840.834877 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 70979.718236 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5030029 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.221477 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -599,14 +584,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204345
|
|||
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908697000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908697000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268407000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268407000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14177104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14177104000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14177104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14177104000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -615,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31411.124825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31411.124825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85446.489762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85446.489762 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69378.276934 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.025578 # Nu
|
|||
sim_ticks 25577832000 # Number of ticks simulated
|
||||
final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 153227 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 217448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 55271946 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270340 # Number of bytes of host memory used
|
||||
host_seconds 462.76 # Real time elapsed on the host
|
||||
host_inst_rate 133487 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 48151664 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268312 # Number of bytes of host memory used
|
||||
host_seconds 531.19 # Real time elapsed on the host
|
||||
sim_insts 70907629 # Number of instructions simulated
|
||||
sim_ops 100626876 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
|
||||
|
|
@ -85,29 +85,16 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 128779 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 83944 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 312 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 83944 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
|
|
@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
|
||||
|
|
@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh
|
|||
system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 643885000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 1400135000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 24884.99 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10872.55 # Average bank access latency per request
|
||||
system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 24884.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 10873.20 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 40757.55 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 40758.05 # Average memory access latency
|
||||
system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -247,23 +232,23 @@ system.cpu.workload.num_syscalls 1946 # Nu
|
|||
system.cpu.numCycles 51155665 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
|
||||
system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
||||
system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
|
||||
system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
|
||||
system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
|
||||
system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
|
||||
|
|
@ -275,42 +260,42 @@ system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
|
||||
system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
|
||||
system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
|
||||
system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
|
||||
system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode
|
||||
system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
|
||||
system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
|
||||
system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
|
||||
system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename
|
||||
system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
|
||||
system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
|
||||
system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
|
||||
system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
|
||||
system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
|
||||
system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups
|
||||
system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
|
||||
system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
|
||||
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
|
||||
system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
|
||||
system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
|
||||
system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer
|
||||
system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
|
||||
system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
|
||||
system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
|
||||
system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores.
|
||||
system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
|
||||
system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
|
||||
|
|
@ -318,23 +303,23 @@ system.cpu.iq.iqSquashedInstsIssued 274406 # Nu
|
|||
system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle
|
||||
system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
|
||||
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
|
||||
|
|
@ -366,7 +351,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # at
|
|||
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
||||
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
||||
|
|
@ -405,15 +390,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
|
||||
system.cpu.iq.rate 2.096836 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads
|
||||
system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
|
||||
system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
|
||||
system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
|
||||
system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
|
||||
system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
|
||||
system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses
|
||||
system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
|
||||
system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
|
||||
system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
|
|
@ -427,32 +412,32 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 29 #
|
|||
system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
|
||||
system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions
|
||||
system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
|
||||
system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
||||
system.cpu.iew.exec_nop 9761 # number of nop insts executed
|
||||
system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 14602542 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 21344564 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 2.076700 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 53282087 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value
|
||||
system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
|
||||
|
|
@ -460,23 +445,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr
|
|||
system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle
|
||||
system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
|
||||
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
|
||||
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
|
||||
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
||||
|
|
@ -487,12 +472,12 @@ system.cpu.commit.branches 13741505 # Nu
|
|||
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
||||
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
|
||||
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
||||
system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.rob.rob_reads 149959303 # The number of ROB reads
|
||||
system.cpu.rob.rob_reads 149959530 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 224865260 # The number of ROB writes
|
||||
system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
|
||||
|
|
@ -500,19 +485,19 @@ system.cpu.cpi 0.721441 # CP
|
|||
system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 511661177 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 103341315 # number of integer regfile writes
|
||||
system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 804 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 688 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 28586 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
|
||||
|
|
@ -527,12 +512,12 @@ system.cpu.icache.demand_misses::cpu.inst 34686 # n
|
|||
system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 34686 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
|
||||
|
|
@ -545,12 +530,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.002970
|
|||
system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
|
||||
|
|
@ -571,34 +556,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 30945
|
|||
system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 95649 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy
|
||||
|
|
@ -631,19 +616,19 @@ system.cpu.l2cache.demand_misses::total 128855 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 128855 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -672,19 +657,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.667902 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -717,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128779
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -743,61 +728,61 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 158328 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44337922 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1707147 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -820,16 +805,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037076
|
|||
system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked
|
||||
|
|
@ -840,16 +825,16 @@ system.cpu.dcache.fast_writes 0 # nu
|
|||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 129109 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses
|
||||
|
|
@ -858,14 +843,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 162756
|
|||
system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -874,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu
|
|||
sim_ticks 993559170500 # Number of ticks simulated
|
||||
final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 148425 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 148425 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 81036604 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 464668 # Number of bytes of host memory used
|
||||
host_seconds 12260.62 # Real time elapsed on the host
|
||||
host_inst_rate 139940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 139940 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 76403951 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 449176 # Number of bytes of host memory used
|
||||
host_seconds 13004.03 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
|
||||
|
|
@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1018171 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
||||
|
|
@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see
|
||||
|
|
@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 44263 # Wh
|
|||
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see
|
||||
|
|
@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 5 # Wh
|
|||
system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 9795530000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 58644685000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 18298.46 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29934.41 # Average bank access latency per request
|
||||
system.physmem.totBankLat 58645221250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 18295.82 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 29934.69 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 53232.87 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 53230.51 # Average memory access latency
|
||||
system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -187,13 +172,13 @@ system.physmem.peakBW 12800.00 # Th
|
|||
system.physmem.busUtil 1.50 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.10 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 10.46 # Average write queue length over time
|
||||
system.physmem.readRowHits 770935 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 285714 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHits 770937 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 285715 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 333661.47 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 326540496 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits
|
||||
|
|
@ -205,22 +190,22 @@ system.cpu.dtb.fetch_hits 0 # IT
|
|||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 444796007 # DTB read hits
|
||||
system.cpu.dtb.read_hits 444796009 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4897078 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 449693085 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833351 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 449693087 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 160833358 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 162534655 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605629358 # DTB hits
|
||||
system.cpu.dtb.write_accesses 162534662 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 605629367 # DTB hits
|
||||
system.cpu.dtb.data_misses 6598382 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 612227740 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232025962 # ITB hits
|
||||
system.cpu.dtb.data_accesses 612227749 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 232025963 # ITB hits
|
||||
system.cpu.itb.fetch_misses 22 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 232025984 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 232025985 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -237,16 +222,16 @@ system.cpu.workload.num_syscalls 29 # Nu
|
|||
system.cpu.numCycles 1987118342 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File
|
||||
system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True).
|
||||
system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False).
|
||||
system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File
|
||||
system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
|
||||
system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File
|
||||
system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617884568 # Number of Address Generations
|
||||
system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic
|
||||
system.cpu.agen_unit.agens 617884569 # Number of Address Generations
|
||||
system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken.
|
||||
system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken).
|
||||
system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted
|
||||
|
|
@ -256,12 +241,12 @@ system.cpu.execution_unit.executions 1139371391 # Nu
|
|||
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
|
||||
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
||||
system.cpu.contextSwitches 1 # Number of context switches
|
||||
system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
||||
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
||||
system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.100703 # Percentage of cycles cpu is active
|
||||
system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed
|
||||
system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed.
|
||||
system.cpu.activity 79.100705 # Percentage of cycles cpu is active
|
||||
system.cpu.comLoads 444595663 # Number of Load instructions committed
|
||||
system.cpu.comStores 160728502 # Number of Store instructions committed
|
||||
system.cpu.comBranches 214632552 # Number of Branches instructions committed
|
||||
|
|
@ -279,66 +264,66 @@ system.cpu.cpi_total 1.091955 # CP
|
|||
system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread)
|
||||
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
||||
system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads
|
||||
system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed.
|
||||
system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks.
|
||||
system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232024853 # number of overall hits
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 232024854 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 1109 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859
|
|||
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 1926957 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 30901.189526 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.warmup_cycle 67146389751 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 15036.225587 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 34.907127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 15830.056812 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy
|
||||
|
|
@ -412,17 +397,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50231000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163632000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 83213863000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66179053000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 66179053000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 50231000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 149342685000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 149392916000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50231000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 149342685000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 149392916000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50226000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163468000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 83213694000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66176738000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 66176738000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 50226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 149340206000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 149390432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50226000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 149340206000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 149390432000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -447,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58470.314319 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.349673 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.489122 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84700.912199 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84700.912199 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 76231.743012 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 76231.743012 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -479,17 +464,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39565474 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68486082132 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68525647606 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56482752358 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56482752358 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39565474 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124968834490 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 125008399964 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39565474 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -501,51 +486,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46059.923166 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58160.796015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58151.974947 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72293.388777 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72293.388777 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 9107372 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.total_refs 593512840 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 65.139102 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593512880 # number of overall hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 156244082 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 156244082 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 593512840 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 593512840 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 593512840 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 593512840 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11811285 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 4484420 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 11811325 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 11811325 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 11811325 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 11811325 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288000500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 167288000500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 202511222000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 202511222000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -556,38 +541,38 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165
|
|||
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3693293 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses
|
||||
|
|
@ -596,14 +581,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111468
|
|||
system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -612,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.041622 # Nu
|
|||
sim_ticks 41622221000 # Number of ticks simulated
|
||||
final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 156492 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 156492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70874179 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228076 # Number of bytes of host memory used
|
||||
host_seconds 587.27 # Real time elapsed on the host
|
||||
host_inst_rate 75517 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 75517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34200879 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 228092 # Number of bytes of host memory used
|
||||
host_seconds 1216.99 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
|
||||
|
|
@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 4938 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1202 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3235 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1203 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 433 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 23375922 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122137172 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 23405750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 122167000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 74071250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4733.88 # Average queueing delay per request
|
||||
system.physmem.avgQLat 4739.93 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15000.25 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24734.14 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 24740.18 # Average memory access latency
|
||||
system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -288,12 +273,12 @@ system.cpu.stage4.idleCycles 29384711 # Nu
|
|||
system.cpu.stage4.runCycles 53859732 # Number of cycles 1+ instructions are processed.
|
||||
system.cpu.stage4.utilization 64.700694 # Percentage of cycles stage was utilized (processing insts).
|
||||
system.cpu.icache.replacements 7635 # number of replacements
|
||||
system.cpu.icache.tagsinuse 1492.649363 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1492.649326 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649363 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_blocks::cpu.inst 1492.649326 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits
|
||||
|
|
@ -308,12 +293,12 @@ system.cpu.icache.demand_misses::cpu.inst 11365 # n
|
|||
system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11365 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259189500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259189500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259189500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259189500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259189500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 259175500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 259175500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 259175500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 259175500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 259175500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 259175500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses
|
||||
|
|
@ -326,12 +311,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001141
|
|||
system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22805.939287 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22805.939287 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22805.939287 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22804.707435 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22804.707435 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22804.707435 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
||||
|
|
@ -352,34 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520
|
|||
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209613500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209613500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209613500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209613500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209613500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209613500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209599500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 209599500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 209599500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 209599500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 209599500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 209599500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22018.224790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22018.224790 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22018.224790 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22016.754202 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22016.754202 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22016.754202 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 2190.263467 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2190.263404 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6793 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.839012 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325234 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099221 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 1821.325190 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 351.099202 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy
|
||||
|
|
@ -408,17 +393,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 4938 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132557500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 132543500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 24069000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156626500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84092000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84092000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132557500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108161000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240718500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132557500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108161000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240718500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 156612500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 84148000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 132543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 108217000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 240760500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 132543500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 108217000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 240760500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -443,17 +428,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47443.629205 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47438.618468 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57035.545024 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48702.269900 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48833.914053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48833.914053 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48748.177400 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47443.629205 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50448.227612 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48748.177400 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 48697.916667 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48866.434379 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 48756.682868 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47438.618468 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50474.347015 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 48756.682868 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -473,17 +458,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97843336 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18812201 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116655537 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63127136 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63127136 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97843336 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81939337 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179782673 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97843336 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81939337 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179782673 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97826921 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18811852 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116638773 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63182194 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63182194 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97826921 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81994046 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 179820967 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97826921 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81994046 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 179820967 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -495,25 +480,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35019.089477 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44578.675355 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36273.487873 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36659.196283 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36659.196283 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35019.089477 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38217.974347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36407.993722 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35013.214388 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44577.848341 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36268.275187 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36691.169570 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36691.169570 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35013.214388 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38243.491604 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36415.748684 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1441.801688 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.801521 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801688 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_blocks::cpu.data 1441.801521 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits
|
||||
|
|
@ -534,12 +519,12 @@ system.cpu.dcache.overall_misses::cpu.data 8676 #
|
|||
system.cpu.dcache.overall_misses::total 8676 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 31383500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 345698500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 345698500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377082000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377082000 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 377432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 377432000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 377432000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 377432000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -558,17 +543,17 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000327
|
|||
system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54580 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42673.558820 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42673.558820 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43462.655602 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 43502.996773 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.647202 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
|
|
@ -592,12 +577,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2223
|
|||
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25092500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86109500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86109500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111202000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111202000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111202000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111258000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 111258000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111258000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 111258000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -608,12 +593,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52826.315789 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49261.727689 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49261.727689 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50023.391813 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50048.582996 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.023427 # Nu
|
|||
sim_ticks 23426793000 # Number of ticks simulated
|
||||
final_tick 23426793000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 213464 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 213464 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 59405864 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230136 # Number of bytes of host memory used
|
||||
host_seconds 394.35 # Real time elapsed on the host
|
||||
host_inst_rate 128339 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128339 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 35715987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230140 # Number of bytes of host memory used
|
||||
host_seconds 655.92 # Real time elapsed on the host
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_ops 84179709 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory
|
||||
|
|
@ -78,28 +78,15 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 5228 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.rdQLenPdf::0 3174 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1385 # What read queue length does an incoming req see
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3175 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 1384 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 549 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 106 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 28657456 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 133887456 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 28652250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 133882250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 26140000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 79090000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5481.53 # Average queueing delay per request
|
||||
system.physmem.avgQLat 5480.54 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 15128.16 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 25609.69 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 25608.69 # Average memory access latency
|
||||
system.physmem.avgRdBW 14.28 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 14.28 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -579,7 +564,7 @@ system.cpu.l2cache.sampled_refs 3590 # Sa
|
|||
system.cpu.l2cache.avg_refs 2.367688 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::writebacks 17.668263 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2005.213140 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 2005.213141 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 381.714191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.061194 # Average percentage of cache occupancy
|
||||
|
|
@ -674,17 +659,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5228
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106921693 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470923 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130392616 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567754 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567754 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106921693 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89038677 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 195960370 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106921693 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89038677 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 195960370 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106919101 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23470588 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 130389689 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65567128 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65567128 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106919101 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 89037716 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 195956817 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106919101 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 89037716 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 195956817 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.293388 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -696,17 +681,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.380523
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266446 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.380523 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.906924 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50913.065076 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37011.812660 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38456.160704 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38456.160704 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.906924 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41107.422438 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.855777 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34918.060418 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50912.338395 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37010.981834 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38455.793548 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38455.793548 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34918.060418 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41106.978763 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37482.176167 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 159 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1459.874578 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.074156 # Nu
|
|||
sim_ticks 74155951500 # Number of ticks simulated
|
||||
final_tick 74155951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 108940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 119280 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46885764 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245224 # Number of bytes of host memory used
|
||||
host_seconds 1581.63 # Real time elapsed on the host
|
||||
host_inst_rate 102580 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 112316 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 44148416 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 245240 # Number of bytes of host memory used
|
||||
host_seconds 1679.70 # Real time elapsed on the host
|
||||
sim_insts 172303021 # Number of instructions simulated
|
||||
sim_ops 188656503 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 3811 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 2809 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 787 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 17813284 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 103885784 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 17809500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 103882000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 19055000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 67017500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4674.18 # Average queueing delay per request
|
||||
system.physmem.avgQLat 4673.18 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17585.28 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27259.46 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 27258.46 # Average memory access latency
|
||||
system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -699,17 +684,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3811
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2060 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1751 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 3811 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78131980 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30985263 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109117243 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36314730 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36314730 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78131980 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67299993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 145431973 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78131980 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67299993 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 145431973 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 78130246 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30984758 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 109115004 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36313866 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36313866 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 78130246 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67298624 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 145428870 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 78130246 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67298624 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 145428870 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869845 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.560911 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -721,17 +706,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.639322
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.502439 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940892 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.639322 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37928.145631 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45904.093333 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39896.615356 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33749.749071 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33749.749071 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37928.145631 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38435.175899 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38161.105484 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37927.303883 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45903.345185 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39895.796709 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33748.946097 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33748.946097 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37927.303883 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38434.394061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38160.291262 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 57 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1410.136977 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.082836 # Nu
|
|||
sim_ticks 82836235000 # Number of ticks simulated
|
||||
final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 72340 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 121249 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 45372545 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 70076 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 117454 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 43952394 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 275820 # Number of bytes of host memory used
|
||||
host_seconds 1825.69 # Real time elapsed on the host
|
||||
host_seconds 1884.68 # Real time elapsed on the host
|
||||
sim_insts 132071192 # Number of instructions simulated
|
||||
sim_ops 221362961 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 5362 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 153 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 15727084 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 132185834 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 15721750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 26795000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 89663750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 2933.06 # Average queueing delay per request
|
||||
system.physmem.avgQLat 2932.07 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 16722.07 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 4997.20 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 24652.34 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 24651.34 # Average memory access latency
|
||||
system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -648,19 +633,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5362
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121268321 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645617 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139913938 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49242500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49242500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121268321 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67888117 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 189156438 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121268321 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67888117 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 189156438 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -674,19 +659,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35531.298271 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.901015 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36751.756764 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31667.202572 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31667.202572 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35531.298271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34832.281683 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35277.217083 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 56 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu
|
|||
sim_ticks 1870325497500 # Number of ticks simulated
|
||||
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2356651 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 69796056257 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 349376 # Number of bytes of host memory used
|
||||
host_seconds 26.80 # Real time elapsed on the host
|
||||
host_inst_rate 3609656 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 106905838632 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305660 # Number of bytes of host memory used
|
||||
host_seconds 17.50 # Real time elapsed on the host
|
||||
sim_insts 63151114 # Number of instructions simulated
|
||||
sim_ops 63151114 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
|
||||
|
|
@ -99,26 +99,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -151,7 +138,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -184,7 +170,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu
|
|||
sim_ticks 1829330593000 # Number of ticks simulated
|
||||
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1133415 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34534714924 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 347332 # Number of bytes of host memory used
|
||||
host_seconds 52.97 # Real time elapsed on the host
|
||||
host_inst_rate 3233953 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 98537371937 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303612 # Number of bytes of host memory used
|
||||
host_seconds 18.56 # Real time elapsed on the host
|
||||
sim_insts 60037737 # Number of instructions simulated
|
||||
sim_ops 60037737 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
|
||||
|
|
@ -89,26 +89,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -141,7 +128,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -174,7 +160,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -608,69 +593,5 @@ system.cpu.dcache.cache_copies 0 # nu
|
|||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 2042707 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu
|
|||
sim_ticks 912096763500 # Number of ticks simulated
|
||||
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1193297 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 17661410361 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435356 # Number of bytes of host memory used
|
||||
host_seconds 51.64 # Real time elapsed on the host
|
||||
host_inst_rate 1025890 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 15183699019 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 392232 # Number of bytes of host memory used
|
||||
host_seconds 60.07 # Real time elapsed on the host
|
||||
sim_insts 61625970 # Number of instructions simulated
|
||||
sim_ops 79343340 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
|
||||
|
|
@ -117,26 +117,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -169,7 +156,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -202,7 +188,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810264000 # Number of ticks simulated
|
||||
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1101050 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 42519386287 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435224 # Number of bytes of host memory used
|
||||
host_seconds 54.86 # Real time elapsed on the host
|
||||
host_inst_rate 1712706 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66139785958 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 391204 # Number of bytes of host memory used
|
||||
host_seconds 35.27 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
|
@ -100,26 +100,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -152,7 +139,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -185,7 +171,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
|
|||
sim_ticks 2332810256000 # Number of ticks simulated
|
||||
final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1011951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 39078665084 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 435224 # Number of bytes of host memory used
|
||||
host_seconds 59.70 # Real time elapsed on the host
|
||||
host_inst_rate 685945 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 882083 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 26489224850 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 391216 # Number of bytes of host memory used
|
||||
host_seconds 88.07 # Real time elapsed on the host
|
||||
sim_insts 60408639 # Number of instructions simulated
|
||||
sim_ops 77681819 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
|
|
@ -113,26 +113,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -165,7 +152,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -198,7 +184,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 5.112041 # Nu
|
|||
sim_ticks 5112040970500 # Number of ticks simulated
|
||||
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1816388 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 46471341970 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 582576 # Number of bytes of host memory used
|
||||
host_seconds 110.00 # Real time elapsed on the host
|
||||
host_inst_rate 1074050 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 583620 # Number of bytes of host memory used
|
||||
host_seconds 186.03 # Real time elapsed on the host
|
||||
sim_insts 199810242 # Number of instructions simulated
|
||||
sim_ops 409125913 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
|
||||
|
|
@ -97,26 +97,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -149,7 +136,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -182,7 +168,6 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
|||
sim_ticks 200409293000 # Number of ticks simulated
|
||||
final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19440889 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7408936081 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472492 # Number of bytes of host memory used
|
||||
host_seconds 27.05 # Real time elapsed on the host
|
||||
host_inst_rate 11931696 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4547176905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472520 # Number of bytes of host memory used
|
||||
host_seconds 44.07 # Real time elapsed on the host
|
||||
sim_insts 525869186 # Number of instructions simulated
|
||||
sim_ops 525869186 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
|
||||
|
|
@ -91,26 +91,13 @@ testsys.physmem.readPktSize::3 0 # Ca
|
|||
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -143,7 +130,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh
|
|||
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -176,7 +162,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh
|
|||
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -462,26 +447,13 @@ drivesys.physmem.readPktSize::3 0 # Ca
|
|||
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -514,7 +486,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh
|
|||
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -547,7 +518,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh
|
|||
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -751,11 +721,11 @@ sim_seconds 0.000407 # Nu
|
|||
sim_ticks 407365500 # Number of ticks simulated
|
||||
final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 12024534237 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9308365303 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472492 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_inst_rate 6212406894 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4809282801 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 472520 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 525940622 # Number of instructions simulated
|
||||
sim_ops 525940622 # Number of ops (including micro ops) simulated
|
||||
testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
|
||||
|
|
@ -835,26 +805,13 @@ testsys.physmem.readPktSize::3 0 # Ca
|
|||
testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
testsys.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
testsys.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
testsys.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -887,7 +844,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh
|
|||
testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -920,7 +876,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh
|
|||
testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
testsys.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
@ -1157,26 +1112,13 @@ drivesys.physmem.readPktSize::3 0 # Ca
|
|||
drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
drivesys.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
|
||||
|
|
@ -1209,7 +1151,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh
|
|||
drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -1242,7 +1183,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh
|
|||
drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
|
||||
drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
|
||||
drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
|
|||
sim_ticks 19476000 # Number of ticks simulated
|
||||
final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 78389 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 78368 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 238789679 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223680 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 1322 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1322 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4028719 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 223696 # Number of bytes of host memory used
|
||||
host_seconds 4.83 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 469 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2628216 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2627750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8401250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5603.87 # Average queueing delay per request
|
||||
system.physmem.avgQLat 5602.88 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17913.11 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28516.99 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 28515.99 # Average memory access latency
|
||||
system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -372,13 +357,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy
|
||||
|
|
@ -462,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -484,17 +469,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000016 # Number of seconds simulated
|
||||
sim_ticks 16030500 # Number of ticks simulated
|
||||
final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 16039500 # Number of ticks simulated
|
||||
final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76258 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76239 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 191753794 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225728 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 1336 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1336 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3362323 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 225744 # Number of bytes of host memory used
|
||||
host_seconds 4.77 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
|
||||
|
|
@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu
|
|||
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 486 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
|
||||
|
|
@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
|
|||
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
|
||||
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
|
||||
system.physmem.totGap 15817000 # Total gap between requests
|
||||
system.physmem.totGap 15803000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 486 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,28 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2909986 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2921750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2430000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8305000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5987.63 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6011.83 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17088.48 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28076.10 # Average memory access latency
|
||||
system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgMemAccLat 28100.31 # Average memory access latency
|
||||
system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s
|
||||
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
||||
system.physmem.busUtil 15.16 # Data bus utilization in percentage
|
||||
system.physmem.busUtil 15.15 # Data bus utilization in percentage
|
||||
system.physmem.avgRdQLen 0.85 # Average read queue length over time
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length over time
|
||||
system.physmem.readRowHits 396 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 32545.27 # Average gap between requests
|
||||
system.physmem.avgGap 32516.46 # Average gap between requests
|
||||
system.cpu.branchPred.lookups 2896 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect
|
||||
|
|
@ -227,7 +212,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 32062 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 32080 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -258,8 +243,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2753 # Number of cycles decode is running
|
||||
|
|
@ -384,7 +369,7 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 10806 # Type of FU issued
|
||||
system.cpu.iq.rate 0.337034 # Inst issue rate
|
||||
system.cpu.iq.rate 0.336845 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 118 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads
|
||||
|
|
@ -428,13 +413,13 @@ system.cpu.iew.exec_nop 86 # nu
|
|||
system.cpu.iew.exec_refs 3233 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1613 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1101 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.316699 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.316521 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 9710 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 5134 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 6919 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit
|
||||
|
|
@ -472,14 +457,14 @@ system.cpu.commit.bw_limited 0 # nu
|
|||
system.cpu.rob.rob_reads 25928 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 27481 # The number of ROB writes
|
||||
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 6372 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
|
||||
system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 12888 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 7343 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
||||
|
|
@ -487,14 +472,14 @@ system.cpu.fp_regfile_writes 2 # nu
|
|||
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
||||
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1869 # Total number of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor
|
||||
system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy
|
||||
system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits
|
||||
|
|
@ -507,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n
|
|||
system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 480 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses
|
||||
|
|
@ -525,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342
|
|||
system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313
|
|||
system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
||||
|
|
@ -598,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 486 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -631,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -661,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -683,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu
|
|||
sim_ticks 9350000 # Number of ticks simulated
|
||||
final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 146 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 146 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 570039 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224412 # Number of bytes of host memory used
|
||||
host_seconds 16.40 # Real time elapsed on the host
|
||||
host_inst_rate 55287 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 55271 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 216439769 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224436 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 272 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 1329022 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1328750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1360000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 5183750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4886.11 # Average queueing delay per request
|
||||
system.physmem.avgQLat 4885.11 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19057.90 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28944.01 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 28943.01 # Average memory access latency
|
||||
system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -571,13 +556,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 91.174754 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 27.924893 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy
|
||||
|
|
@ -655,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118288 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838816 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9957104 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114024 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114024 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118288 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952840 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11071128 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118288 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -677,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.967213 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40149.612903 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.666667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.666667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
|
|||
sim_ticks 13709000 # Number of ticks simulated
|
||||
final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51480 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64222 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 153638426 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239936 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 31817 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 39697 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 94976589 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 239960 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 394 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2508144 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1970000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7273750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6365.85 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6364.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 29827.14 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 29826.14 # Average memory access latency
|
||||
system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -624,13 +609,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
|
||||
|
|
@ -723,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -745,17 +730,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu
|
|||
sim_ticks 13709000 # Number of ticks simulated
|
||||
final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 58002 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 72354 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 173086159 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238920 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_inst_rate 36221 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 45190 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108117571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 238932 # Number of bytes of host memory used
|
||||
host_seconds 0.13 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 394 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2508144 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 1970000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7273750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6365.85 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6364.85 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18461.29 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 29827.14 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 29826.14 # Average memory access latency
|
||||
system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -579,13 +564,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy
|
||||
|
|
@ -678,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -700,17 +685,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu
|
|||
sim_ticks 19339000 # Number of ticks simulated
|
||||
final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 100636 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100592 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 334460805 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224316 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 54855 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 54842 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 182382541 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 224336 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5814 # Number of instructions simulated
|
||||
sim_ops 5814 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 455 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2650454 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2650000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2275000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 9033750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5825.17 # Average queueing delay per request
|
||||
system.physmem.avgQLat 5824.18 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19854.40 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 30679.57 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 30678.57 # Average memory access latency
|
||||
system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -358,13 +343,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy
|
||||
|
|
@ -448,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -470,17 +455,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 17026500 # Number of ticks simulated
|
||||
final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76348 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 251939378 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226380 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 44899 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 44889 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 148205995 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226388 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
sim_insts 5156 # Number of instructions simulated
|
||||
sim_ops 5156 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 478 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2863474 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2863000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2390000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 9363750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5990.53 # Average queueing delay per request
|
||||
system.physmem.avgQLat 5989.54 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19589.44 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 30579.97 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 30578.97 # Average memory access latency
|
||||
system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -556,13 +541,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy
|
||||
|
|
@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu
|
|||
sim_ticks 14724500 # Number of ticks simulated
|
||||
final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 87376 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87343 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 221965921 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222644 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 62176 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 62167 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 158021685 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222660 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 446 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2286195 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2285750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2230000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8263750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 5126.00 # Average queueing delay per request
|
||||
system.physmem.avgQLat 5125.00 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 18528.59 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 28654.59 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 28653.59 # Average memory access latency
|
||||
system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -553,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy
|
||||
|
|
@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13080769 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509277 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590046 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332772 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332772 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13080769 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842049 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17922818 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13080769 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17922818 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 16783500 # Number of ticks simulated
|
||||
final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 84096 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 84062 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 264753473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230292 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_inst_rate 48421 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 48416 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152524495 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230316 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 423 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2673172 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2672750 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2115000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8208750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6319.56 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6318.56 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19406.03 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 30725.58 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 30724.59 # Average memory access latency
|
||||
system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy
|
||||
|
|
@ -433,17 +418,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -455,17 +440,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000015 # Nu
|
|||
sim_ticks 15468000 # Number of ticks simulated
|
||||
final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 31666 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 57357 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91020367 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241544 # Number of bytes of host memory used
|
||||
host_inst_rate 31901 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 57781 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 91692634 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 241568 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9746 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 451 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 1899951 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 1899500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2255000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 9006250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4212.75 # Average queueing delay per request
|
||||
system.physmem.avgQLat 4211.75 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 19969.51 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 29182.26 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 29181.26 # Average memory access latency
|
||||
system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -536,13 +521,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy
|
||||
|
|
@ -626,17 +611,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -648,17 +633,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 24473000 # Number of ticks simulated
|
||||
final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 4068 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 4068 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 7811345 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226312 # Number of bytes of host memory used
|
||||
host_seconds 3.13 # Real time elapsed on the host
|
||||
host_inst_rate 87264 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 87257 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 167537445 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226344 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
sim_insts 12745 # Number of instructions simulated
|
||||
sim_ops 12745 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
|
||||
|
|
@ -78,29 +78,16 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 970 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 22646466 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 22645500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 4850000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 25973750 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 23346.87 # Average queueing delay per request
|
||||
system.physmem.avgQLat 23345.88 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 26777.06 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 55123.93 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 55122.94 # Average memory access latency
|
||||
system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -717,13 +702,13 @@ system.cpu.icache.no_allocate_misses 0 # Nu
|
|||
system.cpu.l2cache.replacements::0 0 # number of replacements
|
||||
system.cpu.l2cache.replacements::1 0 # number of replacements
|
||||
system.cpu.l2cache.replacements::total 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy
|
||||
|
|
@ -807,17 +792,17 @@ system.cpu.l2cache.demand_mshr_misses::total 970
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -829,17 +814,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements::0 0 # number of replacements
|
||||
system.cpu.dcache.replacements::1 0 # number of replacements
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu
|
|||
sim_ticks 23146500 # Number of ticks simulated
|
||||
final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 62448 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 62442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 95315643 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230224 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_inst_rate 95077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95070 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 145124480 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 230244 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 436 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 2156686 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 2156250 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2180000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 7727500 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 4946.53 # Average queueing delay per request
|
||||
system.physmem.avgQLat 4945.53 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17723.62 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 27670.15 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 27669.15 # Average memory access latency
|
||||
system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy
|
||||
|
|
@ -430,17 +415,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -452,17 +437,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000024 # Nu
|
|||
sim_ticks 23775500 # Number of ticks simulated
|
||||
final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 69212 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69204 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 113962469 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232268 # Number of bytes of host memory used
|
||||
host_inst_rate 69027 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 69023 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 113671122 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 232284 # Number of bytes of host memory used
|
||||
host_seconds 0.21 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 483 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
|
||||
|
|
@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 4632480 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 4632000 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 2415000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 8566250 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 9591.06 # Average queueing delay per request
|
||||
system.physmem.avgQLat 9590.06 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 17735.51 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 32326.56 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 32325.57 # Average memory access latency
|
||||
system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -533,13 +518,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.inst 189.932236 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_blocks::cpu.data 34.709985 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy
|
||||
|
|
@ -623,17 +608,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099263 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042283 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141546 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145788 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145788 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099263 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188071 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 21287334 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099263 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188071 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 21287334 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -645,17 +630,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38985.901786 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63160.671875 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42853.865000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.253012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.253012 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu
|
|||
sim_ticks 105801500 # Number of ticks simulated
|
||||
final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 99938 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 99937 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 10207562 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247464 # Number of bytes of host memory used
|
||||
host_seconds 10.37 # Real time elapsed on the host
|
||||
host_inst_rate 173787 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 173787 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 17750545 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247480 # Number of bytes of host memory used
|
||||
host_seconds 5.96 # Real time elapsed on the host
|
||||
sim_insts 1035849 # Number of instructions simulated
|
||||
sim_ops 1035849 # Number of ops (including micro ops) simulated
|
||||
system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory
|
||||
|
|
@ -59,7 +59,7 @@ system.physmem.bw_total::cpu3.data 7863783 # To
|
|||
system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 661 # Total number of read requests seen
|
||||
system.physmem.writeReqs 0 # Total number of write requests seen
|
||||
system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady
|
||||
system.physmem.bytesRead 42240 # Total number of bytes read from memory
|
||||
system.physmem.bytesWritten 0 # Total number of bytes written to memory
|
||||
system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize()
|
||||
|
|
@ -108,26 +108,13 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 661 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 71 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
|
||||
|
|
@ -160,7 +147,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -193,15 +179,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 4077160 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 4076500 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 3305000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 13310000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 6168.17 # Average queueing delay per request
|
||||
system.physmem.avgQLat 6167.17 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 20136.16 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 31304.33 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 31303.33 # Average memory access latency
|
||||
system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -2117,17 +2102,17 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279
|
|||
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency
|
||||
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.replacements 0 # number of replacements
|
||||
system.l2c.tagsinuse 425.230692 # Cycle average of tags in use
|
||||
system.l2c.tagsinuse 425.230696 # Cycle average of tags in use
|
||||
system.l2c.total_refs 1445 # Total number of references to valid blocks.
|
||||
system.l2c.sampled_refs 527 # Sample count of references to valid blocks.
|
||||
system.l2c.avg_refs 2.741935 # Average number of references to valid blocks.
|
||||
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor
|
||||
system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor
|
||||
|
|
@ -2409,43 +2394,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n
|
|||
system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
||||
system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13752787 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705044 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257064 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230755 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86253 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_latency::total 21722661 # number of ReadReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838755 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607510 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.ReadExReq_mshr_miss_latency::total 6413333 # number of ReadExReq MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.inst 13752787 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu0.data 7952102 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.inst 3257064 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu1.data 1417011 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.inst 230755 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.inst 86253 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::cpu3.data 663761 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.demand_mshr_miss_latency::total 28135994 # number of demand (read+write) MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.inst 13752787 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu0.data 7952102 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.inst 3257064 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu1.data 1417011 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.inst 230755 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles
|
||||
system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses
|
||||
|
|
@ -2483,43 +2468,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667
|
|||
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
||||
system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency
|
||||
system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency
|
||||
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency
|
||||
system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency
|
||||
system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency
|
||||
system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu
|
|||
sim_ticks 100000000000 # Number of ticks simulated
|
||||
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 29045358432 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 222412 # Number of bytes of host memory used
|
||||
host_seconds 3.44 # Real time elapsed on the host
|
||||
host_tick_rate 31852968745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 226592 # Number of bytes of host memory used
|
||||
host_seconds 3.14 # Real time elapsed on the host
|
||||
system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory
|
||||
system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory
|
||||
|
|
@ -66,37 +66,24 @@ system.physmem.readPktSize::3 0 # Ca
|
|||
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::6 3333400 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::7 0 # Categorize read packet sizes
|
||||
system.physmem.readPktSize::8 0 # Categorize read packet sizes
|
||||
system.physmem.writePktSize::0 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::7 0 # categorize write packet sizes
|
||||
system.physmem.writePktSize::8 0 # categorize write packet sizes
|
||||
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
|
||||
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
|
||||
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
||||
system.physmem.writePktSize::6 0 # Categorize write packet sizes
|
||||
system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
||||
|
|
@ -118,7 +105,6 @@ system.physmem.rdQLenPdf::28 0 # Wh
|
|||
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
||||
|
|
@ -151,15 +137,14 @@ system.physmem.wrQLenPdf::28 0 # Wh
|
|||
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
||||
system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests
|
||||
system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays
|
||||
system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests
|
||||
system.physmem.totBusLat 16667000000 # Total cycles spent in databus access
|
||||
system.physmem.totBankLat 46722610000 # Total cycles spent in bank access
|
||||
system.physmem.avgQLat 1834.67 # Average queueing delay per request
|
||||
system.physmem.avgQLat 1833.68 # Average queueing delay per request
|
||||
system.physmem.avgBankLat 14016.50 # Average bank access latency per request
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
||||
system.physmem.avgMemAccLat 20851.17 # Average memory access latency
|
||||
system.physmem.avgMemAccLat 20850.18 # Average memory access latency
|
||||
system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
|
||||
system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s
|
||||
|
|
@ -278,9 +263,9 @@ system.monitor.writeBandwidthHist::total 100 # Hi
|
|||
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
|
||||
system.monitor.totalWrittenBytes 0 # Number of bytes written
|
||||
system.monitor.readLatencyHist::samples 3333399 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency
|
||||
system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency
|
||||
system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency
|
||||
system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency
|
||||
system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency
|
||||
system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency
|
||||
system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency
|
||||
|
|
|
|||
Loading…
Reference in a new issue