cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
754 lines
86 KiB
Plaintext
754 lines
86 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000015 # Number of seconds simulated
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sim_ticks 15468000 # Number of ticks simulated
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final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 31901 # Simulator instruction rate (inst/s)
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host_op_rate 57781 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 91692634 # Simulator tick rate (ticks/s)
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host_mem_usage 241568 # Number of bytes of host memory used
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host_seconds 0.17 # Real time elapsed on the host
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sim_insts 5380 # Number of instructions simulated
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sim_ops 9746 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
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system.physmem.bytes_read::total 28736 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 449 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1253685027 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 604085855 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1857770882 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1253685027 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1253685027 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1253685027 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 604085855 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1857770882 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 451 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 28736 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 49 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 26 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 36 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 34 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 8 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 32 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 11 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 5 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 26 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 15452000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 451 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 1899500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests
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system.physmem.totBusLat 2255000 # Total cycles spent in databus access
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system.physmem.totBankLat 9006250 # Total cycles spent in bank access
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system.physmem.avgQLat 4211.75 # Average queueing delay per request
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system.physmem.avgBankLat 19969.51 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 29181.26 # Average memory access latency
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system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 14.51 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.85 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 333 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 34261.64 # Average gap between requests
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system.cpu.branchPred.lookups 2995 # Number of BP lookups
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system.cpu.branchPred.condPredicted 2995 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 2485 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 793 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 31.911469 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 30937 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 8904 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14405 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2995 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 3911 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2416 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 3684 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 18552 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.371173 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.873073 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 14740 79.45% 79.45% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 189 1.02% 80.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 154 0.83% 81.30% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 193 1.04% 82.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 163 0.88% 83.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 168 0.91% 84.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 265 1.43% 85.55% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 160 0.86% 86.42% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2520 13.58% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 18552 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.096810 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.465624 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 9434 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 3628 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 3523 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1823 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 24308 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1823 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 9778 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 3309 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 767 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 22819 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 24896 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 54742 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 54726 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 11061 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 13835 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 31 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 2054 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2204 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1750 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 20351 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 17307 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 9863 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 23 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 18552 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.932891 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.792260 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 13164 70.96% 70.96% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1399 7.54% 78.50% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 1053 5.68% 84.17% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 693 3.74% 87.91% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 728 3.92% 91.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 621 3.35% 95.18% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 594 3.20% 98.38% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 258 1.39% 99.77% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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|
system.cpu.iq.issued_per_cycle::total 18552 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 134 76.57% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 20 11.43% 88.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 21 12.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 13916 80.41% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 1905 11.01% 91.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1482 8.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 17307 # Type of FU issued
|
|
system.cpu.iq.rate 0.559427 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 175 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010112 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 53542 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 30256 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 15949 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 17474 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 160 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 815 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1823 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 20386 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2204 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1750 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 607 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 663 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 16378 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 929 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3145 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1625 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1365 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.529398 # Inst execution rate
|
|
system.cpu.iew.wb_sent 16147 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 15953 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 10136 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 15661 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.515661 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.647213 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 10639 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 16729 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.582581 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.458500 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 13195 78.88% 78.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1327 7.93% 86.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 118 0.71% 98.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 16729 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
|
system.cpu.commit.committedOps 9746 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 1987 # Number of memory references committed
|
|
system.cpu.commit.loads 1052 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1208 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 9652 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 36893 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 42622 # The number of ROB writes
|
|
system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
|
system.cpu.committedOps 9746 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
|
system.cpu.cpi 5.750372 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 5.750372 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.173902 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.173902 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 28821 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 17168 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
|
system.cpu.misc_regfile_reads 7143 # number of misc regfile reads
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 144.824422 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1475 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 144.824422 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.070715 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.070715 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1475 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1475 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 399 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 20611500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 20611500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 20611500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 20611500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 20611500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 20611500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1874 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1874 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1874 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1874 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1874 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1874 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212914 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51657.894737 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 51657.894737 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 51657.894737 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 51657.894737 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 51657.894737 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 72 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 451 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 15.643836 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 83.496642 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.020385 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.020385 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2284 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 127 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 127 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 203 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 203 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 203 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 203 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 6648000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 6648000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4218500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 4218500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 10866500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 10866500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2487 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2487 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2487 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2487 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081830 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.081830 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.081624 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.081624 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.081624 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.081624 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52346.456693 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 52346.456693 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55506.578947 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55506.578947 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 53529.556650 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53529.556650 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 53529.556650 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.600000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 72 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 72 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3962500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3962500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4066500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4066500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8029000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 8029000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8029000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 8029000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046392 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046392 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.059509 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059509 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.059509 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55034.722222 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55034.722222 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53506.578947 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53506.578947 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54250 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54250 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
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