cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
613 lines
70 KiB
Text
613 lines
70 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.269672 # Number of seconds simulated
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sim_ticks 269671683500 # Number of ticks simulated
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final_tick 269671683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 149368 # Simulator instruction rate (inst/s)
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host_op_rate 149368 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 66926769 # Simulator tick rate (ticks/s)
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host_mem_usage 224496 # Number of bytes of host memory used
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host_seconds 4029.35 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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sim_ops 601856964 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1628992 # Number of bytes read from this memory
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system.physmem.bytes_read::total 1682816 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 53824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 53824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 64896 # Number of bytes written to this memory
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system.physmem.bytes_written::total 64896 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 841 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 25453 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 199591 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 6040649 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6240240 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 199591 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 199591 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 240648 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 240648 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 240648 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 199591 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 6040649 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6480888 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 26294 # Total number of read requests seen
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system.physmem.writeReqs 1014 # Total number of write requests seen
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system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 1682816 # Total number of bytes read from memory
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system.physmem.bytesWritten 64896 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 1682816 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 269671631500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 26294 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 1014 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 16680 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 6777 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 1890 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 383646750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 1095736750 # Sum of mem lat for all requests
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system.physmem.totBusLat 131400000 # Total cycles spent in databus access
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system.physmem.totBankLat 580690000 # Total cycles spent in bank access
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system.physmem.avgQLat 14598.43 # Average queueing delay per request
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system.physmem.avgBankLat 22096.27 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 41694.70 # Average memory access latency
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system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.24 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.05 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 12.19 # Average write queue length over time
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system.physmem.readRowHits 16315 # Number of row buffer hits during reads
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system.physmem.writeRowHits 296 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
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system.physmem.avgGap 9875187.91 # Average gap between requests
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system.cpu.branchPred.lookups 86405403 # Number of BP lookups
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system.cpu.branchPred.condPredicted 81476373 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 44774039 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 77.410930 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 114517881 # DTB read hits
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system.cpu.dtb.read_misses 2631 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 114520512 # DTB read accesses
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system.cpu.dtb.write_hits 39453501 # DTB write hits
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system.cpu.dtb.write_misses 2302 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 39455803 # DTB write accesses
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system.cpu.dtb.data_hits 153971382 # DTB hits
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system.cpu.dtb.data_misses 4933 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 153976315 # DTB accesses
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system.cpu.itb.fetch_hits 24997849 # ITB hits
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system.cpu.itb.fetch_misses 22 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 24997871 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 539343368 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 49180751 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 541064074 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 1004918920 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 255159834 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 154928367 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 34132403 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 2205624 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 36338027 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 26209890 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 58.096302 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 412128439 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 535764686 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 296132 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 50809772 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 488533596 # Number of cycles cpu stages are processed.
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system.cpu.activity 90.579328 # Percentage of cycles cpu is active
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system.cpu.comLoads 114514042 # Number of Load instructions committed
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system.cpu.comStores 39451321 # Number of Store instructions committed
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system.cpu.comBranches 62547159 # Number of Branches instructions committed
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system.cpu.comNops 36304520 # Number of Nop instructions committed
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system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
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system.cpu.comInts 349039879 # Number of Integer instructions committed
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system.cpu.comFloats 24 # Number of Floating Point instructions committed
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system.cpu.committedInsts 601856964 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
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system.cpu.cpi 0.896132 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.896132 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.115907 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.115907 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 200616262 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 338727106 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 62.803610 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 228924009 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 310419359 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 57.555053 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 197778592 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 341564776 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 63.329744 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 427964982 # Number of cycles 0 instructions are processed.
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|
system.cpu.stage3.runCycles 111378386 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 20.650738 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 192544683 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 346798685 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 64.300167 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 30 # number of replacements
|
|
system.cpu.icache.tagsinuse 729.833784 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 24996815 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 29236.040936 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 729.833784 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 24996815 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 24996815 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 24996815 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 24996815 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 24996815 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 24996815 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1034 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1034 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1034 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1034 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1034 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1034 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55838000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 55838000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 55838000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 55838000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 55838000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 55838000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 24997849 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 24997849 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 24997849 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 24997849 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 24997849 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 24997849 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54001.934236 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 54001.934236 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 54001.934236 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54001.934236 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 54001.934236 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 179 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 179 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 179 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 179 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 179 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46086000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 46086000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46086000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 46086000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46086000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 46086000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53901.754386 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53901.754386 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53901.754386 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 53901.754386 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1042 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 22879.116891 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 21684.482898 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 718.953897 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 475.680097 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.698215 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 436887 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 436887 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 232860 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 232860 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 429942 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 429956 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 429942 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 429956 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 841 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 4125 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4966 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 21328 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 21328 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 841 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 25453 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 26294 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 26294 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45081000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470660000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 515741000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1198171500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 1198171500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 45081000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 1668831500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 1713912500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 45081000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 1668831500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 1713912500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 436887 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 436887 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 254188 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 254188 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983626 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.020501 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.024577 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.083906 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.083906 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983626 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.055892 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.057631 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53604.042806 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.393939 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 103854.409988 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56178.333646 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56178.333646 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 65182.646231 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53604.042806 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65565.218245 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 65182.646231 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1014 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1014 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 841 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 4125 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4966 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 21328 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 21328 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 841 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 25453 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 26294 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34644438 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418276481 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452920919 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932715801 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932715801 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34644438 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350992282 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 1385636720 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34644438 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350992282 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 1385636720 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.083906 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.083906 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41194.337693 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.359030 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91204.373540 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43731.986168 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43731.986168 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41194.337693 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53077.919381 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52697.829163 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 451299 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4093.423689 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 151786159 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 333.306600 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4093.423689 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114120811 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114120811 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 37665348 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 37665348 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 151786159 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 151786159 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 151786159 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 151786159 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 393231 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 393231 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1785973 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1785973 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2179204 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2179204 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2179204 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2179204 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984681000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5984681000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23170641500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 23170641500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 29155322500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 29155322500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 29155322500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 29155322500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15219.250263 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 15219.250263 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.679613 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.679613 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 13378.886281 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.886281 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 13378.886281 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 191152 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 6083 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.423968 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 436887 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191999 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 191999 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531810 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1531810 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1723809 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1723809 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1723809 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1723809 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643654000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643654000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782424000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782424000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6426078000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6426078000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6426078000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6426078000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.343961 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.343961 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.882886 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.882886 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.998144 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.998144 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|