cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
785 lines
90 KiB
Text
785 lines
90 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.082836 # Number of seconds simulated
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sim_ticks 82836235000 # Number of ticks simulated
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final_tick 82836235000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 70076 # Simulator instruction rate (inst/s)
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host_op_rate 117454 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 43952394 # Simulator tick rate (ticks/s)
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host_mem_usage 275820 # Number of bytes of host memory used
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host_seconds 1884.68 # Real time elapsed on the host
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sim_insts 132071192 # Number of instructions simulated
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sim_ops 221362961 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 218368 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 124544 # Number of bytes read from this memory
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system.physmem.bytes_read::total 342912 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 218368 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 218368 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3412 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1946 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5358 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2636141 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1503497 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 4139638 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2636141 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2636141 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2636141 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1503497 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4139638 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5362 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 5515 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 342912 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 342912 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 153 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 275 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 321 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 274 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 367 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 377 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 379 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 371 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 376 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 367 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 353 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 361 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 338 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 355 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 248 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 82836206000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 5362 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 4169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 943 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 199 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 15721750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 132180500 # Sum of mem lat for all requests
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system.physmem.totBusLat 26795000 # Total cycles spent in databus access
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system.physmem.totBankLat 89663750 # Total cycles spent in bank access
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system.physmem.avgQLat 2932.07 # Average queueing delay per request
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system.physmem.avgBankLat 16722.07 # Average bank access latency per request
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system.physmem.avgBusLat 4997.20 # Average bus latency per request
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system.physmem.avgMemAccLat 24651.34 # Average memory access latency
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system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 4538 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 15448751.59 # Average gap between requests
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system.cpu.branchPred.lookups 19976706 # Number of BP lookups
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system.cpu.branchPred.condPredicted 19976706 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 2014402 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 13812152 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 13105283 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 94.882267 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.workload.num_syscalls 400 # Number of system calls
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system.cpu.numCycles 165672471 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 25870668 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 219126869 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 19976706 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 13105283 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 57628355 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 17696017 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 66630701 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 278 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 2007 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 24475842 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 426793 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 165546176 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.187647 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.326502 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 109520431 66.16% 66.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 3059143 1.85% 68.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 2383042 1.44% 69.44% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2888379 1.74% 71.19% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 3450462 2.08% 73.27% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 3573116 2.16% 75.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 4323051 2.61% 78.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 2727876 1.65% 79.69% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 33620676 20.31% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 165546176 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.120580 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.322651 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 38775408 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 56644846 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 44737695 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9974174 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 15414053 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 354047911 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 15414053 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 46255302 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 14979465 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 23344 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 46561207 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 42312805 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 345686471 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 102 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 18031828 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 22149425 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 50 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 399403706 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 962076305 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 952204922 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 9871383 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 259428604 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 139975102 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 1676 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 1665 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 90583210 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 86793756 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 31811808 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 57862174 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 18818230 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 334054188 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 3459 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 267584091 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 253989 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 112238541 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 231222254 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 2214 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 165546176 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.616371 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.504250 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 45159771 27.28% 27.28% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 46666031 28.19% 55.47% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 32872103 19.86% 75.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 19858979 12.00% 87.32% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 13194353 7.97% 95.29% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 4779249 2.89% 98.18% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 2330620 1.41% 99.59% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 541020 0.33% 99.91% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 144050 0.09% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 165546176 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 132244 4.97% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 2258982 84.96% 89.93% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 267651 10.07% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 1212144 0.45% 0.45% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 174232004 65.11% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.57% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 1599138 0.60% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.16% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 67256463 25.13% 91.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 23284342 8.70% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 267584091 # Type of FU issued
|
|
system.cpu.iq.rate 1.615139 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2658877 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.009937 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 698266747 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 441935949 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 260335869 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 5360477 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 4651988 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2579879 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 266334819 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2696005 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 19019917 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 30144170 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 29191 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 297029 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 11296091 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 49411 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 15414053 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 584332 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 268197 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 334057647 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 187603 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 86793756 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 31811808 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1663 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 154006 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 31822 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 297029 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 1177472 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 918811 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 2096283 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 264704604 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 66268952 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 2879487 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 89158933 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 14605846 # Number of branches executed
|
|
system.cpu.iew.exec_stores 22889981 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.597759 # Inst execution rate
|
|
system.cpu.iew.wb_sent 263752937 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 262915748 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 212158955 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 375269860 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.586961 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.565350 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 112734910 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 2014608 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 150132123 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.474454 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.942401 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 50871002 33.88% 33.88% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 57276171 38.15% 72.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13824598 9.21% 81.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 12056402 8.03% 89.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4136994 2.76% 92.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 2958422 1.97% 94.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1072501 0.71% 94.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 994968 0.66% 95.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 6941065 4.62% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 150132123 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
|
|
system.cpu.commit.committedOps 221362961 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 77165303 # Number of memory references committed
|
|
system.cpu.commit.loads 56649586 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 12326938 # Number of branches committed
|
|
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 220339551 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 0 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 6941065 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 477288929 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 683644230 # The number of ROB writes
|
|
system.cpu.timesIdled 2956 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 126295 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
|
|
system.cpu.committedOps 221362961 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
|
|
system.cpu.cpi 1.254418 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.254418 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.797182 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.797182 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 562757952 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 298813122 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 3531630 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2237821 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 137110805 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
|
|
system.cpu.icache.replacements 4901 # number of replacements
|
|
system.cpu.icache.tagsinuse 1627.835837 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 24466683 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 6871 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 3560.862029 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1627.835837 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.794842 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.794842 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 24466683 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 24466683 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 24466683 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 24466683 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 24466683 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 24466683 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 9159 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 9159 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 9159 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 9159 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 9159 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 9159 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 269675497 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 269675497 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 269675497 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 269675497 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 269675497 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 269675497 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 24475842 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 24475842 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 24475842 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 24475842 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 24475842 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 24475842 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000374 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000374 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000374 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000374 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000374 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000374 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29443.770827 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 29443.770827 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 29443.770827 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 29443.770827 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 29443.770827 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 33.230769 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2133 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2133 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2133 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2133 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2133 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2133 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7026 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 7026 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 7026 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 7026 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 7026 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 7026 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 205371497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 205371497 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 205371497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 205371497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 205371497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 205371497 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000287 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000287 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000287 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29230.215912 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29230.215912 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 29230.215912 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29230.215912 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 29230.215912 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 2531.748288 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3493 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 3808 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.917279 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 1.438884 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2246.558475 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 283.750928 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.000044 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.068560 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.008659 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.077263 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3460 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3490 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 13 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 13 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3460 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 37 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3497 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3460 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 37 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3497 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3413 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 394 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 3807 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 153 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 153 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1555 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1555 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3413 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1949 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 5362 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3413 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1949 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 5362 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 163591500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 23492500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 187084000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68820500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 68820500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 163591500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 92313000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 255904500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 163591500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 92313000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 255904500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6873 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 424 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7297 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 153 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 153 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1562 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1562 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 6873 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1986 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8859 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 6873 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1986 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8859 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.496581 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.929245 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.521721 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995519 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.995519 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.496581 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.981370 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.605260 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.496581 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.981370 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.605260 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47931.878113 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59625.634518 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 49142.106646 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44257.556270 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44257.556270 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47931.878113 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47364.289379 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 47725.568818 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47931.878113 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47364.289379 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 47725.568818 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3413 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 394 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 3807 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 153 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 153 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3413 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1949 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 5362 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3413 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1949 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5362 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 121265541 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18645311 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 139910852 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1530153 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1530153 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49241002 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49241002 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 121265541 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67886313 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 189151854 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 121265541 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67886313 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 189151854 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.929245 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.521721 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995519 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995519 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.605260 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496581 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981370 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.605260 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35530.483739 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47323.124365 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36750.946152 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31666.239228 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31666.239228 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35530.483739 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34831.356080 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35276.362178 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 56 # number of replacements
|
|
system.cpu.dcache.tagsinuse 1416.460930 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 67604390 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1983 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 34091.976803 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 1416.460930 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.345816 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.345816 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 47090189 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 47090189 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 20514015 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 20514015 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 67604204 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 67604204 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 67604204 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 67604204 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1716 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1716 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2507 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2507 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2507 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2507 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 39751500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 39751500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 77402500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 77402500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 117154000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 117154000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 117154000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 117154000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 47090980 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 47090980 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 67606711 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 67606711 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 67606711 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 67606711 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50254.740834 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 50254.740834 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45106.351981 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 45106.351981 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 46730.753889 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 46730.753889 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 46730.753889 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.500000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 13 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 424 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1715 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1715 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2139 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2139 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2139 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2139 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24221500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73937000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 73937000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 98158500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 98158500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 98158500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 98158500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57126.179245 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57126.179245 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43111.953353 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43111.953353 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45889.901823 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45889.901823 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|