cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
872 lines
99 KiB
Text
872 lines
99 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.025578 # Number of seconds simulated
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sim_ticks 25577832000 # Number of ticks simulated
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final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 133487 # Simulator instruction rate (inst/s)
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host_op_rate 189436 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 48151664 # Simulator tick rate (ticks/s)
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host_mem_usage 268312 # Number of bytes of host memory used
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host_seconds 531.19 # Real time elapsed on the host
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sim_insts 70907629 # Number of instructions simulated
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sim_ops 100626876 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory
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system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128779 # Total number of read requests seen
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system.physmem.writeReqs 83944 # Total number of write requests seen
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system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 8241856 # Total number of bytes read from memory
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system.physmem.bytesWritten 5372416 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 25577735000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 128779 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 83944 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests
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system.physmem.totBusLat 643885000 # Total cycles spent in databus access
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system.physmem.totBankLat 1400217500 # Total cycles spent in bank access
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system.physmem.avgQLat 24884.85 # Average queueing delay per request
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system.physmem.avgBankLat 10873.20 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 40758.05 # Average memory access latency
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system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 4.16 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.21 # Average read queue length over time
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system.physmem.avgWrQLen 9.73 # Average write queue length over time
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system.physmem.readRowHits 116758 # Number of row buffer hits during reads
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system.physmem.writeRowHits 52879 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes
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system.physmem.avgGap 120239.63 # Average gap between requests
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system.cpu.branchPred.lookups 16629564 # Number of BP lookups
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system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1946 # Number of system calls
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system.cpu.numCycles 51155665 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers
|
|
system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued
|
|
system.cpu.iq.rate 2.096836 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9761 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 14602542 # Number of branches executed
|
|
system.cpu.iew.exec_stores 21344564 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.076700 # Inst execution rate
|
|
system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 53282087 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
|
|
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 47862846 # Number of memory references committed
|
|
system.cpu.commit.loads 27307108 # Number of loads committed
|
|
system.cpu.commit.membars 15920 # Number of memory barriers committed
|
|
system.cpu.commit.branches 13741505 # Number of branches committed
|
|
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 149959530 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 224865260 # The number of ROB writes
|
|
system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
|
|
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 511661173 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 103341311 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 804 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 688 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
|
|
system.cpu.icache.replacements 28586 # number of replacements
|
|
system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 11645446 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 34686 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 30.440000 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3741 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 3741 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 3741 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 3741 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 3741 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 3741 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30945 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 30945 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 30945 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 95649 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.918275 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 25825 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 33460 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 59285 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 129109 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 129109 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4785 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 25825 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 38245 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 64070 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 25825 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 38245 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 64070 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 4676 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 21922 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 26598 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 312 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 102257 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 102257 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 4676 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 124179 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 128855 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 128855 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 129109 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 129109 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 332 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 332 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107042 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 107042 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 30501 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 162424 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 192925 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 30501 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 162424 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 192925 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153306 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395833 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.309700 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.939759 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.939759 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955298 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955298 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153306 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.764536 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.667902 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 83944 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 83944 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21861 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 26522 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102257 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 102257 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 124118 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 128779 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.939759 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.939759 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955298 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955298 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 158328 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 44337915 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1707154 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 129109 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|