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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson cb9e208a4c stats: Update stats to reflect SimpleDRAM changes 
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
2013-03-01 13:20:30 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.517371 # Number of seconds simulated
sim_ticks 517371024000 # Number of ticks simulated
final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 170437 # Simulator instruction rate (inst/s)
host_op_rate 190135 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 57090080 # Simulator tick rate (ticks/s)
host_mem_usage 485276 # Number of bytes of host memory used
host_seconds 9062.36 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 143734144 # Number of bytes read from this memory
system.physmem.bytes_read::total 143782208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48064 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 70446784 # Number of bytes written to this memory
system.physmem.bytes_written::total 70446784 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 751 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2245846 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2246597 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1100731 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1100731 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 92900 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 277816378 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 277909279 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 92900 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 92900 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 136162987 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 136162987 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 136162987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 92900 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 277816378 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 414072265 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 2246597 # Total number of read requests seen
system.physmem.writeReqs 1100731 # Total number of write requests seen
system.physmem.cpureqs 3350452 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 143782208 # Total number of bytes read from memory
system.physmem.bytesWritten 70446784 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 143782208 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 70446784 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 642 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 141495 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 139690 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 141603 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 141749 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 142295 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 140068 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 141091 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 140693 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 138519 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 136203 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 140642 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 140693 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 141066 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 139208 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 139271 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 141669 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 69094 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 68448 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 69171 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 69468 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 69338 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 68952 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 69046 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 68406 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 67828 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 66957 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 69534 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 69263 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 69109 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 68653 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 68505 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 68959 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 3124 # Number of times wr buffer was full causing retry
system.physmem.totGap 517370944500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 2246597 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1100731 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1563680 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 451075 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 162592 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 68583 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 44125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 47135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 47739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 47809 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 47829 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 47835 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 47837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 47838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 47840 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 47858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 47857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 47857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 47857 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 3733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 29 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
system.physmem.totQLat 51812524750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 131293078500 # Sum of mem lat for all requests
system.physmem.totBusLat 11229775000 # Total cycles spent in databus access
system.physmem.totBankLat 68250778750 # Total cycles spent in bank access
system.physmem.avgQLat 23069.26 # Average queueing delay per request
system.physmem.avgBankLat 30388.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 58457.57 # Average memory access latency
system.physmem.avgRdBW 277.91 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 136.16 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 277.91 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 136.16 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.25 # Average read queue length over time
system.physmem.avgWrQLen 10.92 # Average write queue length over time
system.physmem.readRowHits 827855 # Number of row buffer hits during reads
system.physmem.writeRowHits 271156 # Number of row buffer hits during writes
system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes
system.physmem.avgGap 154562.37 # Average gap between requests
system.cpu.branchPred.lookups 303290886 # Number of BP lookups
system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups
system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1034742049 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed
system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 155399906 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 380 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 288562414 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5732154 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 958634216 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.523474 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.213325 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 523513675 54.61% 54.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25518990 2.66% 57.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 39095186 4.08% 61.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 48349741 5.04% 66.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 43010158 4.49% 70.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 46440341 4.84% 75.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 38425121 4.01% 79.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18710957 1.95% 81.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 175570047 18.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 958634216 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.293108 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.112936 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 329763250 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 133666994 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 405221512 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 20079412 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 69903048 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46058380 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 679 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2367190993 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2433 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 69903048 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 353304996 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 63447183 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 15614 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 400231748 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 71731627 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2304653779 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 133097 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5040028 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 58589233 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 7 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2280042978 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10643127773 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10643124880 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2893 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 573723048 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 497 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 494 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 158827938 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 624515157 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 220983969 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 86332349 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 71315853 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2201513470 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 522 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2018112827 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4002858 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 473886256 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1126241029 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 958634216 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.105196 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.906381 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 277594004 28.96% 28.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 151404549 15.79% 44.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 161201477 16.82% 61.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 119812250 12.50% 74.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 123999377 12.94% 87.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 73820536 7.70% 94.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 38419650 4.01% 98.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 9808498 1.02% 99.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2573875 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 958634216 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 872312 3.66% 3.66% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 5645 0.02% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 18268766 76.62% 80.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 4697940 19.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1236677496 61.28% 61.28% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 926030 0.05% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 33 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 587482532 29.11% 90.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193026708 9.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2018112827 # Type of FU issued
system.cpu.iq.rate 1.950354 # Inst issue rate
system.cpu.iq.fu_busy_cnt 23844663 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.011815 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5022707128 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2675590256 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1957438118 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 556 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2041957357 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 64629974 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 138588388 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 271831 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 192988 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 46136924 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 4659196 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 69903048 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 28888784 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1501235 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2201514122 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 6139547 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 624515157 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 220983969 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 460 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 475783 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 89669 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 192988 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8156378 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 9617829 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 17774207 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1988116656 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 573901246 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29996171 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 130 # number of nop insts executed
system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed
system.cpu.iew.exec_branches 238330381 # Number of branches executed
system.cpu.iew.exec_stores 190143920 # Number of stores executed
system.cpu.iew.exec_rate 1.921365 # Inst execution rate
system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1957438221 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1296419261 # num instructions producing a value
system.cpu.iew.wb_consumers 2061223018 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.891716 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.628956 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 478537797 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 15221576 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 888731168 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.938802 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.727796 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 401249220 45.15% 45.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 192209497 21.63% 66.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 72554391 8.16% 74.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35214687 3.96% 78.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19001350 2.14% 81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30768614 3.46% 84.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 20079948 2.26% 86.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11444333 1.29% 88.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106209128 11.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 888731168 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773814 # Number of memory references committed
system.cpu.commit.loads 485926769 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462426 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106209128 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2984133091 # The number of ROB reads
system.cpu.rob.rob_writes 4473274350 # The number of ROB writes
system.cpu.timesIdled 1017651 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 76107833 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
system.cpu.cpi 0.669925 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.669925 # CPI: Total CPI of All Threads
system.cpu.ipc 1.492703 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.492703 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9956233395 # number of integer regfile reads
system.cpu.int_regfile_writes 1937436072 # number of integer regfile writes
system.cpu.fp_regfile_reads 98 # number of floating regfile reads
system.cpu.fp_regfile_writes 104 # number of floating regfile writes
system.cpu.misc_regfile_reads 737527238 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
system.cpu.icache.replacements 22 # number of replacements
system.cpu.icache.tagsinuse 625.709575 # Cycle average of tags in use
system.cpu.icache.total_refs 288561231 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 779 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 370425.200257 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 625.709575 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.305522 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.305522 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 288561231 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 288561231 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 288561231 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 288561231 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 288561231 # number of overall hits
system.cpu.icache.overall_hits::total 288561231 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1183 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1183 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1183 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1183 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1183 # number of overall misses
system.cpu.icache.overall_misses::total 1183 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 68862000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 68862000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 68862000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 68862000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 68862000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 68862000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 288562414 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 288562414 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 288562414 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 288562414 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 288562414 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 288562414 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58209.636517 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 58209.636517 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 58209.636517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58209.636517 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 58209.636517 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 404 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 404 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 404 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 404 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 404 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 404 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 779 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 779 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 779 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 779 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 779 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 779 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46813500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 46813500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46813500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 46813500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46813500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 46813500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60094.351733 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60094.351733 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60094.351733 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60094.351733 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2213910 # number of replacements
system.cpu.l2cache.tagsinuse 31531.957469 # Cycle average of tags in use
system.cpu.l2cache.total_refs 9247495 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2243685 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.121566 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14435.927117 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 20.343245 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 17075.687107 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.440550 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000621 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.521109 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.962279 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6290241 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6290268 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3781695 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3781695 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1066899 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1066899 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7357140 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7357167 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7357140 # number of overall hits
system.cpu.l2cache.overall_hits::total 7357167 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 752 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1419201 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1419953 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 826653 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 826653 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 752 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2245854 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2246606 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 752 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2245854 # number of overall misses
system.cpu.l2cache.overall_misses::total 2246606 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45758500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 113786309000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 113832067500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70488863500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70488863500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 45758500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 184275172500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 184320931000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 45758500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 184275172500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 184320931000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 779 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7709442 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7710221 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3781695 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3781695 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893552 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893552 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 779 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.data 9602994 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9603773 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965340 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184086 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.184165 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965340 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.233870 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.233930 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965340 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.233870 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.233930 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60849.069149 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80176.316815 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80166.081201 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85270.196201 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85270.196201 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 82044.172855 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60849.069149 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82051.269806 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 82044.172855 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1100731 # number of writebacks
system.cpu.l2cache.writebacks::total 1100731 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 751 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419193 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1419944 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826653 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 826653 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 751 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2245846 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2246597 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2245846 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2246597 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36118599 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 96162576934 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 96198695533 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60228963949 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60228963949 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36118599 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156391540883 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 156427659482 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36118599 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156391540883 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 156427659482 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184085 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184164 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.233929 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964056 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233869 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.233929 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48094.006658 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67758.632500 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67748.231996 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72858.822201 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72858.822201 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48094.006658 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.914877 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69628.713776 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9598898 # number of replacements
system.cpu.dcache.tagsinuse 4088.019682 # Cycle average of tags in use
system.cpu.dcache.total_refs 656099070 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9602994 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.322345 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3440663000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4088.019682 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998052 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 489051603 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 489051603 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167047341 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167047341 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 65 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 65 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 656098944 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 656098944 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 656098944 # number of overall hits
system.cpu.dcache.overall_hits::total 656098944 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 11478513 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 11478513 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5538706 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5538706 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 17017219 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 17017219 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 17017219 # number of overall misses
system.cpu.dcache.overall_misses::total 17017219 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 323000428500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 323000428500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 229631369718 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 229631369718 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 423500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 423500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 552631798218 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 552631798218 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 552631798218 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 552631798218 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 500530116 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 500530116 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 673116163 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 673116163 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 673116163 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 673116163 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022933 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.022933 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.025281 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.025281 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.025281 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.025281 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28139.570735 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28139.570735 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389561 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389561 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 141166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 141166.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 32474.859624 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32474.859624 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32474.859624 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 26343962 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1054966 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1182360 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 64552 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.280830 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16.342886 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3781695 # number of writebacks
system.cpu.dcache.writebacks::total 3781695 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3769070 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3769070 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645155 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3645155 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 7414225 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 7414225 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 7414225 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 7414225 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7709443 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7709443 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893551 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893551 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9602994 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9602994 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9602994 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9602994 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186232562000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 186232562000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83589909224 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83589909224 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269822471224 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 269822471224 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269822471224 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 269822471224 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014266 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014266 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014266 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24156.422455 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24156.422455 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44144.524876 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44144.524876 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28097.744435 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28097.744435 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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