cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
764 lines
89 KiB
Plaintext
764 lines
89 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.603674 # Number of seconds simulated
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sim_ticks 2603674284000 # Number of ticks simulated
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final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 271279 # Simulator instruction rate (inst/s)
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host_op_rate 345198 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 11733407598 # Simulator tick rate (ticks/s)
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host_mem_usage 403640 # Number of bytes of host memory used
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host_seconds 221.90 # Real time elapsed on the host
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sim_insts 60197457 # Number of instructions simulated
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sim_ops 76600355 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
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system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 15494095 # Total number of read requests seen
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system.physmem.writeReqs 811481 # Total number of write requests seen
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system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 991622080 # Total number of bytes read from memory
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system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 2603669924000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 6652 # Categorize read packet sizes
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system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 152019 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 754018 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 57463 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests
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system.physmem.totBusLat 77468795000 # Total cycles spent in databus access
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system.physmem.totBankLat 17451610000 # Total cycles spent in bank access
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system.physmem.avgQLat 22040.37 # Average queueing delay per request
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system.physmem.avgBankLat 1126.36 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 28166.74 # Average memory access latency
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system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.13 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.17 # Average read queue length over time
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system.physmem.avgWrQLen 12.40 # Average write queue length over time
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system.physmem.readRowHits 15418728 # Number of row buffer hits during reads
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system.physmem.writeRowHits 794030 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
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system.physmem.avgGap 159679.73 # Average gap between requests
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system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
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system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_txs 0 # Number of DMA write transactions.
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 14995645 # DTB read hits
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system.cpu.dtb.read_misses 7332 # DTB read misses
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system.cpu.dtb.write_hits 11230857 # DTB write hits
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system.cpu.dtb.write_misses 2203 # DTB write misses
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 15002977 # DTB read accesses
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system.cpu.dtb.write_accesses 11233060 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 26226502 # DTB hits
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system.cpu.dtb.misses 9535 # DTB misses
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system.cpu.dtb.accesses 26236037 # DTB accesses
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system.cpu.itb.inst_hits 61491397 # ITB inst hits
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system.cpu.itb.inst_misses 4471 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 61495868 # ITB inst accesses
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system.cpu.itb.hits 61491397 # DTB hits
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system.cpu.itb.misses 4471 # DTB misses
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system.cpu.itb.accesses 61495868 # DTB accesses
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system.cpu.numCycles 5207348568 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 60197457 # Number of instructions committed
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system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
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system.cpu.num_func_calls 2139722 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls
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system.cpu.num_int_insts 68868122 # number of integer instructions
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system.cpu.num_fp_insts 10269 # number of float instructions
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system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read
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system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
|
system.cpu.num_mem_refs 27393871 # number of memory refs
|
|
system.cpu.num_load_insts 15659652 # Number of load instructions
|
|
system.cpu.num_store_insts 11734219 # Number of store instructions
|
|
system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.879352 # Percentage of idle cycles
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed
|
|
system.cpu.icache.replacements 855484 # number of replacements
|
|
system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 60635401 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 855996 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9856784000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9856784000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11514.988388 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11514.988388 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 61912 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 50892.966587 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1682705 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 13.219148 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 2553153097000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 37868.000507 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 6995.362387 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 6025.716777 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.577820 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.106741 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.776565 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 843754 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 370328 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1226331 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 596040 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 596040 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 114438 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 114438 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 843754 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 484766 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1340769 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 843754 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 484766 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1340769 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 153654 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 561610000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 535948000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1098024500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 462000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 462000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6083213000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6083213000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 561610000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6619161000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 7181237500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 561610000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6619161000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 7181237500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 854358 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 380187 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1246802 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 596040 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 596040 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247621 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 247621 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 854358 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 627808 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1494423 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 854358 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 627808 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1494423 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537850 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.537850 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.102818 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.102818 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52962.089777 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54361.294249 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 53638.048947 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.695652 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.695652 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45675.596735 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45675.596735 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 46736.417536 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 46736.417536 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 57463 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253755 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113753 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430132104 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413197859 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 843697471 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28847322 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28847322 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4445123890 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4445123890 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253755 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113753 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430132104 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4858321749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 5288821361 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253755 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113753 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430132104 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4858321749 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 5288821361 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209116116 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166689052786 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166898168902 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175171345 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175171345 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209116116 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175864224131 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176073340247 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537850 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537850 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.102818 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.102818 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 627296 # number of replacements
|
|
system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 23168154 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 619307 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 596040 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|