cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
613 lines
70 KiB
Text
613 lines
70 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.042726 # Number of seconds simulated
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sim_ticks 42726055500 # Number of ticks simulated
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final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 89848 # Simulator instruction rate (inst/s)
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host_op_rate 89848 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 43455006 # Simulator tick rate (ticks/s)
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host_mem_usage 257260 # Number of bytes of host memory used
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host_seconds 983.23 # Real time elapsed on the host
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sim_insts 88340673 # Number of instructions simulated
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sim_ops 88340673 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 165519 # Total number of read requests seen
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system.physmem.writeReqs 113997 # Total number of write requests seen
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system.physmem.cpureqs 279530 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 10593216 # Total number of bytes read from memory
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system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
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system.physmem.totGap 42726035000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 165519 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 113997 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
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system.physmem.totQLat 7053839750 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 9647402250 # Sum of mem lat for all requests
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system.physmem.totBusLat 827595000 # Total cycles spent in databus access
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system.physmem.totBankLat 1765967500 # Total cycles spent in bank access
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system.physmem.avgQLat 42616.50 # Average queueing delay per request
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system.physmem.avgBankLat 10669.27 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 58285.77 # Average memory access latency
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system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.27 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.23 # Average read queue length over time
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system.physmem.avgWrQLen 10.42 # Average write queue length over time
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system.physmem.readRowHits 148856 # Number of row buffer hits during reads
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system.physmem.writeRowHits 71619 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes
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system.physmem.avgGap 152857.21 # Average gap between requests
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system.cpu.branchPred.lookups 18742591 # Number of BP lookups
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system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 20277550 # DTB read hits
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system.cpu.dtb.read_misses 90148 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 20367698 # DTB read accesses
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system.cpu.dtb.write_hits 14728779 # DTB write hits
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system.cpu.dtb.write_misses 7252 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 14736031 # DTB write accesses
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system.cpu.dtb.data_hits 35006329 # DTB hits
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system.cpu.dtb.data_misses 97400 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 35103729 # DTB accesses
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system.cpu.itb.fetch_hits 12368275 # ITB hits
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system.cpu.itb.fetch_misses 11063 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 12379338 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4583 # Number of system calls
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system.cpu.numCycles 85452112 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 35060657 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed.
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system.cpu.activity 81.422683 # Percentage of cycles cpu is active
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system.cpu.comLoads 20276638 # Number of Load instructions committed
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system.cpu.comStores 14613377 # Number of Store instructions committed
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system.cpu.comBranches 13754477 # Number of Branches instructions committed
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system.cpu.comNops 8748916 # Number of Nop instructions committed
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system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
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system.cpu.comInts 30791227 # Number of Integer instructions committed
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system.cpu.comFloats 151453 # Number of Floating Point instructions committed
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system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
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system.cpu.cpi 0.967302 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 0.967302 # CPI: Total CPI of All Threads
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system.cpu.ipc 1.033803 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 1.033803 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 32797293 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 52654819 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 61.619096 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 42999337 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 42452775 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 49.680194 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 42422406 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 43029706 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 50.355345 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 63339640 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 22112472 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 25.877034 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 39402909 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 46049203 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 53.888900 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 84308 # number of replacements
|
|
system.cpu.icache.tagsinuse 1908.296945 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 12251160 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 86354 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 141.871367 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1908.296945 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.931786 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.931786 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 12251160 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 12251160 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 12251160 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 12251160 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 12251160 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 12251160 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 117106 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 117106 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 117106 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 117106 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 117106 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 117106 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1889037500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1889037500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1889037500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1889037500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1889037500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1889037500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 12368266 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 12368266 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 12368266 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 12368266 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 12368266 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 12368266 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 271 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30752 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 30752 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 30752 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 30752 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 30752 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 30752 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 86354 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 86354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 86354 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 86354 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 86354 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336921000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1336921000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336921000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1336921000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336921000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1336921000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006982 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006982 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006982 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006982 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15481.865345 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15481.865345 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15481.865345 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 15481.865345 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 131595 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 30966.013370 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 151363 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.924896 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 27281.106918 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2018.513701 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1666.392751 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.832553 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.061600 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.945008 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 79247 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 33054 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 112301 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 168350 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 168350 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 79247 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 45933 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 125180 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 79247 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 45933 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 125180 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 7107 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 27521 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 34628 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130891 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130891 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 7107 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 158412 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 165519 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 7107 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 165519 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 455300000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1513155000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1968455000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11996427000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11996427000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 455300000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 13509582000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 13964882000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 455300000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 13509582000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 13964882000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86354 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 60575 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 146929 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 168350 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 168350 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 86354 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 204345 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 290699 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 86354 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 204345 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 290699 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082301 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454329 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.235678 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91652.038719 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91652.038719 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84370.265649 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64063.599268 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85281.304447 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84370.265649 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130891 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130891 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7107 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 165519 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7107 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 165519 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 366897656 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1170781845 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1537679501 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10407190958 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10407190958 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 366897656 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11577972803 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11944870459 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 366897656 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11577972803 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11944870459 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454329 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235678 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569383 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082301 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775218 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569383 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51624.828479 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42541.399113 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44405.668852 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79510.363264 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79510.363264 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51624.828479 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73087.725696 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72166.158924 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 200249 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4078.188712 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 33754882 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 204345 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 165.185750 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4078.188712 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.995652 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.995652 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20180269 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20180269 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 13574613 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 13574613 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 33754882 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 33754882 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1135133 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 168350 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|