cb9e208a4c
This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
835 lines
95 KiB
Plaintext
835 lines
95 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.629620 # Number of seconds simulated
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sim_ticks 629619966000 # Number of ticks simulated
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final_tick 629619966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 178339 # Simulator instruction rate (inst/s)
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host_op_rate 178339 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 61592425 # Simulator tick rate (ticks/s)
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host_mem_usage 247872 # Number of bytes of host memory used
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host_seconds 10222.36 # Real time elapsed on the host
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sim_insts 1823043370 # Number of instructions simulated
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sim_ops 1823043370 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 176384 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30472320 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 176384 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 176384 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2756 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 476130 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 280144 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 48117813 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 48397957 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 280144 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 280144 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 6801106 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6801106 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 6801106 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 280144 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 48117813 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 55199063 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 476130 # Total number of read requests seen
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system.physmem.writeReqs 66908 # Total number of write requests seen
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system.physmem.cpureqs 543038 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30472320 # Total number of bytes read from memory
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system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 30472320 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 84 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 29664 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 29737 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 29644 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 29657 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 29716 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 29817 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 29817 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 29794 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 29703 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 29783 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 29754 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 29855 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 29819 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 629619903500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 476130 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 66908 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 406575 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 66997 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 2280 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 167 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2899 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 2394780250 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 20405886500 # Sum of mem lat for all requests
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system.physmem.totBusLat 2380230000 # Total cycles spent in databus access
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system.physmem.totBankLat 15630876250 # Total cycles spent in bank access
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system.physmem.avgQLat 5030.56 # Average queueing delay per request
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system.physmem.avgBankLat 32834.80 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 42865.37 # Average memory access latency
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system.physmem.avgRdBW 48.40 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 48.40 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 6.80 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.43 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.03 # Average read queue length over time
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system.physmem.avgWrQLen 11.00 # Average write queue length over time
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system.physmem.readRowHits 143857 # Number of row buffer hits during reads
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system.physmem.writeRowHits 46184 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 69.03 # Row buffer hit rate for writes
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system.physmem.avgGap 1159439.86 # Average gap between requests
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system.cpu.branchPred.lookups 389447649 # Number of BP lookups
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system.cpu.branchPred.condPredicted 255913711 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 25827412 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 318653162 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 258406685 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 81.093401 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 57304748 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 7060 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 523436365 # DTB read hits
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system.cpu.dtb.read_misses 589877 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 524026242 # DTB read accesses
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system.cpu.dtb.write_hits 283043527 # DTB write hits
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system.cpu.dtb.write_misses 50254 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 283093781 # DTB write accesses
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system.cpu.dtb.data_hits 806479892 # DTB hits
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system.cpu.dtb.data_misses 640131 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 807120023 # DTB accesses
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system.cpu.itb.fetch_hits 394546295 # ITB hits
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system.cpu.itb.fetch_misses 717 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 394547012 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 39 # Number of system calls
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system.cpu.numCycles 1259239933 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 410282333 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 3275811622 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 389447649 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 315711433 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 630410102 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 157985911 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 72865288 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 7390 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 394546295 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 10716533 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1245235231 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.630677 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.141977 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 614825129 49.37% 49.37% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 58056687 4.66% 54.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 43354375 3.48% 57.52% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 71856761 5.77% 63.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 128610709 10.33% 73.62% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 45745044 3.67% 77.29% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 41218746 3.31% 80.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 7546870 0.61% 81.21% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 234020910 18.79% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1245235231 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.309272 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.601420 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 438008414 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 59262942 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 607236165 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 9069872 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 131657838 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 32266957 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 12470 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3196223031 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 46480 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 131657838 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 467254081 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 24463646 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 27494 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 586711565 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 35120607 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3098173488 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 98 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 15446 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 28849573 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 2055567023 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3582389843 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3461627532 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 120762311 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 670597953 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 4242 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 109579430 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 745093938 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 351398329 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 68579657 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 8864385 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2626006003 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 100 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2162044617 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 17925122 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 802898808 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 727596475 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1245235231 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.736254 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.804060 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 447917303 35.97% 35.97% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 197535103 15.86% 51.83% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 251432136 20.19% 72.03% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 120080138 9.64% 81.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 104735346 8.41% 90.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 79904704 6.42% 96.50% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 24241740 1.95% 98.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 17620604 1.42% 99.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 1768157 0.14% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1245235231 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 1146296 3.12% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 25620524 69.67% 72.79% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 10007560 27.21% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1235570303 57.15% 57.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 17096 0.00% 57.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 27851417 1.29% 58.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 8254694 0.38% 58.82% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 590015596 27.29% 86.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 293128107 13.56% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2162044617 # Type of FU issued
|
|
system.cpu.iq.rate 1.716944 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36774380 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.017009 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5472922147 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 3340796044 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1991352678 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 151101820 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 88182161 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 73610057 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2121366202 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 77450043 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 63177927 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 234023912 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1058362 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 75850 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 140603433 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 2424 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 131657838 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 10420983 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 524239 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2989422700 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 731121 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 745093938 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 351398329 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 100 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 195339 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 1467 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 75850 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 25820235 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 27779 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 25848014 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2068492319 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 524026374 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 93552298 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 363416597 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 807120680 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 278196977 # Number of branches executed
|
|
system.cpu.iew.exec_stores 283094306 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.642651 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2067333908 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2064962735 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1181126750 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1753498514 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.639849 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.673583 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 963484022 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 25815357 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1113577393 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.804084 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.508160 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 494309525 44.39% 44.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 228815920 20.55% 64.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 119838693 10.76% 75.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 58859369 5.29% 80.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 50684004 4.55% 85.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24146580 2.17% 87.70% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19115188 1.72% 89.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 16708765 1.50% 90.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 101099349 9.08% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1113577393 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
|
|
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 721864922 # Number of memory references committed
|
|
system.cpu.commit.loads 511070026 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 266706457 # Number of branches committed
|
|
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 101099349 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3979313260 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6076602940 # The number of ROB writes
|
|
system.cpu.timesIdled 331541 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 14004702 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.690735 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.690735 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.447733 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.447733 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2629807592 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1497388428 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 78811502 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 52661191 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 8338 # number of replacements
|
|
system.cpu.icache.tagsinuse 1655.801182 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 394533427 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 10050 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 39257.057413 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1655.801182 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.808497 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.808497 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 394533427 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 394533427 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 394533427 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 394533427 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 394533427 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 394533427 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12868 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12868 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12868 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12868 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12868 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12868 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 310260499 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 310260499 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 310260499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 310260499 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 310260499 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 310260499 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 394546295 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 394546295 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 394546295 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 394546295 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 394546295 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 394546295 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24111.011735 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 24111.011735 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 24111.011735 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24111.011735 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 24111.011735 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1217 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 71.588235 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2817 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2817 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2817 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2817 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2817 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2817 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10051 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 10051 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 10051 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 10051 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 10051 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 10051 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233282499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 233282499 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233282499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 233282499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233282499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 233282499 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23209.879514 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23209.879514 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23209.879514 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 23209.879514 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 443352 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 32702.161581 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1090053 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 476088 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.289604 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 1307.378151 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 33.870078 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31360.913353 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.039898 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001034 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.957059 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997991 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 7294 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1053720 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1061014 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 95989 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 95989 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4789 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4789 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 7294 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1058509 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1065803 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 7294 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1058509 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1065803 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2757 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 406520 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 409277 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66854 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66854 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2757 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 473374 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 476131 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2757 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 473374 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 476131 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 150279500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27491647500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 27641927000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3779391500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3779391500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 150279500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 31271039000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 31421318500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 150279500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 31271039000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 31421318500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 10051 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1460240 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1470291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 95989 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 95989 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 71643 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 71643 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 10051 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1531883 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1541934 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 10051 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1531883 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1541934 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.274301 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278393 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.278365 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933155 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.933155 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274301 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.309014 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.308788 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274301 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.309014 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.308788 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54508.342401 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67626.801879 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67538.432406 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56532.017531 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56532.017531 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 65993.011377 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54508.342401 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66059.899783 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 65993.011377 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66908 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2757 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406520 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 409277 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2757 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 473374 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 476131 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2757 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 473374 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 476131 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116032718 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22416103108 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22532135826 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2973259427 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2973259427 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116032718 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25389362535 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 25505395253 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116032718 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25389362535 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 25505395253 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278393 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278365 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933155 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933155 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.308788 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274301 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309014 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.308788 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42086.586144 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55141.452101 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55053.511011 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44473.919691 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44473.919691 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42086.586144 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53634.890245 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53568.020677 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1527787 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.859370 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 668059061 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1531883 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 436.103189 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 314057000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.859370 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999722 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999722 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 458325911 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 458325911 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 209733124 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 209733124 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 26 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 26 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 668059035 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 668059035 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 668059035 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 668059035 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1925830 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1925830 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1061772 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1061772 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2987602 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2987602 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2987602 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2987602 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 64791591000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 64791591000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 35422596379 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 35422596379 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 44500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 44500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 100214187379 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 100214187379 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 100214187379 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 100214187379 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 460251741 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 460251741 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 27 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 27 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 671046637 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 671046637 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 671046637 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 671046637 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004184 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004184 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.037037 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.037037 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.004452 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.004452 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.004452 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.004452 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33643.463338 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 33643.463338 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33361.772941 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33361.772941 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 44500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 44500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 33543.352622 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33543.352622 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 33543.352622 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 14428 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 387 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.281654 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 95989 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465591 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 465591 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990129 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 990129 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1455720 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1455720 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1455720 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1455720 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460239 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1460239 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71643 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 71643 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1531882 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1531882 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1531882 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1531882 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39489667000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 39489667000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3899533000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3899533000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 42500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 42500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43389200000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 43389200000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43389200000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 43389200000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003173 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003173 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.037037 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.037037 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27043.290174 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27043.290174 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54430.062951 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54430.062951 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 42500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 42500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28324.113737 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28324.113737 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|