stats: Update stats to match cache changes
This commit is contained in:
Andreas Hansson
parent
337774e192
commit
324bc9771d
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu
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sim_ticks 51111152682000 # Number of ticks simulated
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final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 549288 # Simulator instruction rate (inst/s)
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host_op_rate 645503 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 28514691627 # Simulator tick rate (ticks/s)
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host_mem_usage 672288 # Number of bytes of host memory used
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host_seconds 1792.45 # Real time elapsed on the host
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host_inst_rate 1110267 # Simulator instruction rate (inst/s)
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host_op_rate 1304746 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 57636324297 # Simulator tick rate (ticks/s)
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host_mem_usage 725492 # Number of bytes of host memory used
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host_seconds 886.79 # Real time elapsed on the host
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sim_insts 984570519 # Number of instructions simulated
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sim_ops 1157031967 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory
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system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory
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system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory
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system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory
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system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
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@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks
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system.cpu.dcache.writebacks::total 8921279 # number of writebacks
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system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks
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system.cpu.dcache.writebacks::total 8921277 # number of writebacks
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.tags.replacements 14295641 # number of replacements
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system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
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@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks::writebacks 14295641 # number of writebacks
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system.cpu.icache.writebacks::total 14295641 # number of writebacks
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.replacements 1722572 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.replacements 1723188 # number of replacements
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system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use
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system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks.
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system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks.
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system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks.
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system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor
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system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
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system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id
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@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910
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system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id
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system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses
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system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses
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system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits
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system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits
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system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits
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system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits
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system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits
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system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits
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system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits
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system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits
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system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits
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system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits
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system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits
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system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits
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system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits
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system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits
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system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits
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system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits
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system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits
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||||
system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits
|
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system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits
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system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits
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||||
system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits
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||||
system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits
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||||
system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses
|
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system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses
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@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917
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system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
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system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
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system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
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||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses
|
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system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses
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||||
system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses
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||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses
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||||
system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses
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||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544
|
|||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1503689 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1503967 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
|
||||
|
|
@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1954373 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1954989 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||
|
|
@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks 106631 # nu
|
|||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525878 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525254 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1610320 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 225581 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 224691 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3921686 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3920464 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3921686 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3920464 # Request fanout histogram
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,53 +4,53 @@ sim_seconds 51.111153 # Nu
|
|||
sim_ticks 51111152682000 # Number of ticks simulated
|
||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 625482 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 735044 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32470102586 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 669952 # Number of bytes of host memory used
|
||||
host_seconds 1574.10 # Real time elapsed on the host
|
||||
host_inst_rate 1109940 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1304361 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57619334274 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 720500 # Number of bytes of host memory used
|
||||
host_seconds 887.05 # Real time elapsed on the host
|
||||
sim_insts 984570519 # Number of instructions simulated
|
||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5543028 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 110110088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 116884284 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5543028 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103060480 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103081060 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 127017 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1720483 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1866737 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1610320 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1612893 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 108450 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2154326 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2286865 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 108450 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2016399 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2016802 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2016399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 108450 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2154729 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4303666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||||
|
|
@ -360,8 +360,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 8921279 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8921279 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 8921277 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 14295641 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
|
|
@ -411,23 +411,25 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 14295641 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 14295641 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1722572 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65341.862554 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46966735 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1785868 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.299108 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 1723188 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37098.596964 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.195568 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.733962 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6290.976194 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21198.359866 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.566080 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095993 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.323461 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id
|
||||
|
|
@ -439,33 +441,35 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 426185247 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 426185247 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 8921279 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 8921279 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1692559 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1692559 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14212229 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7504111 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7504111 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694322 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694322 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14212229 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9196670 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24171131 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14212229 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9196670 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24171131 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses
|
||||
|
|
@ -473,29 +477,31 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917
|
|||
system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 826558 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 826558 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83929 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344087 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344087 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 551027 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 551027 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83929 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1170645 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1266903 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83929 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1170645 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1266903 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -525,24 +531,24 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544
|
|||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328114 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328114 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005871 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043843 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442468 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442468 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005871 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.112917 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049803 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005871 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112917 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049803 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,21 +557,22 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1503689 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1503689 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1503967 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution
|
||||
|
|
@ -580,23 +587,23 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2158994970 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1954373 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55082670 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1954989 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54487002 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 595668 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55082670 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
|
||||
|
|
@ -710,47 +717,47 @@ system.iocache.writebacks::writebacks 106631 # nu
|
|||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525878 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525254 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1610320 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 225581 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 224691 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377021 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377021 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 449199 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5529643 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5658835 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6003209 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212740640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212909690 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220300730 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3921686 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3920464 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3921686 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3921686 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3920464 # Request fanout histogram
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,71 +4,71 @@ sim_seconds 51.111153 # Nu
|
|||
sim_ticks 51111152682000 # Number of ticks simulated
|
||||
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 564761 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 663687 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 29317960092 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 669948 # Number of bytes of host memory used
|
||||
host_seconds 1743.34 # Real time elapsed on the host
|
||||
host_inst_rate 1108699 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1302904 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 57554949131 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 721016 # Number of bytes of host memory used
|
||||
host_seconds 888.04 # Real time elapsed on the host
|
||||
sim_insts 984570519 # Number of instructions simulated
|
||||
sim_ops 1157031967 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 3317876 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 64750152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 3272948 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 64755976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.itb.walker 188480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 2225152 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 45360128 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 2212992 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 45372224 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 116883644 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 3317876 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 2225152 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5543028 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103060608 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 116844476 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 3272948 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 2212992 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 103078400 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103081188 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 103098980 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 92249 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1011734 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.inst 91547 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1011825 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.itb.walker 2945 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 34768 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 708752 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 34578 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 708941 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1866727 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1610322 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 1866115 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1610600 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1612895 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1613173 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 64915 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 1266850 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.inst 64036 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 1266964 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.itb.walker 3688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 43536 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 887480 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 43298 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 887717 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2286852 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 64915 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 43536 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 108450 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2016402 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2286086 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 64036 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 43298 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2016750 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2016804 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2016402 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2017152 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2016750 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 64915 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 1267252 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 64036 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 1267366 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.itb.walker 3688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 43536 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 887480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 43298 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 887717 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4303656 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4303238 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
||||
|
|
@ -410,8 +410,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 8921279 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 8921279 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 8921277 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 8921277 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 14295641 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use
|
||||
|
|
@ -475,6 +475,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 14295641 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 14295641 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -786,30 +788,30 @@ system.iocache.cache_copies 0 # nu
|
|||
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
||||
system.iocache.writebacks::total 106631 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 1722562 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65341.862549 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 47048799 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1785858 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 26.345207 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 1723178 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65341.862566 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 47049406 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1786474 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 26.336463 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 37097.979539 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460552 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 243.494258 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 3630.477879 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 9618.607320 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652985 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 37238.861730 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.459058 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.itb.walker 243.477138 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 3478.418369 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 9618.970377 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652979 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240388 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2660.497968 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 11581.451661 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.566070 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 2640.978192 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 11611.804335 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.568220 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.055397 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.146768 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.053076 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.146774 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.040596 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.176719 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.040298 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.177182 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_blocks::1024 63020 # Occupied blocks per task id
|
||||
|
|
@ -821,48 +823,50 @@ system.l2c.tags.age_task_id_blocks_1024::3 4910 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 426841717 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 426841717 # Number of data accesses
|
||||
system.l2c.tags.tag_accesses 426842331 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 426842331 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 142757 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 844303 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 8921279 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 8921279 # number of Writeback hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 14294063 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 864866 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 827692 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 1692558 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 7107362 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 7104867 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 14212229 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 3754928 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 3749182 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 7504110 # number of ReadSharedReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu0.data 345122 # number of InvalidateReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 864865 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 827683 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 1692548 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 7108064 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 7105057 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 3754840 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 3749002 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 7503842 # number of ReadSharedReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu0.data 345118 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::cpu1.data 349199 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::total 694321 # number of InvalidateReq hits
|
||||
system.l2c.InvalidateReq_hits::total 694317 # number of InvalidateReq hits
|
||||
system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 7107362 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 4619794 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.inst 7108064 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 4619705 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.itb.walker 142757 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 7104867 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 4576874 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 24253200 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 7105057 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 4576685 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 24253814 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 7107362 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 4619794 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.inst 7108064 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 4619705 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.itb.walker 142757 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 7104867 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 4576874 # number of overall hits
|
||||
system.l2c.overall_hits::total 24253200 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 7105057 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 4576685 # number of overall hits
|
||||
system.l2c.overall_hits::total 24253814 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses
|
||||
|
|
@ -873,43 +877,45 @@ system.l2c.UpgradeReq_misses::cpu1.data 19925 # nu
|
|||
system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 415071 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 411488 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 826559 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 49148 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 34781 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 83929 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 177103 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 166985 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 344088 # number of ReadSharedReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu0.data 420021 # number of InvalidateReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 415072 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 411497 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 826569 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 48446 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 34591 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 177191 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 167165 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 344356 # number of ReadSharedReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu0.data 420025 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::cpu1.data 131007 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::total 551028 # number of InvalidateReq misses
|
||||
system.l2c.InvalidateReq_misses::total 551032 # number of InvalidateReq misses
|
||||
system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 49148 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 592174 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 48446 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 592263 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.itb.walker 2945 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 34781 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 578473 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1266892 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 34591 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 578662 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1266278 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 49148 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 592174 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.inst 48446 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 592263 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.itb.walker 2945 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 34781 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 578473 # number of overall misses
|
||||
system.l2c.overall_misses::total 1266892 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 34591 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 578662 # number of overall misses
|
||||
system.l2c.overall_misses::total 1266278 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 856619 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 8921279 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -955,36 +961,36 @@ system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 #
|
|||
system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.324290 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.332065 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.328115 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006868 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004872 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.005871 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045041 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042640 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.043843 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548944 # miss rate for InvalidateReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.324291 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.332072 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.328119 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006770 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004845 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045063 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042686 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548950 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.272814 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::total 0.442469 # miss rate for InvalidateReq accesses
|
||||
system.l2c.InvalidateReq_miss_rate::total 0.442472 # miss rate for InvalidateReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.006868 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.113618 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.006770 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.113635 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.itb.walker 0.020212 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004872 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.112208 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.049643 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004845 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.112245 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.049619 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.006868 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.113618 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.006770 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.113635 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.itb.walker 0.020212 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004872 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.112208 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.049643 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004845 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.112245 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.049619 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -993,51 +999,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 1503691 # number of writebacks
|
||||
system.l2c.writebacks::total 1503691 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 1503969 # number of writebacks
|
||||
system.l2c.writebacks::total 1503969 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 76679 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525866 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 525242 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1610322 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 225569 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1610600 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 224679 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 40488 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377023 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377023 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 449187 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 40489 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1377035 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 1377035 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 448563 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5529617 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5658809 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5527785 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 5656977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6003183 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 6001351 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212740128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 212909178 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212718752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 212887802 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220300218 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 220278842 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3921668 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3920446 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3921668 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 3920446 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3921668 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3920446 # Request fanout histogram
|
||||
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
||||
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
||||
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
||||
|
|
@ -1093,15 +1099,16 @@ system.realview.realview_io.osc_system_bus.clock 41667
|
|||
system.toL2Bus.snoop_filter.tot_requests 52477792 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 26568978 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 2719 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 2719 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 8921279 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 16984756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution
|
||||
|
|
@ -1116,22 +1123,22 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35
|
|||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 80533877 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 2159735666 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1954363 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 55175249 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size::total 3074555570 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1954979 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 55175865 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.011169 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.105093 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 54558983 98.88% 98.88% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 616266 1.12% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 54559594 98.88% 98.88% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 616271 1.12% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 55175249 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 55175865 # Request fanout histogram
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu
|
|||
sim_ticks 61241011500 # Number of ticks simulated
|
||||
final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 252391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 253648 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 170598134 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 450980 # Number of bytes of host memory used
|
||||
host_seconds 358.98 # Real time elapsed on the host
|
||||
host_inst_rate 266495 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 267822 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 180131185 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 451088 # Number of bytes of host memory used
|
||||
host_seconds 339.98 # Real time elapsed on the host
|
||||
sim_insts 90602850 # Number of instructions simulated
|
||||
sim_ops 91054081 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # By
|
|||
system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 73241750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 73240250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 365252750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 4702.73 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 23452.73 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -227,28 +227,28 @@ system.physmem_0.preEnergy 3440250 # En
|
|||
system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.511702 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 2491483680 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 34557957750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 41122783920 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 671.511714 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 57480384250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1713932750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.513254 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 2555148690 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 34502111250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 41122878405 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 671.513257 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 57387653250 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1806576750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 20752188 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted
|
||||
|
|
@ -386,8 +386,8 @@ system.cpu.discardedOps 2176623 # Nu
|
|||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.351856 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.739724 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 109255161 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 13226862 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 946097 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks.
|
||||
|
|
@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n
|
|||
system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 989221 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919046000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11919046000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542633500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2542633500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 14461679500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 14461679500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 14461679500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 14461679500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309
|
|||
system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 14619.319624 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 14619.260509 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190
|
|||
system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865349000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865349000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481625500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481625500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346974500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 12346974500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347131000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 12347131000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -516,16 +516,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 5 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use
|
||||
|
|
@ -587,6 +587,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 5 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 5 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -613,12 +615,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 10245.556296 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655409 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy
|
||||
|
|
@ -634,8 +636,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits
|
||||
|
|
@ -660,20 +664,22 @@ system.cpu.l2cache.demand_misses::total 15582 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15582 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067670500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1067670500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1089567500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1147164500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1089567500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1147164500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -698,18 +704,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -740,18 +746,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922230500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922230500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941176500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 990886500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941176500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 990886500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -764,18 +770,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -784,8 +790,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution
|
||||
|
|
@ -793,22 +800,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 950829 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 950995 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1891831500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -833,9 +840,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15574 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 21739000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 82131250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.361489 # Number of seconds simulated
|
||||
sim_ticks 361488536500 # Number of ticks simulated
|
||||
final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.361598 # Number of seconds simulated
|
||||
sim_ticks 361597758500 # Number of ticks simulated
|
||||
final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1117046 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1656101101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 428664 # Number of bytes of host memory used
|
||||
host_seconds 218.28 # Real time elapsed on the host
|
||||
host_inst_rate 1135132 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1683423955 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 429008 # Number of bytes of host memory used
|
||||
host_seconds 214.80 # Real time elapsed on the host
|
||||
sim_insts 243825150 # Number of instructions simulated
|
||||
sim_ops 243835265 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 56256 # Nu
|
|||
system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 443 # Number of system calls
|
||||
system.cpu.numCycles 722977073 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 723195517 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 243825150 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu
|
|||
system.cpu.num_load_insts 82803521 # Number of load instructions
|
||||
system.cpu.num_store_insts 22907920 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29302884 # Number of branches fetched
|
||||
|
|
@ -90,18 +90,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 244431613 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
|
||||
|
|
@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n
|
|||
system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 939567 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567
|
|||
system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -206,26 +206,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 25 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
|
||||
|
|
@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n
|
|||
system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 882 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses
|
||||
|
|
@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -278,44 +278,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 25 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 25 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
||||
|
|
@ -325,8 +327,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
||||
|
|
@ -351,20 +355,22 @@ system.cpu.l2cache.demand_misses::total 15603 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -389,18 +395,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -421,18 +427,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -445,18 +451,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -465,8 +471,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution
|
||||
|
|
@ -474,22 +481,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -514,9 +521,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 15603 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.365989 # Number of seconds simulated
|
||||
sim_ticks 365988859500 # Number of ticks simulated
|
||||
final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.366199 # Number of seconds simulated
|
||||
sim_ticks 366199170500 # Number of ticks simulated
|
||||
final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 563395 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 992048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1305133674 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 455224 # Number of bytes of host memory used
|
||||
host_seconds 280.42 # Real time elapsed on the host
|
||||
host_inst_rate 639917 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1126791 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1483253517 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 455604 # Number of bytes of host memory used
|
||||
host_seconds 246.89 # Real time elapsed on the host
|
||||
sim_insts 157988548 # Number of instructions simulated
|
||||
sim_ops 278192465 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,21 +25,21 @@ system.physmem.num_reads::cpu.data 29241 # Nu
|
|||
system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 102 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 444 # Number of system calls
|
||||
system.cpu.numCycles 731977719 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 732398341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 157988548 # Number of instructions committed
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu
|
|||
system.cpu.num_load_insts 90779385 # Number of load instructions
|
||||
system.cpu.num_store_insts 31439752 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 29309705 # Number of branches fetched
|
||||
|
|
@ -100,18 +100,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 278192465 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2062733 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses
|
||||
|
|
@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n
|
|||
system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829
|
|||
system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -198,24 +198,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 24 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n
|
|||
system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses
|
||||
|
|
@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004
|
|||
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -267,44 +267,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 24 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 24 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 313 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 20041.891909 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
|
||||
|
|
@ -314,8 +316,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2062482 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2062482 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits
|
||||
|
|
@ -340,20 +344,22 @@ system.cpu.l2cache.demand_misses::total 30044 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 30044 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42159500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 42159500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11392500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11392500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42159500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1535183500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1577343000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42159500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1535183500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1577343000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2062482 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2062482 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -378,18 +384,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014531 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,18 +418,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30044
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1233551000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1233551000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34129500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34129500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9222500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9222500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -436,18 +442,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 197 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution
|
||||
|
|
@ -465,29 +472,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 313 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1020 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 102 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 102 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 14 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
|
||||
|
|
@ -509,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 30160 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.707537 # Number of seconds simulated
|
||||
sim_ticks 707536959500 # Number of ticks simulated
|
||||
final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.708526 # Number of seconds simulated
|
||||
sim_ticks 708526400500 # Number of ticks simulated
|
||||
final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1064510 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1491485099 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319084 # Number of bytes of host memory used
|
||||
host_seconds 474.38 # Real time elapsed on the host
|
||||
host_inst_rate 974268 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1366955379 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319428 # Number of bytes of host memory used
|
||||
host_seconds 518.32 # Real time elapsed on the host
|
||||
sim_insts 504986854 # Number of instructions simulated
|
||||
sim_ops 546878105 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1415073919 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1417052801 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986854 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu
|
|||
system.cpu.num_load_insts 115884756 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548302 # Number of branches fetched
|
||||
|
|
@ -215,14 +215,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 548695379 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
|
|
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n
|
|||
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1064880 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1064880 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1064678 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
||||
|
|
@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917
|
|||
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
|
|
@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
|||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses
|
||||
|
|
@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
|||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -409,92 +409,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 9788 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 9788 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 253923000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 253923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 253923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 253923000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 253923000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 251687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251687000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 251687000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251687000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22040.013888 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21845.933513 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21845.933513 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109779 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.replacements 110394 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713329 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.110965 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831623 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27180 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18829920 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1064880 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1064880 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255527 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255527 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743598 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 743598 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8781 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 999125 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1007906 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8781 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 999125 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1007906 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100733 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100733 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2740 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2740 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39060 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39060 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2740 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 139793 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 142533 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2740 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 139793 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142533 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 255472 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 255472 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743385 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 743385 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998857 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1008075 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998857 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1008075 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2303 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 39273 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2303 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 140061 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 142364 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142364 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000938500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 8477621500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1064678 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1064678 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -507,30 +513,30 @@ system.cpu.l2cache.demand_accesses::total 1150439 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282751 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282751 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.237827 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.237827 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.049907 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.049907 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.237827 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122742 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -539,70 +545,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 96032 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96032 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 792 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 792 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100733 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100733 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2740 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2740 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39060 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39060 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2740 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 139793 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 96330 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution
|
||||
|
|
@ -610,51 +617,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 109779 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 110394 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 41800 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 96032 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 12399 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100733 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100733 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 41800 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393497 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 393497 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15268160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15268160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadResp 41576 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 11920 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 100788 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 251058 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 250615 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 251058 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 250615 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.647861 # Number of seconds simulated
|
||||
sim_ticks 1647861059500 # Number of ticks simulated
|
||||
final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.650527 # Number of seconds simulated
|
||||
sim_ticks 1650526667500 # Number of ticks simulated
|
||||
final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 657040 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1309397988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 327616 # Number of bytes of host memory used
|
||||
host_seconds 1258.49 # Real time elapsed on the host
|
||||
host_inst_rate 726731 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1450624585 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 327760 # Number of bytes of host memory used
|
||||
host_seconds 1137.80 # Real time elapsed on the host
|
||||
sim_insts 826877110 # Number of instructions simulated
|
||||
sim_ops 1528988702 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 551 # Number of system calls
|
||||
system.cpu.numCycles 3295722119 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3301053335 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 826877110 # Number of instructions committed
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu
|
|||
system.cpu.num_load_insts 384102157 # Number of load instructions
|
||||
system.cpu.num_store_insts 149160186 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 149758583 # Number of branches fetched
|
||||
|
|
@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1528988702 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2514362 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
|
|
@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n
|
|||
system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2323227 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 2323200 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
|
||||
|
|
@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458
|
|||
system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1253 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
|
|
@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n
|
|||
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 2814 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses
|
||||
|
|
@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003
|
|||
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -270,92 +270,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1253 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1253 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 348182 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.replacements 348438 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 29288.473875 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3847001 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.102472 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.252047 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.876987 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.639049 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004005 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.250759 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.893813 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 41466677 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 933 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2139476 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2140409 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206327 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206327 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1881 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1881 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172655 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 172655 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1881 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 378982 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 380863 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1881 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 380863 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 41466938 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 41466938 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 2323200 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 2323200 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 584688 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 584688 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554724 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1554724 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 2139412 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2140417 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 2139412 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2140417 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278187500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 12278187500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107652500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 107652500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 107652500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22553283000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22660935500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 107652500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22553283000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22660935500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2323200 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 2323200 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -368,30 +374,30 @@ system.cpu.l2cache.demand_accesses::total 2521272 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.151060 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.668443 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150482 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.151060 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.026657 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.026657 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52534.290271 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52534.290271 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.237468 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.237468 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.291443 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52534.290271 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.122697 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.291443 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260865 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.260865 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099970 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099970 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.150507 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.151057 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.150507 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.151057 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.026653 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.026653 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59509.397457 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59509.397457 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.165417 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.165417 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -400,60 +406,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 293174 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293174 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 275 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 275 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206327 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206327 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1881 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1881 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172655 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172655 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1881 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 378982 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 380863 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1881 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 378982 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 380863 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8768903000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8768903000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 80007000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 80007000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7337878500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7337878500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 80007000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16106781500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16186788500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 80007000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16106781500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16186788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 293208 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214627500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214627500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89562500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89562500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89562500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762823000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18852385500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89562500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762823000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18852385500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -462,8 +468,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
|
||||
|
|
@ -471,53 +478,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 348182 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 174536 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 293174 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 53553 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206327 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206327 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadResp 174499 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 727623 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 727569 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 727623 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 727569 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu
|
|||
sim_ticks 225710988500 # Number of ticks simulated
|
||||
final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 311102 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 311102 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 176136084 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304484 # Number of bytes of host memory used
|
||||
host_seconds 1281.46 # Real time elapsed on the host
|
||||
host_inst_rate 329346 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 329346 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 186465123 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304340 # Number of bytes of host memory used
|
||||
host_seconds 1210.47 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -482,6 +482,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3187 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3187 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5165 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 5165 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 5165 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -528,8 +530,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 114772 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 114772 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 3187 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 3187 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1273 # number of ReadCleanReq hits
|
||||
|
|
@ -566,8 +570,10 @@ system.cpu.l2cache.demand_miss_latency::total 593982000
|
|||
system.cpu.l2cache.overall_miss_latency::cpu.inst 291102500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 302879500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 593982000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 3187 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 3187 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5165 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -668,8 +674,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 3187 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution
|
||||
|
|
@ -677,22 +684,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 967
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 842944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9330 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 9330 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9330 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 10485000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.567335 # Number of seconds simulated
|
||||
sim_ticks 567335097500 # Number of ticks simulated
|
||||
final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.567385 # Number of seconds simulated
|
||||
sim_ticks 567385356500 # Number of ticks simulated
|
||||
final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1348015 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1918345002 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301916 # Number of bytes of host memory used
|
||||
host_seconds 295.74 # Real time elapsed on the host
|
||||
host_inst_rate 1390819 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1390819 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1979434182 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 302276 # Number of bytes of host memory used
|
||||
host_seconds 286.64 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 1134670195 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134770713 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664609 # Number of instructions committed
|
||||
|
|
@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu
|
|||
system.cpu.num_load_insts 94754511 # Number of load instructions
|
||||
system.cpu.num_store_insts 73520765 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1134670195 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1134770713 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
|
|
@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 398664665 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 764 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
|
||||
|
|
@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n
|
|||
system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4152 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152
|
|||
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -221,28 +221,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id
|
||||
|
|
@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n
|
|||
system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3673 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses
|
||||
|
|
@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009
|
|||
system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits
|
||||
|
|
@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 7174 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7174 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution
|
||||
|
|
@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 950
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7174 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.215510 # Number of seconds simulated
|
||||
sim_ticks 215510486500 # Number of ticks simulated
|
||||
final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.215512 # Number of seconds simulated
|
||||
sim_ticks 215512229500 # Number of ticks simulated
|
||||
final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 166248 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 199599 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 131220473 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326292 # Number of bytes of host memory used
|
||||
host_seconds 1642.35 # Real time elapsed on the host
|
||||
host_inst_rate 175368 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 210548 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 138419960 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 326400 # Number of bytes of host memory used
|
||||
host_seconds 1556.94 # Real time elapsed on the host
|
||||
sim_insts 273037857 # Number of instructions simulated
|
||||
sim_ops 327812214 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu
|
|||
system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 1015627 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1235976 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2251603 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1015627 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1015627 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1015627 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1235976 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2251603 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7582 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 215510247500 # Total gap between requests
|
||||
system.physmem.totGap 215511990500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 894 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52026250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1510 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 320.169536 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 189.396997 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 331.756940 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 550 36.42% 36.42% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 336 22.25% 58.68% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 179 11.85% 70.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 73 4.83% 75.36% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 74 4.90% 80.26% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 52 3.44% 83.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 33 2.19% 85.89% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 29 1.92% 87.81% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 184 12.19% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1510 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 54741000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 196903500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 7219.86 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25969.86 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da
|
|||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6062 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6065 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 79.99 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 28423931.35 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
|
||||
system.physmem.avgGap 28424161.24 # Average gap between requests
|
||||
system.physmem.pageHitRate 79.99 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 5019840 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 2739000 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.715971 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 5641560180 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 124356115500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 144111263400 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 668.704665 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 206876360250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 1436474750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.actEnergy 6373080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 3477375 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.792285 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 5809762620 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 124208569500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 144133083255 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 668.805913 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 206629350750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1684213750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 32816918 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 32816919 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 16892731 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBLookups 17497038 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 15468343 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage
|
||||
system.cpu.branchPred.BTBHitPct 88.405495 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
|
|
@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 431020973 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 431024459 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037857 # Number of instructions committed
|
||||
system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.578612 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.633468 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.578625 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.633463 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 427416966 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 3607493 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 1354 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3085.807941 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.807941 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.753371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.753371 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
|
||||
|
|
@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 7285 # n
|
|||
system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7290 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 138607500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 138607500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 393622500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393622500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 532230000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 532230000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 532230000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 532230000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 73058.339053 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 73008.230453 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508
|
|||
system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111882000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 111882000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219521500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219521500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 331403500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 331403500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331641500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 331641500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 36873 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 36871 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1923.837997 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 72548794 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 38807 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1869.477002 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1923.837997 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.939374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.939374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
|
||||
|
|
@ -547,42 +547,42 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1485
|
|||
system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 72548791 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38810 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 72548794 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 72548794 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 72548794 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 72548794 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 72548794 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 72548794 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 38808 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 38808 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 38808 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 38808 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 38808 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 38808 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 741346000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 741346000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 741346000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 741346000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 741346000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 741346000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 72587602 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 72587602 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 72587602 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 72587602 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 72587602 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 72587602 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000535 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000535 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000535 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19088.843082 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19088.843082 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19102.916924 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19102.916924 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19102.916924 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19102.916924 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19102.916924 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19102.916924 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -591,40 +591,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38810 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 38810 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 38810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 38810 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38810 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38810 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702029000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 702029000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 702029000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702029000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 702029000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.writebacks::writebacks 36871 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 36871 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 38808 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 38808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 38808 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 38808 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 38808 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 702539000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 702539000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 702539000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 702539000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 702539000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 702539000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000535 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000535 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000535 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000535 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18088.868848 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18102.942692 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18102.942692 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18102.942692 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18102.942692 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18102.942692 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18102.942692 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4197.348676 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 57958 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.tagsinuse 4197.336283 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 57954 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5644 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.268958 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 10.268249 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.816119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 353.814210 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.192128 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.329945 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy
|
||||
|
|
@ -636,22 +638,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172241 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 540762 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 540762 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 540730 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 540730 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 21970 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 21970 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 35388 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 35388 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 35386 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 35386 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 291 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 291 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 35388 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 35386 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 35695 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 35388 # number of overall hits
|
||||
system.cpu.l2cache.demand_hits::total 35693 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 35386 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 35695 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 35693 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3422 # number of ReadCleanReq misses
|
||||
|
|
@ -664,56 +668,58 @@ system.cpu.l2cache.demand_misses::total 7626 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3422 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7626 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 214741500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 214741500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257334000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 257334000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 104502500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 104502500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 257334000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 319244000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 576578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 257334000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 319244000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 576578000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215012500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 215012500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257866500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 257866500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106408000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106408000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 257866500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 321420500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 579287000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 257866500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 321420500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 579287000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1010 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 21970 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 21970 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 38810 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 38810 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 38808 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::total 38808 # number of ReadCleanReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1641 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadSharedReq_accesses::total 1641 # number of ReadSharedReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 38810 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 38808 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 43321 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 38810 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 43319 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 38808 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 43321 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 43319 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.088173 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.088173 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.088178 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.088178 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.822669 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.822669 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088173 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088178 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.176035 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.176043 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088178 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75199.883109 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77409.259259 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77409.259259 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75606.871230 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75199.883109 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75938.154139 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75606.871230 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.176043 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75337.245971 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -744,79 +750,80 @@ system.cpu.l2cache.demand_mshr_misses::total 7582
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186472500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186472500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223532000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223532000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90324000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90324000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223532000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 276796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 500328500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223532000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 276796500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 500328500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088126 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.175027 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.175027 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 81544 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 38329 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 21970 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 228 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99585 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 109845 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3889728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 4243072 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.476679 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 28198 65.09% 65.09% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15121 34.91% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 43319 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 78653000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 58211498 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6787957 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 4728 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2854 # Transaction distribution
|
||||
|
|
@ -837,9 +844,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 7582 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 40239750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.517243 # Number of seconds simulated
|
||||
sim_ticks 517243165500 # Number of ticks simulated
|
||||
final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.517291 # Number of seconds simulated
|
||||
sim_ticks 517291025500 # Number of ticks simulated
|
||||
final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 702843 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 843789 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1332923086 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 322968 # Number of bytes of host memory used
|
||||
host_seconds 388.05 # Real time elapsed on the host
|
||||
host_inst_rate 635145 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 762516 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1204648551 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323584 # Number of bytes of host memory used
|
||||
host_seconds 429.41 # Real time elapsed on the host
|
||||
sim_insts 272739286 # Number of instructions simulated
|
||||
sim_ops 327433744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu
|
|||
system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1034486331 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1034582051 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739286 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu
|
|||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563503 # Number of branches fetched
|
||||
|
|
@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 327812214 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
|
|
@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n
|
|||
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475
|
|||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -335,26 +335,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
|
|
@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n
|
|||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
|
||||
|
|
@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045
|
|||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -408,44 +408,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13796 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
|
|
@ -455,8 +457,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
|
||||
|
|
@ -481,20 +485,22 @@ system.cpu.l2cache.demand_misses::total 6832 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150075000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 150075000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137027500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 137027500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72007000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 72007000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 137027500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 222082000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 359109500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 137027500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 222082000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 359109500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -519,18 +525,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -551,18 +557,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 121515000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 121515000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 110947500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 110947500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58327000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58327000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110947500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 179842000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 290789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110947500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 179842000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 290789500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -575,18 +581,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -595,8 +601,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
|
||||
|
|
@ -604,22 +611,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
@ -644,9 +651,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 6833 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7261500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 34588500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.286279 # Number of seconds simulated
|
||||
sim_ticks 1286278511500 # Number of ticks simulated
|
||||
final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.288319 # Number of seconds simulated
|
||||
sim_ticks 1288319411500 # Number of ticks simulated
|
||||
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1389844 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1925210162 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 305148 # Number of bytes of host memory used
|
||||
host_seconds 668.12 # Real time elapsed on the host
|
||||
host_inst_rate 1465054 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1465054 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2032611527 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306300 # Number of bytes of host memory used
|
||||
host_seconds 633.82 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18509184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18646976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289206 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 107125 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14389717 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14496842 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107125 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107125 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3317876 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3317876 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3317876 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107125 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14389717 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17814717 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 2572557023 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2576638823 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
|
|
@ -89,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu
|
|||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2572557023 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2576638823 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
|
|
@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.261358 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1046537500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261358 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
|
|
@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n
|
|||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18597166000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18597166000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696410000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3696410000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22293576000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22293576000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22293576000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22293576000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28562.173298 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28562.173298 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 89031 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 89031 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88866 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
|
|
@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528
|
|||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17885652000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17885652000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3627396000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3627396000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21513048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21513048000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21513048000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21513048000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.486224 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486224 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
|
||||
|
|
@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n
|
|||
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 6168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 170684500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 170684500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 170684500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 170684500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 170684500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 170684500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
|
||||
|
|
@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007
|
|||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27672.584306 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27672.584306 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -298,93 +298,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 4618 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 4618 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164516500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 164516500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164516500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 164516500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164516500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 164516500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258580 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32657.927159 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207050 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291314 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.143467 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 258847 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2486.879631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.811890 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.075894 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001520 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.919227 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996641 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12902296 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12902296 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 89031 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 89031 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4015 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 4015 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488956 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488956 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491322 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 495337 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491322 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 495337 # number of overall hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 495307 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2153 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2153 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222558 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222558 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289206 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291359 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289206 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291359 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499032000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3499032000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113105000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 113105000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11684343000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11684343000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 113105000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15183375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15296480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 113105000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15183375000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15296480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 89031 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 89031 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291389 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -399,28 +405,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 780528
|
|||
system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.349060 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312795 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312795 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370526 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370526 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -431,58 +437,58 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 238 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 238 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2153 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2153 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222558 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222558 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289206 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291359 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289206 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2832552000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2832552000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91575000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91575000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9458763000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9458763000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91575000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12291315000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12382890000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91575000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12291315000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12382890000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.349060 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312795 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312795 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -491,8 +497,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution
|
||||
|
|
@ -500,51 +507,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55651776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258580 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258847 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 224711 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190417 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224741 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190447 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224711 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839818 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839818 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22914688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22914688 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 548514 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 548519 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 548514 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 548514 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 815261292 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 548519 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1456808792 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,95 +1,95 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.542258 # Number of seconds simulated
|
||||
sim_ticks 542257676500 # Number of ticks simulated
|
||||
final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.542265 # Number of seconds simulated
|
||||
sim_ticks 542265386500 # Number of ticks simulated
|
||||
final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 169610 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 208813 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 143560034 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325880 # Number of bytes of host memory used
|
||||
host_seconds 3777.22 # Real time elapsed on the host
|
||||
host_inst_rate 179877 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 221452 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 152251725 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 325476 # Number of bytes of host memory used
|
||||
host_seconds 3561.64 # Real time elapsed on the host
|
||||
sim_insts 640655085 # Number of instructions simulated
|
||||
sim_ops 788730744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18474304 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18637888 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288661 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 291217 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291175 # Number of read requests accepted
|
||||
system.physmem.bw_read::cpu.inst 301668 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 34068750 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 34370418 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 301668 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 301668 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 7801110 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 7801110 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 7801110 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 301668 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 34068750 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42171528 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 291217 # Number of read requests accepted
|
||||
system.physmem.writeReqs 66098 # Number of write requests accepted
|
||||
system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.readBursts 291217 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
|
||||
system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side
|
||||
system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM
|
||||
system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue
|
||||
system.physmem.bytesWritten 4228800 # Total number of bytes written to DRAM
|
||||
system.physmem.bytesReadSys 18637888 # Total read bytes from the system interface side
|
||||
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
|
||||
system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue
|
||||
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
||||
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18282 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18135 # Per bank write bursts
|
||||
system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write
|
||||
system.physmem.perBankRdBursts::0 18283 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::1 18129 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18173 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18273 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18400 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18176 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17989 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::3 18184 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::4 18283 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::5 18405 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::6 18181 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::7 17993 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::8 18030 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18104 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18195 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18214 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18267 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::9 18058 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::10 18107 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::11 18199 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::12 18220 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::13 18271 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
|
||||
system.physmem.perBankRdBursts::15 18260 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4098 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::5 4222 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4092 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4097 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
|
||||
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 542257582000 # Total gap between requests
|
||||
system.physmem.totGap 542265360500 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 291175 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::6 291217 # Read request sizes (log2)
|
||||
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
||||
|
|
@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr
|
|||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 290512 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
|
|
@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh
|
|||
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4015 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::15 894 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::17 4016 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::28 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::31 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
||||
|
|
@ -193,43 +193,42 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
|||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.bytesPerActivate::samples 111115 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 205.591972 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 133.871353 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 256.553383 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 45879 41.29% 41.29% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 43676 39.31% 80.60% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 9414 8.47% 89.07% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 1626 1.46% 90.53% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 693 0.62% 91.16% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 670 0.60% 91.76% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 551 0.50% 92.72% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 8091 7.28% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 111115 # Bytes accessed per row activation
|
||||
system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::mean 48.511200 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::gmean 34.259636 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::stdev 506.474106 # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
|
||||
system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.447598 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.427351 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.833980 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3118 77.62% 77.62% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2868100000 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst
|
||||
system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes
|
||||
system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::mean 16.444749 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::gmean 16.424614 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::stdev 0.831636 # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::16 3124 77.75% 77.75% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::17 1 0.02% 77.78% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::18 893 22.22% 100.00% # Writes before turning the bus around for reads
|
||||
system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads
|
||||
system.physmem.totQLat 2873170250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 8327545250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 9876.83 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28626.83 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -239,49 +238,49 @@ system.physmem.busUtil 0.33 # Da
|
|||
system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads
|
||||
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 194250 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51642 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads
|
||||
system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 194203 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 51643 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 1517768.15 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 693.324021 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states
|
||||
system.physmem.avgGap 1517611.52 # Average gap between requests
|
||||
system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_0.readEnergy 1136101200 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 215537760 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 107646010785 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 230928516000 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 375994196925 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 693.386081 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 383467912500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 18107180000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 140682990000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 693.447269 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states
|
||||
system.physmem_1.actEnergy 419141520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 228698250 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 1132419600 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 107856715275 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 230743687500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 376010934465 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 693.416947 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 383162755000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 18107180000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 140991278500 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 154805770 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.lookups 154805774 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 105138294 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBLookups 90693368 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 91.615652 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 19277596 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions.
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
|
|
@ -401,24 +400,24 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 1084515353 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1084530773 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 640655085 # Number of instructions committed
|
||||
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.692823 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.590729 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.692847 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.590721 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 1025899528 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 58631245 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 778339 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4092.484104 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484104 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
|
|
@ -454,14 +453,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n
|
|||
system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 851729 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770851500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 24770851500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105356000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 10105356000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 34876207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 34876207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 34876207500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 34876207500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -486,14 +485,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 40954.320047 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 40947.540239 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -502,8 +501,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 88920 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88920 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 88693 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88693 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 902 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
|
||||
|
|
@ -522,16 +521,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296
|
|||
system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24041947500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24041947500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067670500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067670500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29109618000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 29109618000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29111406000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 29111406000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -542,24 +541,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 23591 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1713.095631 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 291576507 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 11505.662813 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095631 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
|
||||
|
|
@ -567,44 +566,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58
|
|||
system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 291576499 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 583229042 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 583229042 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 291576507 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 291576507 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 291576507 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 291576507 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 291576507 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 291576507 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 25343 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 498728500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 498728500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 498728500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 498728500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 498728500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 498728500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 291601850 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 291601850 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 291601850 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 291601850 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 291601850 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 291601850 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 19679.142169 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 19679.142169 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -613,93 +612,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 23591 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 23591 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25343 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 25343 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 25343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 473386500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 473386500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473386500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 473386500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18679.181628 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18679.181628 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18679.181628 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18679.181628 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18679.181628 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18679.181628 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 258395 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 258813 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32576.208282 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1245284 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 291557 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.271151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2603.470497 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 85.754116 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29886.983669 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.079452 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002617 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.912078 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.994147 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2812 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29412 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29319 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 13211317 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 13211317 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 88920 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 88920 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 13211735 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 13211735 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88693 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88693 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 22257 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 22257 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22765 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 22765 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490574 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490574 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 22765 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493805 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 516570 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 22765 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493805 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 516570 # number of overall hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 22781 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490516 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490516 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 22781 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493747 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 516528 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 22781 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493747 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 516528 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2578 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2578 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222539 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222539 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288630 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291208 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291208 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2562 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 2562 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222597 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222597 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 2562 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288688 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 291250 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2562 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288688 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 291250 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929759500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4929759500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194891500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 194891500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17821559500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17821559500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 194891500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 22751319000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22946210500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 194891500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 22751319000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22946210500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88693 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88693 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 22257 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 22257 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25343 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -714,28 +719,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 782435
|
|||
system.cpu.l2cache.overall_accesses::total 807778 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101724 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101724 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312067 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312067 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101724 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368887 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.360505 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101093 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101093 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312148 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312148 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101093 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368961 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.360557 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101093 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368961 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.360557 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74590.481306 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74590.481306 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76070.062451 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76070.062451 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80061.993198 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -756,58 +761,54 @@ system.cpu.l2cache.demand_mshr_hits::total 32 #
|
|||
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222570 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222570 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288661 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 291218 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288661 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 291218 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268849500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268849500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169007000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169007000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15594098500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15594098500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169007000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19862948000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20031955000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169007000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19862948000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20031955000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100896 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312110 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312110 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.360517 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.360517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -816,8 +817,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution
|
||||
|
|
@ -825,51 +827,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621888 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55766720 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258395 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 258813 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.071523 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1061152 99.49% 99.49% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5424 0.51% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1066591 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 917138000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 225084 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190644 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 225126 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190686 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 225084 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839092 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22865472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 225126 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839218 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 839218 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22868160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 547917 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 548001 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 547917 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 548001 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 547917 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 548001 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 918049500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1554665000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.043724 # Number of seconds simulated
|
||||
sim_ticks 1043723537500 # Number of ticks simulated
|
||||
final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.045756 # Number of seconds simulated
|
||||
sim_ticks 1045756396500 # Number of ticks simulated
|
||||
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 832063 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1358287943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323064 # Number of bytes of host memory used
|
||||
host_seconds 768.41 # Real time elapsed on the host
|
||||
host_inst_rate 734670 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 902587 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1201635964 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323928 # Number of bytes of host memory used
|
||||
host_seconds 870.28 # Real time elapsed on the host
|
||||
sim_insts 639366787 # Number of instructions simulated
|
||||
sim_ops 785501035 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 2087447075 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 2091512793 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 639366787 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu
|
|||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 137364860 # Number of branches fetched
|
||||
|
|
@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 788730744 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
|
||||
|
|
@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n
|
|||
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 89072 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 89072 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 88995 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003
|
|||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
|
|
@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n
|
|||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses
|
||||
|
|
@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
|||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -413,93 +413,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 8769 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8769 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 257579 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 257772 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 12984085 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12984085 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 89072 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 89072 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8439 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8439 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490322 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490322 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493552 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501991 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8439 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493552 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501991 # number of overall hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 501982 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1769 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1769 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222497 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222497 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1769 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288590 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 290359 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1769 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288590 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290359 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 290368 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -514,28 +520,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 782142
|
|||
system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.173295 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.173295 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312137 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312137 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173295 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368974 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.366453 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368974 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.366453 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -546,58 +552,54 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 184 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 184 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1769 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1769 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222497 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222497 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288590 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 290359 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -606,8 +608,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution
|
||||
|
|
@ -615,51 +618,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257579 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 224266 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190085 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224275 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 190094 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 224266 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836901 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 836901 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22813248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 546599 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 546561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 546599 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 546599 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 811365948 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 546561 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1452169448 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.623057 # Number of seconds simulated
|
||||
sim_ticks 2623057163500 # Number of ticks simulated
|
||||
final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.636720 # Number of seconds simulated
|
||||
sim_ticks 2636719559500 # Number of ticks simulated
|
||||
final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1405944 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2026548224 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297224 # Number of bytes of host memory used
|
||||
host_seconds 1294.35 # Real time elapsed on the host
|
||||
host_inst_rate 1488641 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1488641 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2156924734 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297352 # Number of bytes of host memory used
|
||||
host_seconds 1222.44 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 1951440 # Nu
|
|||
system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 29 # Number of system calls
|
||||
system.cpu.numCycles 5246114327 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5273439119 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1819780127 # Number of instructions committed
|
||||
|
|
@ -89,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu
|
|||
system.cpu.num_load_insts 449492741 # Number of load instructions
|
||||
system.cpu.num_store_insts 162429806 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5246114327 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5273439119 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
|
|
@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1826378509 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses
|
||||
|
|
@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n
|
|||
system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734
|
|||
system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -228,26 +228,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses
|
||||
|
|
@ -264,12 +265,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n
|
|||
system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 802 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses
|
||||
|
|
@ -282,12 +283,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55066.708229 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -296,55 +297,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43361500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 43361500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43361500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 43361500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43361500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 43361500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919524 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30534.757407 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.replacements 1919525 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1949316 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.377078 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218167130000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.972607 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.460854 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001189 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.469803 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.931847 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1062 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27300 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149600036 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149600036 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3679426 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3679426 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits
|
||||
|
|
@ -365,20 +370,22 @@ system.cpu.l2cache.demand_misses::total 1952242 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41075219500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41075219500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42150500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 42150500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61385220500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61385220500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 42150500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102460440000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102502590500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 42150500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102502590500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3679426 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3679426 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -403,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.214237 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -425,8 +432,8 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021962 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses
|
||||
|
|
@ -439,18 +446,18 @@ system.cpu.l2cache.demand_mshr_misses::total 1952242
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33251369500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33251369500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34130500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34130500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49694670500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49694670500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34130500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82946040000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 82980170500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34130500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82946040000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 82980170500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses
|
||||
|
|
@ -465,18 +472,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -485,7 +492,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
|
||||
|
|
@ -494,29 +502,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919524 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919525 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169857 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1021962 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782385 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782385 # Transaction distribution
|
||||
|
|
@ -526,19 +534,19 @@ system.membus.pkt_count::total 5823129 # Pa
|
|||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3872712 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3870887 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3872712 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 3870887 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.363368 # Number of seconds simulated
|
||||
sim_ticks 2363368369500 # Number of ticks simulated
|
||||
final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.377030 # Number of seconds simulated
|
||||
sim_ticks 2377029670500 # Number of ticks simulated
|
||||
final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1008024 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1548215415 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315828 # Number of bytes of host memory used
|
||||
host_seconds 1526.51 # Real time elapsed on the host
|
||||
host_inst_rate 970948 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1499891883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316204 # Number of bytes of host memory used
|
||||
host_seconds 1584.80 # Real time elapsed on the host
|
||||
sim_insts 1538759602 # Number of instructions simulated
|
||||
sim_ops 1658228915 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4726736739 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4754059341 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759602 # Number of instructions committed
|
||||
|
|
@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu
|
|||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462427 # Number of branches fetched
|
||||
|
|
@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032481 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
|
||||
|
|
@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n
|
|||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235
|
|||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
|
|
@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
|||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
|
||||
|
|
@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -405,93 +405,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 7 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 7 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33596000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 33596000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33596000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 33596000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33596000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 33596000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 37902000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 37902000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 37902000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52658.307210 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52658.307210 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919018 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.199290 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386233 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948786 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.382151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067869000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15515.970631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.734659 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15468.494001 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.473510 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000724 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472061 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946295 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 1919027 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31012.105366 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14386231 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948795 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.382116 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 150459065000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15503.034415 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.646166 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15485.424786 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.473115 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000722 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.472578 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946414 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1084 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26839 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1085 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1728 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149644895 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149644895 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3681379 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3681379 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107017 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107017 # number of ReadExReq hits
|
||||
system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107015 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6057123 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7164140 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7164162 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7164138 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7164160 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7164140 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7164162 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782132 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782132 # number of ReadExReq misses
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7164138 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7164160 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782134 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 616 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168964 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951096 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951712 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951098 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951714 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951096 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951712 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41062370000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41062370000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 32383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 32383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61386933500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61386933500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102449303500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102481686500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32383000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102449303500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102481686500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3681379 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3681379 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951098 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951714 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46537233000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 36689000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69569093500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 36689000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116106326500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116143015500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 36689000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -504,30 +510,30 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n
|
|||
system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414013 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414013 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214048 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214100 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214101 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214048 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214100 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.562565 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.562565 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52569.805195 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52569.805195 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59560.064935 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59513.461065 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59560.064935 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59508.198204 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59508.214574 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -538,58 +544,58 @@ system.cpu.l2cache.fast_writes 0 # nu
|
|||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1021127 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 226 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 226 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782132 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782132 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951096 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951712 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -598,8 +604,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution
|
||||
|
|
@ -607,51 +614,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919018 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919027 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169580 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1021127 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 897054 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782132 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 897056 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782134 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5821605 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190261696 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3870264 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3869897 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870264 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870264 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7969342268 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 3869897 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9772290268 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,45 +1,45 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.882285 # Number of seconds simulated
|
||||
sim_ticks 5882284743500 # Number of ticks simulated
|
||||
final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 5.895948 # Number of seconds simulated
|
||||
sim_ticks 5895947852500 # Number of ticks simulated
|
||||
final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 704974 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1378571885 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317252 # Number of bytes of host memory used
|
||||
host_seconds 4266.94 # Real time elapsed on the host
|
||||
host_inst_rate 730138 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1137621 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1431096811 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 317400 # Number of bytes of host memory used
|
||||
host_seconds 4119.88 # Real time elapsed on the host
|
||||
sim_insts 3008081022 # Number of instructions simulated
|
||||
sim_ops 4686862596 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 11764569487 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 11791895705 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 3008081022 # Number of instructions committed
|
||||
|
|
@ -60,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu
|
|||
system.cpu.num_load_insts 1239184746 # Number of load instructions
|
||||
system.cpu.num_store_insts 438528338 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 248500691 # Number of branches fetched
|
||||
|
|
@ -100,19 +100,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 4686862596 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 9108581 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
|
||||
|
|
@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n
|
|||
system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3682721 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3682716 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
|
||||
|
|
@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677
|
|||
system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 10 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n
|
|||
system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 675 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses
|
||||
|
|
@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
|||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -267,89 +267,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 10 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 10 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1919162 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 1919169 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7161483 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7161483 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7161483 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7161483 # number of overall hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168761 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168761 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951194 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951869 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951194 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951869 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41077744500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 41077744500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35453500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 35453500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61359978500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 61359978500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 35453500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 102473176500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 35453500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -366,26 +372,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024
|
|||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -394,60 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022288 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 1022289 # number of writebacks
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution
|
||||
|
|
@ -465,53 +472,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919162 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1919169 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 1169436 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1022288 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1169437 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 896090 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 782433 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 3870262 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 3870249 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 3870262 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks)
|
||||
system.membus.snoop_fanout::total 3870249 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu
|
|||
sim_ticks 51910606500 # Number of ticks simulated
|
||||
final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 339215 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 339215 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 191602600 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303192 # Number of bytes of host memory used
|
||||
host_seconds 270.93 # Real time elapsed on the host
|
||||
host_inst_rate 362776 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 362776 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 204910533 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 303308 # Number of bytes of host memory used
|
||||
host_seconds 253.33 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # By
|
|||
system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35331250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 35329750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s
|
||||
|
|
@ -227,28 +227,28 @@ system.physmem_0.preEnergy 1914000 # En
|
|||
system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ)
|
||||
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.907929 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states
|
||||
system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ)
|
||||
system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ)
|
||||
system.physmem_0.averagePower 669.907919 # Core power per rank (mW)
|
||||
system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states
|
||||
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ)
|
||||
system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ)
|
||||
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
|
||||
system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
|
||||
system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.156857 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states
|
||||
system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ)
|
||||
system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ)
|
||||
system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ)
|
||||
system.physmem_1.averagePower 670.156855 # Core power per rank (mW)
|
||||
system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states
|
||||
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.cpu.branchPred.lookups 11441088 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted
|
||||
|
|
@ -305,12 +305,12 @@ system.cpu.ipc 0.885205 # IP
|
|||
system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
|
|
@ -340,12 +340,12 @@ system.cpu.dcache.overall_misses::cpu.data 3431 #
|
|||
system.cpu.dcache.overall_misses::total 3431 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -364,12 +364,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000129
|
|||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -398,12 +398,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2230
|
|||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -414,20 +414,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084
|
|||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13850 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
||||
|
|
@ -483,6 +483,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13850 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13850 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -509,13 +511,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890
|
|||
system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.794194 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046720 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy
|
||||
|
|
@ -530,8 +532,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits
|
||||
|
|
@ -556,20 +560,22 @@ system.cpu.l2cache.demand_misses::total 5319 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5319 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128817000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128817000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236600000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 236600000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 236600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164634000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 401234000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 236600000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164634000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 401234000 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -594,18 +600,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294763 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -626,18 +632,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5319
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -650,18 +656,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -670,8 +676,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution
|
||||
|
|
@ -679,23 +686,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 485
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
|
||||
|
|
@ -719,9 +726,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 5319 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu
|
|||
sim_ticks 130772642500 # Number of ticks simulated
|
||||
final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 233615 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 246267 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177290947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321196 # Number of bytes of host memory used
|
||||
host_seconds 737.62 # Real time elapsed on the host
|
||||
host_inst_rate 246902 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 260275 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 187375043 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 321308 # Number of bytes of host memory used
|
||||
host_seconds 697.92 # Real time elapsed on the host
|
||||
sim_insts 172317810 # Number of instructions simulated
|
||||
sim_ops 181650743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -591,6 +591,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 2888 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 2888 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -638,8 +640,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2524 # number of ReadCleanReq hits
|
||||
|
|
@ -676,8 +680,10 @@ system.cpu.l2cache.demand_miss_latency::total 294557500
|
|||
system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -788,8 +794,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution
|
||||
|
|
@ -797,22 +804,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,52 +4,52 @@ sim_seconds 1.869358 # Nu
|
|||
sim_ticks 1869358498000 # Number of ticks simulated
|
||||
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2397277 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2397276 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68943602925 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377676 # Number of bytes of host memory used
|
||||
host_seconds 27.11 # Real time elapsed on the host
|
||||
host_inst_rate 2198730 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2198729 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 63233555824 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 377528 # Number of bytes of host memory used
|
||||
host_seconds 29.56 # Real time elapsed on the host
|
||||
sim_insts 65000470 # Number of instructions simulated
|
||||
sim_ops 65000470 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.inst 763776 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66536960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 106240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 68174144 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 763776 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 106240 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 870016 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7835712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7835712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11934 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1039640 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 1660 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1065221 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122433 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122433 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 408577 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35593472 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 56832 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36469272 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 408577 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 56832 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 465409 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4191658 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4191658 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4191658 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 408577 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35593472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 56832 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40660931 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -86,61 +86,6 @@ system.cpu0.itb.data_accesses 0 # DT
|
|||
system.cpu0.numCycles 3738723791 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 49478313 # Number of instructions committed
|
||||
system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1124639 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 46202260 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 197598 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 12536155 # number of memory refs
|
||||
system.cpu0.num_load_insts 7783785 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4752370 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
|
||||
system.cpu0.Branches 7530941 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 49486454 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed
|
||||
|
|
@ -231,6 +176,61 @@ system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # n
|
|||
system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
|
||||
system.cpu0.committedInsts 49478313 # Number of instructions committed
|
||||
system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1124639 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 46202260 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 197598 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 12536155 # number of memory refs
|
||||
system.cpu0.num_load_insts 7783785 # Number of load instructions
|
||||
system.cpu0.num_store_insts 4752370 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
|
||||
system.cpu0.Branches 7530941 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 49486454 # Class of executed instruction
|
||||
system.cpu0.dcache.tags.replacements 1781373 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks.
|
||||
|
|
@ -303,8 +303,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 632989 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 632989 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 632988 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.icache.tags.replacements 618298 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use
|
||||
|
|
@ -354,6 +354,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 618298 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -390,61 +392,6 @@ system.cpu1.itb.data_accesses 0 # DT
|
|||
system.cpu1.numCycles 3738297607 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 15522157 # Number of instructions committed
|
||||
system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 493140 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 14295542 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 198941 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 4961785 # number of memory refs
|
||||
system.cpu1.num_load_insts 2849089 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2112696 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
|
||||
system.cpu1.Branches 2214162 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 15525873 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed
|
||||
|
|
@ -518,6 +465,61 @@ system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # nu
|
|||
system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
|
||||
system.cpu1.committedInsts 15522157 # Number of instructions committed
|
||||
system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 493140 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 14295542 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 198941 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 4961785 # number of memory refs
|
||||
system.cpu1.num_load_insts 2849089 # Number of load instructions
|
||||
system.cpu1.num_store_insts 2112696 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
|
||||
system.cpu1.Branches 2214162 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
|
||||
system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction
|
||||
system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 15525873 # Class of executed instruction
|
||||
system.cpu1.dcache.tags.replacements 201756 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks.
|
||||
|
|
@ -639,6 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks
|
||||
system.cpu1.icache.writebacks::total 380671 # number of writebacks
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
|
|
@ -737,22 +741,22 @@ system.iocache.cache_copies 0 # nu
|
|||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.l2c.tags.replacements 999687 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65320.982503 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4249853 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064737 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.991458 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 999918 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 55911.121944 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4939.470586 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4176.774738 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 179.034361 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.580874 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.853136 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.075370 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063733 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002732 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063753 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu1.data 0.001749 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id
|
||||
|
|
@ -761,62 +765,66 @@ system.l2c.tags.age_task_id_blocks_1024::2 6123 #
|
|||
system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 46365678 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46365678 # Number of data accesses
|
||||
system.l2c.Writeback_hits::writebacks 777520 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 777520 # number of Writeback hits
|
||||
system.l2c.tags.tag_accesses 46365909 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 46365909 # Number of data accesses
|
||||
system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 168079 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 606990 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379552 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986542 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626685 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129013 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755698 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 606990 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738161 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379552 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910319 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 606990 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738161 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379552 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910319 # number of overall hits
|
||||
system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits
|
||||
system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits
|
||||
system.l2c.ReadSharedReq_hits::total 755692 # number of ReadSharedReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 607076 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 379556 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 185614 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1910402 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 607076 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 738156 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 379556 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 185614 # number of overall hits
|
||||
system.l2c.overall_hits::total 1910402 # number of overall hits
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses
|
||||
system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113873 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu0.data 113874 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 124942 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11934 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1660 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13594 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926611 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1033 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11934 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040484 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1660 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066180 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11934 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040484 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1660 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12102 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066180 # number of overall misses
|
||||
system.l2c.Writeback_accesses::writebacks 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 777520 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.ReadExReq_misses::total 124943 # number of ReadExReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::cpu1.inst 1656 # number of ReadCleanReq misses
|
||||
system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu0.data 926615 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::cpu1.data 1035 # number of ReadSharedReq misses
|
||||
system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1656 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 12104 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066097 # number of overall misses
|
||||
system.l2c.WritebackDirty_accesses::writebacks 777519 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 777519 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 719211 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 719211 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -848,25 +856,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.882002 # mi
|
|||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505318 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426393 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019282 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004355 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013592 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596545 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551073 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019282 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584987 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004355 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358199 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019282 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584987 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004355 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358199 # miss rate for overall accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -875,47 +883,47 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
|||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 80913 # number of writebacks
|
||||
system.l2c.writebacks::total 80913 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 80921 # number of writebacks
|
||||
system.l2c.writebacks::total 80921 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7449 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948866 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948782 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 122433 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917961 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917844 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 126472 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124247 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941417 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 126447 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 124222 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3174012 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3218086 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3343081 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73455634 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76124370 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2205834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2205642 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2205834 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2205834 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2205642 # Request fanout histogram
|
||||
system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter.
|
||||
system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
|
|
@ -926,8 +934,9 @@ system.toL2Bus.trans_dist::ReadReq 7449 # Tr
|
|||
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 777520 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1862622 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution
|
||||
|
|
@ -940,17 +949,17 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5
|
|||
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758075 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 243126098 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1083281 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141075 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106201 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.308342 # Request fanout histogram
|
||||
system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 1083512 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6383226 89.39% 89.39% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
|
||||
|
|
@ -958,7 +967,7 @@ system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re
|
|||
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141075 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
|
|
@ -4,42 +4,42 @@ sim_seconds 1.829332 # Nu
|
|||
sim_ticks 1829332273500 # Number of ticks simulated
|
||||
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2390951 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2390950 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72850763127 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 374092 # Number of bytes of host memory used
|
||||
host_seconds 25.11 # Real time elapsed on the host
|
||||
host_inst_rate 2238603 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2238602 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 68208828665 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 373932 # Number of bytes of host memory used
|
||||
host_seconds 26.82 # Real time elapsed on the host
|
||||
sim_insts 60038341 # Number of instructions simulated
|
||||
sim_ops 60038341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67693184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7414144 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115846 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -76,61 +76,6 @@ system.cpu.itb.data_accesses 0 # DT
|
|||
system.cpu.numCycles 3658670905 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064400 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
|
|
@ -216,6 +161,61 @@ system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # nu
|
|||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.cpu.committedInsts 60038341 # Number of instructions committed
|
||||
system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913563 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115702 # number of memory refs
|
||||
system.cpu.num_load_insts 9747508 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368194 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064400 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050179 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 2042728 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks.
|
||||
|
|
@ -284,8 +284,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833493 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833493 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833492 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 919605 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use
|
||||
|
|
@ -335,19 +335,21 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 919605 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 919605 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992219 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560066 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.312600 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 992425 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||
|
|
@ -356,40 +358,44 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 48753828 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48753828 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905373 # number of overall hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058082 # number of overall misses
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -408,16 +414,16 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000
|
|||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -426,8 +432,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74334 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74365 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -439,8 +445,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2127019 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution
|
||||
|
|
@ -450,21 +457,21 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075788 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 1075994 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013252 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018475 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
||||
|
|
@ -563,42 +570,42 @@ system.iocache.writebacks::writebacks 41512 # nu
|
|||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 7184 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948374 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 948291 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 9838 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 9838 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 115846 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917156 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116946 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 917027 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 116931 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107665 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141709 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266686 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 2150005 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 2149824 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2150005 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2150005 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 2149824 # Request fanout histogram
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1159279 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1411237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22604281025 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628452 # Number of bytes of host memory used
|
||||
host_seconds 123.16 # Real time elapsed on the host
|
||||
host_inst_rate 1280554 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1558869 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24968967598 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 628580 # Number of bytes of host memory used
|
||||
host_seconds 111.49 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT
|
|||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
|
|
@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
|
|
@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
|
|
@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu
|
|||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
|
|
@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu
|
|||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
|
|
@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
|||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1171566 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1426194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22843865684 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624228 # Number of bytes of host memory used
|
||||
host_seconds 121.87 # Real time elapsed on the host
|
||||
host_inst_rate 1269873 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1545867 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24760705808 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 624348 # Number of bytes of host memory used
|
||||
host_seconds 112.43 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -209,6 +209,8 @@ system.cpu.itb.accesses 147044108 # DT
|
|||
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 142772879 # Number of instructions committed
|
||||
system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
||||
|
|
@ -266,8 +268,6 @@ system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 177219912 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
|
||||
|
|
@ -400,6 +400,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109913 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use
|
||||
|
|
@ -433,8 +435,10 @@ system.cpu.l2cache.tags.data_accesses 40582495 # Nu
|
|||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 682040 # number of Writeback hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits
|
||||
|
|
@ -479,8 +483,10 @@ system.cpu.l2cache.overall_misses::total 181651 # nu
|
|||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 682040 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
||||
|
|
@ -545,8 +551,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 1797302 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -559,11 +566,11 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 205238629 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 182974 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram
|
||||
|
|
@ -683,7 +690,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
|||
system.membus.trans_dist::ReadResp 74202 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138139 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu
|
|||
sim_ticks 2783867052000 # Number of ticks simulated
|
||||
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1174884 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1430233 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 22908545755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623708 # Number of bytes of host memory used
|
||||
host_seconds 121.52 # Real time elapsed on the host
|
||||
host_inst_rate 1268879 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1544656 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 24741311872 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 623824 # Number of bytes of host memory used
|
||||
host_seconds 112.52 # Real time elapsed on the host
|
||||
sim_insts 142772879 # Number of instructions simulated
|
||||
sim_ops 173803124 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -226,6 +226,8 @@ system.cpu0.itb.accesses 74781709 # DT
|
|||
system.cpu0.numCycles 5536444792 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu0.committedInsts 72626333 # Number of instructions committed
|
||||
system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses
|
||||
|
|
@ -283,8 +285,6 @@ system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Cl
|
|||
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 89742700 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
||||
system.cpu0.dcache.tags.replacements 819402 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks.
|
||||
|
|
@ -459,6 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks
|
||||
system.cpu0.icache.writebacks::total 1699214 # number of writebacks
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -599,6 +601,8 @@ system.cpu1.itb.accesses 72262399 # DT
|
|||
system.cpu1.numCycles 88040649 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu1.committedInsts 70146546 # Number of instructions committed
|
||||
system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses
|
||||
|
|
@ -656,8 +660,6 @@ system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Cl
|
|||
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 87477212 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
||||
|
|
@ -801,8 +803,10 @@ system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # nu
|
|||
system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 14441 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 682264 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 682264 # number of Writeback hits
|
||||
system.l2c.WritebackDirty_hits::writebacks 682264 # number of WritebackDirty hits
|
||||
system.l2c.WritebackDirty_hits::total 682264 # number of WritebackDirty hits
|
||||
system.l2c.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits
|
||||
system.l2c.WritebackClean_hits::total 1667206 # number of WritebackClean hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
||||
|
|
@ -872,8 +876,10 @@ system.l2c.ReadReq_accesses::cpu0.itb.walker 2288
|
|||
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 14449 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 682264 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 682264 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::writebacks 682264 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackDirty_accesses::total 682264 # number of WritebackDirty accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
||||
|
|
@ -955,7 +961,7 @@ system.membus.trans_dist::ReadReq 40087 # Tr
|
|||
system.membus.trans_dist::ReadResp 74196 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 138133 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 7977 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
||||
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
|
|
@ -1044,8 +1050,9 @@ system.toL2Bus.trans_dist::ReadReq 71244 # Tr
|
|||
system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::Writeback 682264 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 1797078 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
||||
system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
||||
|
|
@ -1058,11 +1065,11 @@ system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2
|
|||
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 205266733 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.toL2Bus.snoops 182968 # Total snoops (count)
|
||||
system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram
|
||||
system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,55 +4,57 @@ sim_seconds 5.112152 # Nu
|
|||
sim_ticks 5112152301500 # Number of ticks simulated
|
||||
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1349307 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2762327 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 34477807791 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659588 # Number of bytes of host memory used
|
||||
host_seconds 148.27 # Real time elapsed on the host
|
||||
host_inst_rate 1265336 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2590419 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32332152611 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 659496 # Number of bytes of host memory used
|
||||
host_seconds 158.11 # Real time elapsed on the host
|
||||
sim_insts 200066731 # Number of instructions simulated
|
||||
sim_ops 409580371 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 853568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10615616 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11497920 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 853568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 853568 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9269440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9269440 # Number of bytes written to this memory
|
||||
system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13337 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165869 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 179655 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144835 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144835 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166968 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2076545 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2249135 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166968 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166968 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813217 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813217 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813217 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 166968 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4062352 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224308568 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.committedInsts 200066731 # Number of instructions committed
|
||||
system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses
|
||||
|
|
@ -110,8 +112,6 @@ system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Cl
|
|||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409581402 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.dcache.tags.replacements 1621902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks.
|
||||
|
|
@ -279,6 +279,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 792216 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 792216 # number of writebacks
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use
|
||||
|
|
@ -335,22 +337,22 @@ system.cpu.itb_walker_cache.cache_copies 0 # nu
|
|||
system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 106193 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340112 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170151 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.507414 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 106204 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51850.671935 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2531.452775 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10441.669005 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.791178 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038627 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159327 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
|
|
@ -359,52 +361,56 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349
|
|||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 39255968 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255968 # Number of data accesses
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538777 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179780 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179780 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779384 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779384 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275199 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284751 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779384 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454979 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2243915 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779384 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454979 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2243915 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134641 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134641 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13338 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13338 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32163 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 32169 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13338 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166804 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180148 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13338 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166804 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180148 # number of overall misses
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538777 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538777 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 180051 # number of overall misses
|
||||
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses)
|
||||
|
|
@ -427,24 +433,24 @@ system.cpu.l2cache.overall_accesses::cpu.data 1621783
|
|||
system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428219 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428219 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016826 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016826 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024601 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024427 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016826 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102852 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074317 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016826 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102852 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074317 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -453,8 +459,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98168 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98168 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98177 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -466,8 +472,9 @@ system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Tr
|
|||
system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 880405 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution
|
||||
|
|
@ -479,17 +486,17 @@ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50735040 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 279335545 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203459 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930673 # Request fanout histogram
|
||||
system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 203470 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911114 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram
|
||||
|
|
@ -497,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re
|
|||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930673 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram
|
||||
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
|
||||
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
|
||||
|
|
@ -602,16 +609,16 @@ system.iocache.writebacks::writebacks 46667 # nu
|
|||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.membus.trans_dist::ReadReq 13857337 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903747 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 13903644 # Transaction distribution
|
||||
system.membus.trans_dist::WriteReq 13943 # Transaction distribution
|
||||
system.membus.trans_dist::WriteResp 13943 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 144835 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8392 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134360 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134355 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46410 # Transaction distribution
|
||||
system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution
|
||||
system.membus.trans_dist::CleanEvict 8271 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution
|
||||
system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 134351 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 134346 # Transaction distribution
|
||||
system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution
|
||||
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
|
||||
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
|
||||
system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution
|
||||
|
|
@ -620,32 +627,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav
|
|||
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470559 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28213119 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358794 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17793920 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43218681 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46269945 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.snoops 0 # Total snoops (count)
|
||||
system.membus.snoop_fanout::samples 14256770 # Request fanout histogram
|
||||
system.membus.snoop_fanout::samples 14256561 # Request fanout histogram
|
||||
system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
|
||||
system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram
|
||||
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14255074 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram
|
||||
system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 2 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256770 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 14256561 # Request fanout histogram
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu
|
|||
sim_ticks 21900500 # Number of ticks simulated
|
||||
final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 94413 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 94393 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 324370159 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297000 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 101932 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101910 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 350189482 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296592 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 6372 # Number of instructions simulated
|
||||
sim_ops 6372 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000033 # Number of seconds simulated
|
||||
sim_ticks 32545500 # Number of ticks simulated
|
||||
final_tick 32545500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000036 # Number of seconds simulated
|
||||
sim_ticks 35667500 # Number of ticks simulated
|
||||
final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 507828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 507304 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2581337246 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294696 # Number of bytes of host memory used
|
||||
host_inst_rate 607241 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 606492 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3381446720 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294520 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6390 # Number of instructions simulated
|
||||
sim_ops 6390 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 546680801 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 330368254 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 877049054 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 546680801 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 546680801 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 330368254 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 877049054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 17 # Number of system calls
|
||||
system.cpu.numCycles 65091 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 71335 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 6390 # Number of instructions committed
|
||||
|
|
@ -82,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu
|
|||
system.cpu.num_load_insts 1190 # Number of load instructions
|
||||
system.cpu.num_store_insts 868 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 65091 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 71335 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1050 # Number of branches fetched
|
||||
|
|
@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 6400 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 103.756988 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.756988 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025331 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
|
||||
|
|
@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n
|
|||
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 168 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168
|
|||
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5130000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3942000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9072000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 9072000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9072000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 9072000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 127.992231 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.992231 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
|
||||
|
|
@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n
|
|||
system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 279 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15304500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15304500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15304500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
|
||||
|
|
@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587
|
|||
system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54854.838710 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54854.838710 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279
|
|||
system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15025500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15025500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15025500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53854.838710 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53854.838710 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.470347 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.998222 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.472125 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003906 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001723 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses
|
||||
|
|
@ -344,18 +344,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 446 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4987500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4987500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -380,18 +380,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -412,18 +412,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3102500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3102500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4037500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4037500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7140000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18955500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7140000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18955500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -436,18 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -479,11 +479,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
|
|||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 373 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
|
||||
|
|
@ -504,8 +504,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 446 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000012 # Nu
|
|||
sim_ticks 12363500 # Number of ticks simulated
|
||||
final_tick 12363500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79707 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 412680664 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295680 # Number of bytes of host memory used
|
||||
host_inst_rate 83593 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 83552 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 432562452 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 295260 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_ops 2387 # Number of ops (including micro ops) simulated
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 16524500 # Number of ticks simulated
|
||||
final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000018 # Number of seconds simulated
|
||||
sim_ticks 18239500 # Number of ticks simulated
|
||||
final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 315037 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 314537 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2013954906 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293376 # Number of bytes of host memory used
|
||||
host_inst_rate 407753 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 406852 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2874172707 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 293212 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_ops 2577 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu
|
|||
system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 245 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
|
|
@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 4 # Number of system calls
|
||||
system.cpu.numCycles 33049 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 36479 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2577 # Number of instructions committed
|
||||
|
|
@ -82,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu
|
|||
system.cpu.num_load_insts 419 # Number of load instructions
|
||||
system.cpu.num_store_insts 298 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 33049 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 36479 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 396 # Number of branches fetched
|
||||
|
|
@ -122,17 +122,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2585 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 47.431392 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.431392 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011580 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011580 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses
|
||||
|
|
@ -152,14 +152,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n
|
|||
system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 82 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -176,14 +176,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -200,14 +200,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82
|
|||
system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1458000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4428000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4428000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -216,27 +216,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 80.038009 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 80.038009 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.039081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.039081 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 5335 # Number of data accesses
|
||||
|
|
@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n
|
|||
system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 163 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
|
||||
|
|
@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032
|
|||
system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -290,39 +290,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163
|
|||
system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8802500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 8802500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 8802500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8802500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 8802500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 107.126637 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.141583 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.985054 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003269 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses
|
||||
|
|
@ -338,18 +338,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 245 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8558000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 8558000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -374,18 +374,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -406,18 +406,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1147500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6928000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6928000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6928000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3485000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 10413000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6928000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3485000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 10413000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -430,18 +430,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -475,7 +475,7 @@ system.cpu.toL2Bus.snoop_fanout::total 245 # Re
|
|||
system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 218 # Transaction distribution
|
||||
|
|
@ -498,8 +498,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 245 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.7 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000030 # Nu
|
|||
sim_ticks 29949500 # Number of ticks simulated
|
||||
final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 110305 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 129095 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 716958322 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313816 # Number of bytes of host memory used
|
||||
host_inst_rate 117235 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 137200 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 761957462 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313960 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 4605 # Number of instructions simulated
|
||||
sim_ops 5391 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -567,6 +567,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 3 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 3 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 322 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 322 # number of demand (read+write) MSHR misses
|
||||
|
|
@ -609,6 +611,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 253
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4181 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4181 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 2 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits
|
||||
|
|
@ -643,6 +647,8 @@ system.cpu.l2cache.demand_miss_latency::total 31692000
|
|||
system.cpu.l2cache.overall_miss_latency::cpu.inst 22597500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 9094500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 31692000 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 322 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -749,7 +755,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution
|
||||
|
|
@ -757,22 +763,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 103
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20608 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.101911 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.302853 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.300891 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 423 89.81% 89.81% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 48 10.19% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 421 89.96% 89.96% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 47 10.04% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 238500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu
|
|||
sim_ticks 17170000 # Number of ticks simulated
|
||||
final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 50361 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 58973 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188251031 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313812 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_inst_rate 54905 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 64292 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 205230571 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313448 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
sim_insts 4592 # Number of instructions simulated
|
||||
sim_ops 5378 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -979,6 +979,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 86.400000
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 93 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 93 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -1178,18 +1180,18 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.102041 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.303046 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 396 89.80% 89.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 45 10.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 221500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25848500 # Number of ticks simulated
|
||||
final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28298500 # Number of ticks simulated
|
||||
final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 341128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 397821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1927554064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 312280 # Number of bytes of host memory used
|
||||
host_inst_rate 321731 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 375194 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1990329160 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311896 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4566 # Number of instructions simulated
|
||||
sim_ops 5330 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
|||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
||||
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 51697 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 56597 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4566 # Number of instructions committed
|
||||
|
|
@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu
|
|||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1008 # Number of branches fetched
|
||||
|
|
@ -208,17 +208,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5391 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
|
||||
|
|
@ -242,14 +242,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n
|
|||
system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 141 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -270,14 +270,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141
|
|||
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -310,27 +310,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
|
||||
|
|
@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
|||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
|
||||
|
|
@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323
|
|||
system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -378,45 +378,47 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 1 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
|
||||
|
|
@ -442,18 +444,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11818000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11818000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4305000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4305000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -478,18 +480,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -510,18 +512,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9568000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9568000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3485000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3485000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9568000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5312500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 14880500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9568000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5312500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 14880500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -534,18 +536,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -565,23 +567,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
|
|||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 43 # Transaction distribution
|
||||
|
|
@ -602,8 +604,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 350 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
sim_ticks 22451000 # Number of ticks simulated
|
||||
final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 22454000 # Number of ticks simulated
|
||||
final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 76638 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76622 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 344943613 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294148 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 82798 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 82780 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 372464129 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294232 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 4986 # Number of instructions simulated
|
||||
sim_ops 4986 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20992 # Nu
|
|||
system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 469 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
|
|
@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
|||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 22364000 # Total gap between requests
|
||||
system.physmem.totGap 22367000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
|
|
@ -206,9 +206,9 @@ system.physmem.totBusLat 2345000 # To
|
|||
system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 10.44 # Data bus utilization in percentage
|
||||
|
|
@ -220,7 +220,7 @@ system.physmem.readRowHits 355 # Nu
|
|||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 47684.43 # Average gap between requests
|
||||
system.physmem.avgGap 47690.83 # Average gap between requests
|
||||
system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
|
||||
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
|
||||
|
|
@ -279,7 +279,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 44903 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 44909 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
|
||||
|
|
@ -308,8 +308,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu
|
|||
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle
|
||||
system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
|
||||
system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
|
||||
system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
|
||||
|
|
@ -436,7 +436,7 @@ system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Ty
|
|||
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
||||
system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
|
||||
system.cpu.iq.rate 0.176759 # Inst issue rate
|
||||
system.cpu.iq.rate 0.176735 # Inst issue rate
|
||||
system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
|
||||
system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
|
||||
|
|
@ -480,13 +480,13 @@ system.cpu.iew.exec_nop 1483 # nu
|
|||
system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
|
||||
system.cpu.iew.exec_branches 1353 # Number of branches executed
|
||||
system.cpu.iew.exec_stores 1053 # Number of stores executed
|
||||
system.cpu.iew.exec_rate 0.170835 # Inst execution rate
|
||||
system.cpu.iew.exec_rate 0.170812 # Inst execution rate
|
||||
system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
|
||||
system.cpu.iew.wb_producers 2832 # num instructions producing a value
|
||||
system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
|
||||
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle
|
||||
system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle
|
||||
system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
|
||||
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
|
||||
|
|
@ -558,27 +558,27 @@ system.cpu.commit.bw_lim_events 116 # nu
|
|||
system.cpu.rob.rob_reads 23467 # The number of ROB reads
|
||||
system.cpu.rob.rob_writes 21056 # The number of ROB writes
|
||||
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.committedInsts 4986 # Number of Instructions Simulated
|
||||
system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
|
||||
system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads
|
||||
system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads
|
||||
system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads
|
||||
system.cpu.int_regfile_reads 10418 # number of integer regfile reads
|
||||
system.cpu.int_regfile_writes 5064 # number of integer regfile writes
|
||||
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
||||
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
||||
system.cpu.misc_regfile_reads 158 # number of misc regfile reads
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
|
||||
|
|
@ -683,14 +683,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943
|
|||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 17 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
|
||||
|
|
@ -709,12 +709,12 @@ system.cpu.icache.demand_misses::cpu.inst 432 # n
|
|||
system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 432 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
|
||||
|
|
@ -727,12 +727,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.218292
|
|||
system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -741,6 +741,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 17 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 17 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -753,33 +755,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 331
|
|||
system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
|
||||
|
|
@ -789,6 +791,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
||||
|
|
@ -809,16 +813,18 @@ system.cpu.l2cache.overall_misses::cpu.data 141 #
|
|||
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -845,16 +851,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1
|
|||
system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -877,16 +883,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141
|
|||
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -901,16 +907,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -919,7 +925,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
|
||||
|
|
@ -927,23 +933,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 91
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
|
||||
|
|
@ -967,7 +973,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
|
|||
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 469 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30902500 # Number of ticks simulated
|
||||
final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000034 # Number of seconds simulated
|
||||
sim_ticks 33912500 # Number of ticks simulated
|
||||
final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 459853 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 459290 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2521006690 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291832 # Number of bytes of host memory used
|
||||
host_inst_rate 492168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 491565 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2961014581 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292188 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu
|
|||
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
|
|
@ -49,7 +49,7 @@ system.cpu.itb.hits 0 # DT
|
|||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 7 # Number of system calls
|
||||
system.cpu.numCycles 61805 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 67825 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5624 # Number of instructions committed
|
||||
|
|
@ -68,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu
|
|||
system.cpu.num_load_insts 1132 # Number of load instructions
|
||||
system.cpu.num_store_insts 902 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 61805 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 67825 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 883 # Number of branches fetched
|
||||
|
|
@ -108,17 +108,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5625 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 86.152837 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.152837 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021033 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021033 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
|
||||
|
|
@ -138,14 +138,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n
|
|||
system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 137 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -162,14 +162,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067388
|
|||
system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -186,14 +186,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137
|
|||
system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4698000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4698000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7398000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7398000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7398000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -202,27 +202,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 13 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 129.096971 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 129.096971 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.063036 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.063036 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
|
||||
|
|
@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n
|
|||
system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 295 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
|
||||
|
|
@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435
|
|||
system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -270,48 +270,52 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 13 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 13 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15846500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15846500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15846500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15846500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15846500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15846500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53716.949153 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53716.949153 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53716.949153 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 183.690355 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.238740 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.451615 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005606 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -330,18 +334,20 @@ system.cpu.l2cache.demand_misses::total 430 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 430 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 15383000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4567500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 4567500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -366,18 +372,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -398,18 +404,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2125000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2125000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12453000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12453000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3697500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3697500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12453000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5822500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 18275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12453000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5822500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 18275500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -422,18 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -442,7 +448,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution
|
||||
|
|
@ -450,27 +456,27 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 87
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 380 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
|
||||
|
|
@ -491,8 +497,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 430 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu
|
|||
sim_ticks 19923000 # Number of ticks simulated
|
||||
final_tick 19923000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 93968 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 93947 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 323084408 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 291680 # Number of bytes of host memory used
|
||||
host_inst_rate 101947 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 101922 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 350504038 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292056 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
sim_insts 5792 # Number of instructions simulated
|
||||
sim_ops 5792 # Number of ops (including micro ops) simulated
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27803500 # Number of ticks simulated
|
||||
final_tick 27803500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30526500 # Number of ticks simulated
|
||||
final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 506128 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 505504 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2635153066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292480 # Number of bytes of host memory used
|
||||
host_inst_rate 511867 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 511179 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2925956101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292840 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5327 # Number of instructions simulated
|
||||
sim_ops 5327 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu
|
|||
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 586976460 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308450375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 895426835 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 586976460 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 586976460 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308450375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 895426835 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 55607 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 61053 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5327 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu
|
|||
system.cpu.num_load_insts 723 # Number of load instructions
|
||||
system.cpu.num_store_insts 678 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 55606.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1121 # Number of branches fetched
|
||||
|
|
@ -90,17 +90,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5370 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 82.111103 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.111103 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses
|
||||
|
|
@ -120,14 +120,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n
|
|||
system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 135 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2929000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7384000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -144,14 +144,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 54240.740741 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 54696.296296 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -168,14 +168,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135
|
|||
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2875000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4374000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7249000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7249000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -184,27 +184,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53240.740741 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53696.296296 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 117.031458 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 117.031458 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057144 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 10999 # Number of data accesses
|
||||
|
|
@ -220,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n
|
|||
system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 257 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14053500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14053500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14053500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
|
||||
|
|
@ -238,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850
|
|||
system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54682.879377 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54682.879377 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -258,39 +258,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257
|
|||
system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13796500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13796500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13796500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53682.879377 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53682.879377 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 142.152541 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.493414 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.659127 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003555 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004338 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses
|
||||
|
|
@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 389 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13388000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13388000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10838000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10838000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10838000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 16533000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10838000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 16533000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -451,9 +451,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
|
|||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 308 # Transaction distribution
|
||||
|
|
@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 389 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000021 # Nu
|
|||
sim_ticks 20818000 # Number of ticks simulated
|
||||
final_tick 20818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 48919 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 88616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 189245943 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313416 # Number of bytes of host memory used
|
||||
host_inst_rate 50154 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 90851 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 194020392 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314048 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
sim_insts 5380 # Number of instructions simulated
|
||||
sim_ops 9747 # Number of ops (including micro ops) simulated
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 28359500 # Number of ticks simulated
|
||||
final_tick 28359500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000031 # Number of seconds simulated
|
||||
sim_ticks 30886500 # Number of ticks simulated
|
||||
final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 279983 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 506758 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1473373857 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 311136 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 150745 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 272977 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864611035 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310988 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 5381 # Number of instructions simulated
|
||||
sim_ops 9748 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -21,18 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu
|
|||
system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 361 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 512279836 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 302403075 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 814682910 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 512279836 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 512279836 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 302403075 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 814682910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 11 # Number of system calls
|
||||
system.cpu.numCycles 56719 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 61773 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 5381 # Number of instructions committed
|
||||
|
|
@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu
|
|||
system.cpu.num_load_insts 1053 # Number of load instructions
|
||||
system.cpu.num_store_insts 935 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 56718.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 1208 # Number of branches fetched
|
||||
|
|
@ -93,17 +93,17 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 9748 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 80.792611 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.792611 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses
|
||||
|
|
@ -123,14 +123,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n
|
|||
system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 134 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -147,14 +147,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404
|
|||
system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134
|
|||
system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2970000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4266000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4266000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7236000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7236000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -187,27 +187,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 105.543720 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.543720 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 13956 # Number of data accesses
|
||||
|
|
@ -223,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n
|
|||
system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 228 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12499500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12499500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12499500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses
|
||||
|
|
@ -241,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217
|
|||
system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54822.368421 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54822.368421 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -261,39 +261,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228
|
|||
system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12271500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12271500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12271500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53822.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53822.368421 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 134.010901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.539859 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.471042 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses
|
||||
|
|
@ -315,18 +315,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 361 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11918000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11918000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2887500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -351,18 +351,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -383,18 +383,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3357500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3357500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 9648000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 9648000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2337500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9648000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 15343000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9648000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5695000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 15343000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -452,7 +452,7 @@ system.cpu.toL2Bus.snoop_fanout::total 362 # Re
|
|||
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 282 # Transaction distribution
|
||||
|
|
@ -477,8 +477,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 361 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 6.4 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu
|
|||
sim_ticks 24832500 # Number of ticks simulated
|
||||
final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 79921 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 79915 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 155707227 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297588 # Number of bytes of host memory used
|
||||
host_seconds 0.16 # Real time elapsed on the host
|
||||
host_inst_rate 76523 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 76517 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 149086837 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297164 # Number of bytes of host memory used
|
||||
host_seconds 0.17 # Real time elapsed on the host
|
||||
sim_insts 12744 # Number of instructions simulated
|
||||
sim_ops 12744 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -905,6 +905,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753
|
|||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
|
||||
system.cpu.icache.writebacks::total 8 # number of writebacks
|
||||
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits
|
||||
|
|
@ -955,6 +957,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504
|
|||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses
|
||||
system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits
|
||||
system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
||||
|
|
@ -985,6 +989,8 @@ system.cpu.l2cache.demand_miss_latency::total 80021500
|
|||
system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles
|
||||
system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -1085,7 +1091,7 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 #
|
|||
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::CleanEvict 8 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution
|
||||
|
|
@ -1093,22 +1099,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 198
|
|||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 62592 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002028 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045015 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 984 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.cpu.toL2Bus.snoop_fanout::total 986 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu
|
|||
sim_ticks 26944000 # Number of ticks simulated
|
||||
final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 95332 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 95323 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 177899852 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294468 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_inst_rate 77815 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 77809 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 145216229 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 294808 # Number of bytes of host memory used
|
||||
host_seconds 0.19 # Real time elapsed on the host
|
||||
sim_insts 14436 # Number of instructions simulated
|
||||
sim_ops 14436 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000041 # Number of seconds simulated
|
||||
sim_ticks 41370500 # Number of ticks simulated
|
||||
final_tick 41370500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000044 # Number of seconds simulated
|
||||
sim_ticks 44282500 # Number of ticks simulated
|
||||
final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 454115 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 453939 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1238118753 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292408 # Number of bytes of host memory used
|
||||
host_inst_rate 498046 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 497817 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1453362434 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 292760 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 15162 # Number of instructions simulated
|
||||
sim_ops 15162 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu
|
|||
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 416 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 430064901 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 213485455 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 643550356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 430064901 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 430064901 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 213485455 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 643550356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.workload.num_syscalls 18 # Number of system calls
|
||||
system.cpu.numCycles 82741 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 88565 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 15162 # Number of instructions committed
|
||||
|
|
@ -50,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu
|
|||
system.cpu.num_load_insts 2231 # Number of load instructions
|
||||
system.cpu.num_store_insts 1452 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 82740.998000 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
|
||||
system.cpu.Branches 3363 # Number of branches fetched
|
||||
|
|
@ -90,14 +90,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
|
|||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 15207 # Class of executed instruction
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 97.990405 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.990405 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023923 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
|
||||
|
|
@ -122,14 +122,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n
|
|||
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 138 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
||||
|
|
@ -148,14 +148,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -172,14 +172,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138
|
|||
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2862000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4590000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4590000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 7452000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7452000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 7452000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
|
||||
|
|
@ -188,27 +188,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633
|
|||
system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 54000 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.tags.replacements 0 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 153.774939 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 153.774939 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.075085 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 30696 # Number of data accesses
|
||||
|
|
@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n
|
|||
system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 280 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 15318500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 15318500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 15318500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses
|
||||
|
|
@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411
|
|||
system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 54708.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 54708.928571 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -262,39 +262,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280
|
|||
system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 15038500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 15038500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 15038500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53708.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 53708.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 184.610716 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.093077 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.517640 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses
|
||||
|
|
@ -316,18 +316,18 @@ system.cpu.l2cache.demand_misses::total 416 # nu
|
|||
system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 416 # number of overall misses
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 14595500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2782500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses)
|
||||
|
|
@ -352,18 +352,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 #
|
|||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
|
|
@ -384,18 +384,18 @@ system.cpu.l2cache.demand_mshr_misses::total 416
|
|||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3612500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3612500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11815500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2252500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11815500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11815500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5865000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses
|
||||
|
|
@ -408,18 +408,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215
|
|||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter.
|
||||
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
||||
|
|
@ -453,7 +453,7 @@ system.cpu.toL2Bus.snoop_fanout::total 418 # Re
|
|||
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.trans_dist::ReadResp 331 # Transaction distribution
|
||||
|
|
@ -476,8 +476,8 @@ system.membus.snoop_fanout::min_value 0 # Re
|
|||
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.membus.snoop_fanout::total 416 # Request fanout histogram
|
||||
system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 5.0 # Layer utilization (%)
|
||||
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 4.7 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ sim_seconds 0.000062 # Nu
|
|||
sim_ticks 61610000 # Number of ticks simulated
|
||||
final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 402374 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 402048 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3843418590 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 682268 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_inst_rate 589960 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 589258 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5631112330 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 681568 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 6440 # Number of instructions simulated
|
||||
sim_ops 6440 # Number of ops (including micro ops) simulated
|
||||
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
|
@ -546,17 +546,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
|||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 511 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 449 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 511 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 449 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu
|
|||
sim_ticks 49855000 # Number of ticks simulated
|
||||
final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 351391 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 406109 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3506224066 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 699088 # Number of bytes of host memory used
|
||||
host_inst_rate 371629 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 429475 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 3707242713 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 698952 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 4988 # Number of instructions simulated
|
||||
sim_ops 5770 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -640,17 +640,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
|||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 461 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.095445 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.294147 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 391 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0.086957 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0.282132 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 417 90.46% 90.46% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 44 9.54% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 357 91.30% 91.30% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 34 8.70% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 461 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 391 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@ sim_seconds 0.000059 # Nu
|
|||
sim_ticks 58892000 # Number of ticks simulated
|
||||
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 489554 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 489001 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5114816745 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679136 # Number of bytes of host memory used
|
||||
host_inst_rate 477419 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 476853 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 4988311028 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 679248 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
sim_insts 5624 # Number of instructions simulated
|
||||
sim_ops 5624 # Number of ops (including micro ops) simulated
|
||||
|
|
@ -532,17 +532,17 @@ system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side
|
|||
system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.l2bus.snoops 0 # Total snoops (count)
|
||||
system.l2bus.snoop_fanout::samples 528 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::samples 434 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::mean 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 528 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::0 434 100.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 528 # Request fanout histogram
|
||||
system.l2bus.snoop_fanout::total 434 # Request fanout histogram
|
||||
system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks)
|
||||
system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
||||
system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks)
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue