735 lines
84 KiB
Plaintext
735 lines
84 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.051911 # Number of seconds simulated
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sim_ticks 51910606500 # Number of ticks simulated
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final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 362776 # Simulator instruction rate (inst/s)
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host_op_rate 362776 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 204910533 # Simulator tick rate (ticks/s)
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host_mem_usage 303308 # Number of bytes of host memory used
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host_seconds 253.33 # Real time elapsed on the host
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sim_insts 91903089 # Number of instructions simulated
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sim_ops 91903089 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory
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system.physmem.bytes_read::total 340416 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5319 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 469 # Per bank write bursts
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system.physmem.perBankRdBursts::1 295 # Per bank write bursts
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system.physmem.perBankRdBursts::2 308 # Per bank write bursts
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system.physmem.perBankRdBursts::3 524 # Per bank write bursts
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system.physmem.perBankRdBursts::4 224 # Per bank write bursts
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system.physmem.perBankRdBursts::5 238 # Per bank write bursts
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system.physmem.perBankRdBursts::6 222 # Per bank write bursts
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system.physmem.perBankRdBursts::7 289 # Per bank write bursts
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system.physmem.perBankRdBursts::8 251 # Per bank write bursts
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system.physmem.perBankRdBursts::9 282 # Per bank write bursts
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system.physmem.perBankRdBursts::10 254 # Per bank write bursts
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system.physmem.perBankRdBursts::11 261 # Per bank write bursts
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system.physmem.perBankRdBursts::12 410 # Per bank write bursts
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system.physmem.perBankRdBursts::13 344 # Per bank write bursts
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system.physmem.perBankRdBursts::14 500 # Per bank write bursts
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system.physmem.perBankRdBursts::15 448 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 51910519000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 5319 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation
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system.physmem.totQLat 35329750 # Total ticks spent queuing
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system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.05 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 4332 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 9759450.84 # Average gap between requests
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system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ)
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system.physmem_0.averagePower 669.907919 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ)
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system.physmem_1.averagePower 670.156855 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states
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system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 11441088 # Number of BP lookups
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system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 20417089 # DTB read hits
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system.cpu.dtb.read_misses 43350 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 20460439 # DTB read accesses
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system.cpu.dtb.write_hits 6579898 # DTB write hits
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system.cpu.dtb.write_misses 278 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6580176 # DTB write accesses
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system.cpu.dtb.data_hits 26996987 # DTB hits
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system.cpu.dtb.data_misses 43628 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 27040615 # DTB accesses
|
|
system.cpu.itb.fetch_hits 22953519 # ITB hits
|
|
system.cpu.itb.fetch_misses 90 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 22953609 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 389 # Number of system calls
|
|
system.cpu.numCycles 103821213 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 91903089 # Number of instructions committed
|
|
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.129681 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.885205 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 157 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 26573200 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3431 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 107 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2230 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 13850 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 45922853 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 45922853 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 22937703 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 22937703 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 22937703 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 22937703 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 22937703 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 22937703 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 15816 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 15816 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 15816 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 15816 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 15816 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 15816 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 408931500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 408931500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 408931500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 408931500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 408931500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 408931500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 22953519 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 22953519 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 22953519 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 22953519 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 22953519 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 22953519 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 25855.557663 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 25855.557663 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 13850 # number of writebacks
|
|
system.cpu.icache.writebacks::total 13850 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 15816 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 15816 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 15816 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393116500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 393116500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393116500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 393116500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393116500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 393116500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24855.620890 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24855.620890 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24855.620890 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010985 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.075616 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3666 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 183 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 12647 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 12647 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 12726 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 12647 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 12726 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1719 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3168 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 3168 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 432 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 432 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 2151 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 5319 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 5319 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 15815 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 485 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 485 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 15815 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2230 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 18045 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 15815 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2230 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 18045 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985100 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200316 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200316 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.890722 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.890722 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200316 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.964574 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.294763 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1719 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3168 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3168 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 432 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 432 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 3600 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1719 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1719 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 5319 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 5319 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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