1605 lines
190 KiB
Plaintext
1605 lines
190 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 51.811412 # Number of seconds simulated
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sim_ticks 51811412441500 # Number of ticks simulated
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final_tick 51811412441500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 619887 # Simulator instruction rate (inst/s)
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host_op_rate 728480 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 38746850862 # Simulator tick rate (ticks/s)
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host_mem_usage 721116 # Number of bytes of host memory used
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host_seconds 1337.18 # Real time elapsed on the host
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sim_insts 828899207 # Number of instructions simulated
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sim_ops 974107036 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 141632 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 4651380 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 65025608 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 401792 # Number of bytes read from this memory
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system.physmem.bytes_read::total 70353980 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 4651380 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 4651380 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 61199552 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::total 61220132 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2213 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 113085 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1016038 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6278 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1139701 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 956243 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 958816 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 2734 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 89775 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1255044 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 7755 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1357886 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 89775 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 89775 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1181198 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1181596 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1181198 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 2734 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 89775 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1255441 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 7755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2539481 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1139701 # Number of read requests accepted
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system.physmem.writeReqs 958816 # Number of write requests accepted
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system.physmem.readBursts 1139701 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 958816 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 72891072 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 49792 # Total number of bytes read from write queue
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system.physmem.bytesWritten 61218752 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 70353980 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 61220132 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 778 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 295779 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 70381 # Per bank write bursts
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system.physmem.perBankRdBursts::1 75813 # Per bank write bursts
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system.physmem.perBankRdBursts::2 71139 # Per bank write bursts
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system.physmem.perBankRdBursts::3 67493 # Per bank write bursts
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system.physmem.perBankRdBursts::4 63564 # Per bank write bursts
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system.physmem.perBankRdBursts::5 70698 # Per bank write bursts
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system.physmem.perBankRdBursts::6 65929 # Per bank write bursts
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system.physmem.perBankRdBursts::7 63583 # Per bank write bursts
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system.physmem.perBankRdBursts::8 66194 # Per bank write bursts
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system.physmem.perBankRdBursts::9 109788 # Per bank write bursts
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system.physmem.perBankRdBursts::10 68376 # Per bank write bursts
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system.physmem.perBankRdBursts::11 70520 # Per bank write bursts
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system.physmem.perBankRdBursts::12 68080 # Per bank write bursts
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system.physmem.perBankRdBursts::13 71994 # Per bank write bursts
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system.physmem.perBankRdBursts::14 69489 # Per bank write bursts
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system.physmem.perBankRdBursts::15 65882 # Per bank write bursts
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system.physmem.perBankWrBursts::0 58404 # Per bank write bursts
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system.physmem.perBankWrBursts::1 62356 # Per bank write bursts
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system.physmem.perBankWrBursts::2 60883 # Per bank write bursts
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system.physmem.perBankWrBursts::3 59981 # Per bank write bursts
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system.physmem.perBankWrBursts::4 56389 # Per bank write bursts
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system.physmem.perBankWrBursts::5 60703 # Per bank write bursts
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system.physmem.perBankWrBursts::6 57931 # Per bank write bursts
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system.physmem.perBankWrBursts::7 57426 # Per bank write bursts
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system.physmem.perBankWrBursts::8 58562 # Per bank write bursts
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system.physmem.perBankWrBursts::9 60878 # Per bank write bursts
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system.physmem.perBankWrBursts::10 59750 # Per bank write bursts
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system.physmem.perBankWrBursts::11 62184 # Per bank write bursts
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system.physmem.perBankWrBursts::12 59419 # Per bank write bursts
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system.physmem.perBankWrBursts::13 62742 # Per bank write bursts
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system.physmem.perBankWrBursts::14 60987 # Per bank write bursts
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system.physmem.perBankWrBursts::15 57948 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 40 # Number of times write queue was full causing retry
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system.physmem.totGap 51811409612500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 43101 # Read request sizes (log2)
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system.physmem.readPktSize::3 13 # Read request sizes (log2)
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system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1096585 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 1 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 956243 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1112094 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 21162 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 399 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 468 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 547 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1194 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 625 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 281 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 324 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 109 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 107 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 71 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 13699 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 16507 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 54180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 55051 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::19 57086 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 56677 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 57597 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 58012 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 59157 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 58593 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::25 58964 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 62926 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 58374 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 57067 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 57736 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 55832 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 55140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 54594 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 869 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 656 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 609 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 521 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 434 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 410 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 325 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 428 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 353 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 231 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 333 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 174 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 186 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 149 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 98 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::59 115 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::60 107 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 113 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 155 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 450541 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 297.663263 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 171.634069 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 329.395643 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 180604 40.09% 40.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 109821 24.38% 64.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 39191 8.70% 73.16% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 22619 5.02% 78.18% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 15643 3.47% 81.65% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 11800 2.62% 84.27% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 10101 2.24% 86.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 8767 1.95% 88.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 51995 11.54% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 450541 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 53849 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 21.149826 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 337.005181 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-4095 53847 100.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 53849 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 53849 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 17.763431 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 17.132779 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 7.573717 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 51569 95.77% 95.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 271 0.50% 96.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 82 0.15% 96.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 312 0.58% 97.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 52 0.10% 97.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 350 0.65% 97.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 234 0.43% 98.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 17 0.03% 98.21% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::48-51 58 0.11% 98.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 145 0.27% 98.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 23 0.04% 98.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 22 0.04% 98.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 441 0.82% 99.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 31 0.06% 99.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 4 0.01% 99.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 4 0.01% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 3 0.01% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 53849 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 14314490470 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 35669296720 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 5694615000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12568.44 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31318.44 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 27.89 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 918030 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 726894 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.99 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 24689535.33 # Average gap between requests
|
|
system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1704243240 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 929894625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 4279041000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3071993040 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1294968358125 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 29950905933000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 34639928569110 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.577285 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 49825452803142 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1730096680000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 255862301858 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1701846720 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 928587000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 4604519400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3126405600 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3384069106080 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1295387816850 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 29950537986750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 34640356268400 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.585540 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 49824790858475 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1730096680000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 256517624025 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 185269 # Table walker walks requested
|
|
system.cpu.dtb.walker.walksLong 185269 # Table walker walks initiated with long descriptors
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12948 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144056 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
|
|
system.cpu.dtb.walker.walkWaitTime::samples 185250 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::mean 0.215924 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::stdev 70.777306 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::0-2047 185248 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::total 185250 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 157023 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 24782.458621 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 20866.161950 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 18013.175833 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::0-65535 155872 99.27% 99.27% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.27% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::131072-196607 991 0.63% 99.90% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::196608-262143 17 0.01% 99.91% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::327680-393215 22 0.01% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::393216-458751 34 0.02% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::total 157023 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walksPending::samples 3934185148 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::mean 0.600903 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::stdev 0.489713 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::0 1570120704 39.91% 39.91% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::1 2364064444 60.09% 100.00% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::total 3934185148 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walkPageSizes::4K 144057 91.75% 91.75% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::2M 12948 8.25% 100.00% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::total 157005 # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185269 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185269 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157005 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157005 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 342274 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 156094559 # DTB read hits
|
|
system.cpu.dtb.read_misses 137688 # DTB read misses
|
|
system.cpu.dtb.write_hits 141675607 # DTB write hits
|
|
system.cpu.dtb.write_misses 47581 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 70732 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 6720 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 156232247 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 141723188 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 297770166 # DTB hits
|
|
system.cpu.dtb.misses 185269 # DTB misses
|
|
system.cpu.dtb.accesses 297955435 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 118504 # Table walker walks requested
|
|
system.cpu.itb.walker.walksLong 118504 # Table walker walks initiated with long descriptors
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level3 107076 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walkWaitTime::samples 118504 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 118504 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 118504 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkCompletionTime::samples 108186 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::mean 28679.602721 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 24825.752216 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 21031.513378 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::0-65535 106793 98.71% 98.71% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.00% 98.71% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::131072-196607 1215 1.12% 99.84% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::262144-327679 67 0.06% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.03% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::458752-524287 12 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::total 108186 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walkPageSizes::4K 107076 98.97% 98.97% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 108186 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118504 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 118504 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108186 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 108186 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 226690 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 829409821 # ITB inst hits
|
|
system.cpu.itb.inst_misses 118504 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 50494 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 829528325 # ITB inst accesses
|
|
system.cpu.itb.hits 829409821 # DTB hits
|
|
system.cpu.itb.misses 118504 # DTB misses
|
|
system.cpu.itb.accesses 829528325 # DTB accesses
|
|
system.cpu.numCycles 103622824883 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed
|
|
system.cpu.committedInsts 828899207 # Number of instructions committed
|
|
system.cpu.committedOps 974107036 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 895578515 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 899571 # Number of float alu accesses
|
|
system.cpu.num_func_calls 49817464 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 125652530 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 895578515 # number of integer instructions
|
|
system.cpu.num_fp_insts 899571 # number of float instructions
|
|
system.cpu.num_int_register_reads 1295563811 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 709708276 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 1453001 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 214507812 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 213899539 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 297748170 # number of memory refs
|
|
system.cpu.num_load_insts 156084233 # Number of load instructions
|
|
system.cpu.num_store_insts 141663937 # Number of store instructions
|
|
system.cpu.num_idle_cycles 100539253419.334061 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 3083571463.665941 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.029758 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.970242 # Percentage of idle cycles
|
|
system.cpu.Branches 184944487 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 674583276 69.21% 69.21% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 2119587 0.22% 69.43% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 97316 0.01% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 156084233 16.01% 85.47% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 141663937 14.53% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 974660774 # Class of executed instruction
|
|
system.cpu.dcache.tags.replacements 9257757 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 288314388 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9258269 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 31.141284 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 110 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1200005027 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1200005027 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 146175483 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 146175483 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 134535173 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 134535173 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 372977 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 372977 # number of SoftPFReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::cpu.data 334025 # number of WriteLineReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::total 334025 # number of WriteLineReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3285857 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3285857 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 3569334 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 3569334 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 280710656 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 280710656 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 281083633 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 281083633 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4833353 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4833353 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1968837 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1968837 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 1108112 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 1108112 # number of SoftPFReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::cpu.data 1218438 # number of WriteLineReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::total 1218438 # number of WriteLineReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 285095 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 285095 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 6802190 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 6802190 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7910302 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7910302 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 82947634000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 82947634000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 66857595000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 66857595000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73267815000 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::total 73267815000 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4367237000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 4367237000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 149805229000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 149805229000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 149805229000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 149805229000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 151008836 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 151008836 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 136504010 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 136504010 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481089 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 1481089 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552463 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::total 1552463 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570952 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 3570952 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3569336 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 3569336 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 287512846 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 287512846 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 288993935 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 288993935 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032007 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.032007 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014423 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.014423 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748174 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.748174 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.784842 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::total 0.784842 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079837 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079837 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.023659 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.023659 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.027372 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.027372 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17161.509619 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 17161.509619 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33957.912717 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 33957.912717 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60132.575478 # average WriteLineReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60132.575478 # average WriteLineReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15318.532419 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15318.532419 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.088005 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 22023.088005 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18937.991116 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 18937.991116 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 7254734 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 7254734 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23450 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 23450 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21299 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 21299 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67486 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 67486 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 44749 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 44749 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 44749 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 44749 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4809903 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 4809903 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1947538 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1947538 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106332 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1106332 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1218438 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::total 1218438 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217609 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 217609 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 6757441 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 6757441 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 7863773 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 7863773 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76766734500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 76766734500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63925265000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 63925265000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20988734000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20988734000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72049377000 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72049377000 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989622500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989622500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140691999500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 140691999500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161680733500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 161680733500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6200659500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6200659500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217612000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217612000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12418271500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12418271500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031852 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031852 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014267 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014267 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746972 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746972 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.784842 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.784842 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060939 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060939 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023503 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.023503 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027211 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.027211 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15960.141920 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15960.141920 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32823.629115 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32823.629115 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18971.460647 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18971.460647 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59132.575478 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59132.575478 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13738.505760 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13738.505760 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20820.307495 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20820.307495 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20560.198457 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20560.198457 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183984.911875 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183984.911875 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.084846 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.084846 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184220.019285 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184220.019285 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 13402148 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 816007156 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 13402660 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 60.883970 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 842812486 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 842812486 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 816007156 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 816007156 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 816007156 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 816007156 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 816007156 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 816007156 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 13402665 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 13402665 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 13402665 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 13402665 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 13402665 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 13402665 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 183016744500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 183016744500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 183016744500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 183016744500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 183016744500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 183016744500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 829409821 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 829409821 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 829409821 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 829409821 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 829409821 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 829409821 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016159 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.016159 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.016159 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.016159 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.016159 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.016159 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13655.250243 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13655.250243 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13655.250243 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13655.250243 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13655.250243 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13655.250243 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 13402148 # number of writebacks
|
|
system.cpu.icache.writebacks::total 13402148 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13402665 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 13402665 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 13402665 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 13402665 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 13402665 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 13402665 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169614079500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 169614079500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169614079500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 169614079500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169614079500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 169614079500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016159 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.016159 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016159 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.016159 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12655.250243 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12655.250243 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12655.250243 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12655.250243 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12655.250243 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12655.250243 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1000398 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65223.179314 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 41597566 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1062477 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 39.151498 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 37712.043475 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 216.479752 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 326.532168 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8422.895801 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 18545.228118 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.575440 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003303 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004982 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.128523 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.282978 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995227 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 193 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61886 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2453 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5516 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53472 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.002945 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944305 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 371574999 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 371574999 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309727 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 241978 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 551705 # number of ReadReq hits
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 7254734 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 7254734 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 13400558 # number of WritebackClean hits
|
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system.cpu.l2cache.WritebackClean_hits::total 13400558 # number of WritebackClean hits
|
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system.cpu.l2cache.UpgradeReq_hits::cpu.data 8841 # number of UpgradeReq hits
|
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|
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|
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|
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system.cpu.l2cache.ReadCleanReq_hits::total 13332668 # number of ReadCleanReq hits
|
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system.cpu.l2cache.ReadSharedReq_hits::total 5913249 # number of ReadSharedReq hits
|
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system.cpu.l2cache.InvalidateReq_hits::cpu.data 738936 # number of InvalidateReq hits
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|
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system.cpu.l2cache.overall_hits::cpu.itb.walker 241978 # number of overall hits
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system.cpu.l2cache.overall_hits::cpu.inst 13332668 # number of overall hits
|
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system.cpu.l2cache.overall_hits::cpu.data 7502110 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::total 4300 # number of ReadReq misses
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system.cpu.l2cache.UpgradeReq_misses::total 32696 # number of UpgradeReq misses
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system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
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system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 69997 # number of ReadCleanReq misses
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system.cpu.l2cache.ReadSharedReq_misses::total 220595 # number of ReadSharedReq misses
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system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 286139000 # number of ReadReq miss cycles
|
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system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 303891500 # number of ReadReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1358307000 # number of UpgradeReq miss cycles
|
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system.cpu.l2cache.UpgradeReq_miss_latency::total 1358307000 # number of UpgradeReq miss cycles
|
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system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
|
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system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
|
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system.cpu.l2cache.ReadExReq_miss_latency::total 41540014500 # number of ReadExReq miss cycles
|
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system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9252321500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadCleanReq_miss_latency::total 9252321500 # number of ReadCleanReq miss cycles
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system.cpu.l2cache.ReadSharedReq_miss_latency::total 29380151500 # number of ReadSharedReq miss cycles
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system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 62462885000 # number of InvalidateReq miss cycles
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system.cpu.l2cache.InvalidateReq_miss_latency::total 62462885000 # number of InvalidateReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 286139000 # number of demand (read+write) miss cycles
|
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system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 303891500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.inst 9252321500 # number of demand (read+write) miss cycles
|
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system.cpu.l2cache.demand_miss_latency::cpu.data 70920166000 # number of demand (read+write) miss cycles
|
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system.cpu.l2cache.demand_miss_latency::total 80762518000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 286139000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 303891500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.inst 9252321500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::total 80762518000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 311814 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244191 # number of ReadReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadReq_accesses::total 556005 # number of ReadReq accesses(hits+misses)
|
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system.cpu.l2cache.WritebackDirty_accesses::writebacks 7254734 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 7254734 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 13400558 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 13400558 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 41537 # number of UpgradeReq accesses(hits+misses)
|
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system.cpu.l2cache.UpgradeReq_accesses::total 41537 # number of UpgradeReq accesses(hits+misses)
|
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system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 1906001 # number of ReadExReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadExReq_accesses::total 1906001 # number of ReadExReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13402665 # number of ReadCleanReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadCleanReq_accesses::total 13402665 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6133844 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 6133844 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1218438 # number of InvalidateReq accesses(hits+misses)
|
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system.cpu.l2cache.InvalidateReq_accesses::total 1218438 # number of InvalidateReq accesses(hits+misses)
|
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system.cpu.l2cache.demand_accesses::cpu.dtb.walker 311814 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.itb.walker 244191 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.inst 13402665 # number of demand (read+write) accesses
|
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system.cpu.l2cache.demand_accesses::cpu.data 8039845 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::total 21998515 # number of demand (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::cpu.dtb.walker 311814 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 244191 # number of overall (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::cpu.inst 13402665 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 8039845 # number of overall (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::total 21998515 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006693 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009063 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.007734 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787154 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787154 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.166390 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.166390 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005223 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005223 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.035964 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.035964 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.393538 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.393538 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006693 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009063 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005223 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.066884 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.027822 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006693 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009063 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005223 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.066884 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.027822 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137105.414471 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 137321.057388 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137216.395349 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41543.522143 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41543.522143 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130983.207732 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130983.207732 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132181.686358 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132181.686358 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133185.935765 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133185.935765 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 130266.161559 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 130266.161559 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137105.414471 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 137321.057388 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132181.686358 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 131886.832734 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 131957.998928 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137105.414471 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 137321.057388 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132181.686358 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 131886.832734 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 131957.998928 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 849613 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 849613 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2087 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2213 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4300 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32696 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 32696 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 317140 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 317140 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 69997 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 69997 # number of ReadCleanReq MSHR misses
|
|
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|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 220595 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 479502 # number of InvalidateReq MSHR misses
|
|
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|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2087 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2213 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 69997 # number of demand (read+write) MSHR misses
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|
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system.cpu.l2cache.demand_mshr_misses::total 612032 # number of demand (read+write) MSHR misses
|
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|
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|
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system.cpu.l2cache.overall_mshr_misses::cpu.data 537735 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_misses::total 612032 # number of overall MSHR misses
|
|
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|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable
|
|
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|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses
|
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 265269000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2311098000 # number of UpgradeReq MSHR miss cycles
|
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2311098000 # number of UpgradeReq MSHR miss cycles
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|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
|
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38368614500 # number of ReadExReq MSHR miss cycles
|
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system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38368614500 # number of ReadExReq MSHR miss cycles
|
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system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8552351500 # number of ReadCleanReq MSHR miss cycles
|
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system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8552351500 # number of ReadCleanReq MSHR miss cycles
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system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27174201500 # number of ReadSharedReq MSHR miss cycles
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system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27174201500 # number of ReadSharedReq MSHR miss cycles
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system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 57667865000 # number of InvalidateReq MSHR miss cycles
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|
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 57667865000 # number of InvalidateReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 265269000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281761500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8552351500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65542816000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 74642198000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 265269000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281761500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8552351500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65542816000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 74642198000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5778581000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10676305500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829959000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829959000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11608540000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16506264500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007734 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787154 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787154 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166390 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166390 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005223 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.035964 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.035964 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393538 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393538 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.027822 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006693 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009063 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005223 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066884 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127216.395349 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70684.426230 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70684.426230 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120983.207732 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120983.207732 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122181.686358 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122181.686358 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123185.935765 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123185.935765 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120266.161559 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120266.161559 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127105.414471 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127321.057388 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122181.686358 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121886.832734 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121957.998928 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171461.070560 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138965.539459 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.758514 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.758514 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172207.981012 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149330.659972 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 45838189 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 23177247 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 2695 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2695 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 972617 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 20509993 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 8211016 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 13400558 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 2162503 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 41540 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 41542 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1906001 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1906001 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 13402665 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6142720 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 1325102 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateResp 1218438 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40292138 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27992932 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598317 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853478 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 69736865 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715578772 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 979098990 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1953528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2494512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 2699125802 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 1572119 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 24940276 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.019256 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.137423 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 24460029 98.07% 98.07% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 480247 1.93% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 24940276 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 43858094500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1606889 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 20147122500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 12740327469 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 354126000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 541664000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 40324 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40324 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 42148000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 11500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 25746500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 38603000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 565448922 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115484 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.446943 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 6.935476 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039884 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039884 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8879 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8839 # number of overall misses
|
|
system.iocache.overall_misses::total 8879 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1627645138 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1632715138 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 13865007784 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 13865007784 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1627645138 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1633066138 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1627645138 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1633066138 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 184143.583890 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 183947.176431 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129987.697667 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 129987.697667 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 183924.556594 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 184143.583890 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 183924.556594 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 33671 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.631293 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106630 # number of writebacks
|
|
system.iocache.writebacks::total 106630 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185695138 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1188915138 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8531807784 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 8531807784 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1185695138 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1189116138 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1185695138 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1189116138 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134143.583890 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 133947.176431 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79987.697667 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79987.697667 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 134143.583890 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 133924.556594 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 76827 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 380595 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 956243 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 155849 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 33272 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 33274 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 796069 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 796069 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 303768 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3338566 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3468258 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341194 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 341194 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 3809452 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124348000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124517826 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226112 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7226112 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 131743938 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3260 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2465217 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 2465217 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2465217 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 106924000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5793500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 6289776705 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 6042674003 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 227496341 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
|
|
|
---------- End Simulation Statistics ----------
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