1074 lines
123 KiB
Plaintext
1074 lines
123 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.403830 # Number of seconds simulated
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sim_ticks 403830091000 # Number of ticks simulated
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final_tick 403830091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 95719 # Simulator instruction rate (inst/s)
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host_op_rate 176996 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 46747318 # Simulator tick rate (ticks/s)
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host_mem_usage 431916 # Number of bytes of host memory used
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host_seconds 8638.57 # Real time elapsed on the host
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sim_insts 826877109 # Number of instructions simulated
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sim_ops 1528988701 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 163776 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 24545280 # Number of bytes read from this memory
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system.physmem.bytes_read::total 24709056 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 163776 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 163776 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2559 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 383520 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 386079 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 405557 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 60781206 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 61186763 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 405557 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 405557 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 46778168 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 46778168 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 46778168 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 405557 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 60781206 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 107964931 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 386079 # Number of read requests accepted
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system.physmem.writeReqs 295163 # Number of write requests accepted
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system.physmem.readBursts 386079 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 24689408 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18889088 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 24709056 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 251728 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 24087 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26440 # Per bank write bursts
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system.physmem.perBankRdBursts::2 24835 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24498 # Per bank write bursts
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system.physmem.perBankRdBursts::4 23219 # Per bank write bursts
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system.physmem.perBankRdBursts::5 23721 # Per bank write bursts
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system.physmem.perBankRdBursts::6 24501 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24288 # Per bank write bursts
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system.physmem.perBankRdBursts::8 23633 # Per bank write bursts
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system.physmem.perBankRdBursts::9 23532 # Per bank write bursts
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system.physmem.perBankRdBursts::10 24814 # Per bank write bursts
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system.physmem.perBankRdBursts::11 23996 # Per bank write bursts
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system.physmem.perBankRdBursts::12 23302 # Per bank write bursts
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system.physmem.perBankRdBursts::13 22925 # Per bank write bursts
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system.physmem.perBankRdBursts::14 24085 # Per bank write bursts
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system.physmem.perBankRdBursts::15 23896 # Per bank write bursts
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system.physmem.perBankWrBursts::0 18615 # Per bank write bursts
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system.physmem.perBankWrBursts::1 19935 # Per bank write bursts
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system.physmem.perBankWrBursts::2 19196 # Per bank write bursts
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system.physmem.perBankWrBursts::3 19026 # Per bank write bursts
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system.physmem.perBankWrBursts::4 18118 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18514 # Per bank write bursts
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system.physmem.perBankWrBursts::6 19142 # Per bank write bursts
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system.physmem.perBankWrBursts::7 19086 # Per bank write bursts
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system.physmem.perBankWrBursts::8 18651 # Per bank write bursts
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system.physmem.perBankWrBursts::9 17953 # Per bank write bursts
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system.physmem.perBankWrBursts::10 18925 # Per bank write bursts
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system.physmem.perBankWrBursts::11 17775 # Per bank write bursts
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system.physmem.perBankWrBursts::12 17401 # Per bank write bursts
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system.physmem.perBankWrBursts::13 17016 # Per bank write bursts
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system.physmem.perBankWrBursts::14 17907 # Per bank write bursts
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system.physmem.perBankWrBursts::15 17882 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 403830049500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 386079 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 295163 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 380933 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 4500 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 6196 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 6591 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 16916 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 17527 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 17623 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17664 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17651 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17699 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 17709 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 17701 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 17763 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 17953 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17614 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17545 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 146827 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 296.793805 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 175.429172 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 322.898216 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 54192 36.91% 36.91% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 39812 27.11% 64.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 13750 9.36% 73.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7660 5.22% 78.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 5440 3.71% 82.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 4000 2.72% 85.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 3009 2.05% 87.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 2793 1.90% 88.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 16171 11.01% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 146827 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 17508 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 22.033813 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 216.830406 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 17508 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 17508 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.857551 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.779124 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 2.831180 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-19 17335 99.01% 99.01% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-23 121 0.69% 99.70% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-31 8 0.05% 99.89% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 17508 # Writes before turning the bus around for reads
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system.physmem.totQLat 4276128000 # Total ticks spent queuing
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system.physmem.totMemAccLat 11509353000 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1928860000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 11084.60 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29834.60 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 61.14 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 46.77 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 61.19 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 46.78 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.84 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing
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system.physmem.readRowHits 318168 # Number of row buffer hits during reads
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system.physmem.writeRowHits 215906 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 592785.02 # Average gap between requests
|
|
system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 567876960 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 309853500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1525477200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 982432800 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 62051510430 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 187864648500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 279677755230 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 692.569390 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 311979208000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 13484640000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 78362495750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 541779840 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 295614000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1483021800 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 929672640 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 60320910060 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 189382719000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 279329673180 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 691.707431 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 314516116250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 13484640000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 75825587500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 219264229 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 219264229 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 8531047 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 124002696 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 121802201 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 98.225446 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 27063113 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1406921 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
|
system.cpu.workload.num_syscalls 551 # Number of system calls
|
|
system.cpu.numCycles 807660183 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 175911242 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 1208663462 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 219264229 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 148865314 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 621862787 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 17775835 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 233 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 94904 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 745978 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.PendingQuiesceStallCycles 1264 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 170762091 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 2319100 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 807504342 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.785127 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 417532473 51.71% 51.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 32497368 4.02% 55.73% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 31891068 3.95% 59.68% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 32657877 4.04% 63.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 26554759 3.29% 67.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 26902865 3.33% 70.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 35168137 4.36% 74.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 31391832 3.89% 78.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 172907963 21.41% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 807504342 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.271481 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.496500 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 120449956 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 370877919 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 225251519 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 82037031 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 8887917 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 2132109647 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 8887917 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 152555499 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 150771591 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 44475 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 271462113 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 223782747 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2088438662 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 138448 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 138151621 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 24868058 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 50731794 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 2190645258 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 5278038161 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 3357041251 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 59967 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 576604404 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 3331 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 3057 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 422478077 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 507119798 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 200816388 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 229077730 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 68200212 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2023068034 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 22911 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1788999576 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 413303 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 494102244 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 832764755 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 22359 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 807504342 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.215467 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.071001 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 238908265 29.59% 29.59% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 123628552 15.31% 44.90% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 118817632 14.71% 59.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 107769877 13.35% 72.96% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 89573603 11.09% 84.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 60241832 7.46% 91.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 42310466 5.24% 96.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 18973159 2.35% 99.10% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 7280956 0.90% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 807504342 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 11498712 42.77% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.77% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 12295029 45.73% 88.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 3093590 11.51% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2718967 0.15% 0.15% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1183065523 66.13% 66.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 369413 0.02% 66.30% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 3881231 0.22% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 133 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 60 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 428545273 23.95% 90.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 170418596 9.53% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1788999576 # Type of FU issued
|
|
system.cpu.iq.rate 2.215040 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 26887331 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.015029 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 4412774566 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2517442986 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1762358918 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 29562 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 69250 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 5611 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1813154984 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 12956 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 186087729 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 123020037 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 213128 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 372787 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 51656202 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 22930 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 1078 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 8887917 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 97798502 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 6162253 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2023090945 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 375323 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 507122194 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 200816388 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 7129 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1832886 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 3426694 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 372787 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 4845812 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 4140641 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 8986453 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1769991187 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 423150453 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 19008389 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 590375275 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 168976940 # Number of branches executed
|
|
system.cpu.iew.exec_stores 167224822 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.191505 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1766866321 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1762364529 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1339720871 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2049946578 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.182062 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.653539 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 494164798 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 8615583 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 740300612 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.065362 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.575682 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 276280439 37.32% 37.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 172026383 23.24% 60.56% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 56011691 7.57% 68.12% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 86227626 11.65% 79.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 25892196 3.50% 83.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 26512378 3.58% 86.85% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 9839162 1.33% 88.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 8995484 1.22% 89.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 78515253 10.61% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 740300612 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 533262343 # Number of memory references committed
|
|
system.cpu.commit.loads 384102157 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 149758583 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 78515253 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 2684938858 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 4113685431 # The number of ROB writes
|
|
system.cpu.timesIdled 1962 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 155841 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 826877109 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.976760 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.976760 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.023793 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.023793 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2722687854 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1435809850 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 5827 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 561 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 596681162 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 405470892 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 971641846 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2530997 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4087.815869 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 381868965 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2535093 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 150.633119 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.815869 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 772828805 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 772828805 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 233213748 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 233213748 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 148173817 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 148173817 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 381387565 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 381387565 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 381387565 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 381387565 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2772906 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2772906 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 986385 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 986385 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3759291 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3759291 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3759291 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3759291 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 59174415500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 59174415500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 31292251995 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 31292251995 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 90466667495 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 90466667495 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 90466667495 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 90466667495 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 235986654 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 235986654 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 385146856 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 385146856 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 385146856 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 385146856 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009761 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009761 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009761 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009761 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 24064.821663 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 24064.821663 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 9788 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.348615 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2330532 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2330532 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007920 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1007920 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19403 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 19403 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1027323 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1027323 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1027323 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1027323 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764986 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1764986 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966982 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 966982 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2731968 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2731968 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2731968 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2731968 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33558631000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33558631000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30070164497 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 30070164497 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63628795497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 63628795497 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63628795497 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 63628795497 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007479 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007479 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006483 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006483 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 6653 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1037.717066 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 170551460 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 8264 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 20637.882381 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1037.717066 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.506698 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.506698 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 321 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1160 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 341729418 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 341729418 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 170554639 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 170554639 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 170554639 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 170554639 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 170554639 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 170554639 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 207451 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 207451 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 207451 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 207451 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 207451 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 207451 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1211820000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1211820000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1211820000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1211820000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1211820000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1211820000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 170762090 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 170762090 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 170762090 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 170762090 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 170762090 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 170762090 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001215 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001215 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001215 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.001215 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001215 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.001215 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5841.475818 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 5841.475818 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 5841.475818 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 5841.475818 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 674 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 74.888889 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 6653 # number of writebacks
|
|
system.cpu.icache.writebacks::total 6653 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2211 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2211 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2211 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2211 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2211 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2211 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205240 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 205240 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 205240 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 205240 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 205240 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 205240 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 926829000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 926829000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 926829000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 926829000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 926829000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 926829000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4515.830248 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4515.830248 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 355338 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 29622.648539 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3892669 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 387670 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 10.041192 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 189329679500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 21024.249099 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.226961 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 8412.172479 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.641609 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005683 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.256719 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.904011 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32332 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13400 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18619 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986694 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 43294553 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 43294553 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 2330532 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 2330532 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 6263 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 6263 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 1839 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 1839 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 563568 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 563568 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5677 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 5677 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587956 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 1587956 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5677 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2151524 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2157201 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5677 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2151524 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2157201 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 195036 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 195036 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 206929 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 206929 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2561 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 2561 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176640 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 176640 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2561 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 383569 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 386130 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2561 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 383569 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 386130 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13989000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 13989000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16413605500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 16413605500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 209990000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 209990000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14188998500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 14188998500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 209990000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 30602604000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 30812594000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 209990000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 30602604000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 30812594000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330532 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 2330532 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 6263 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 6263 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 196875 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 196875 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 770497 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 770497 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8238 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 8238 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764596 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 1764596 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 8238 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2535093 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2543331 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 8238 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2535093 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2543331 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990659 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990659 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268566 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.268566 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.310876 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.310876 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100102 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100102 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.310876 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.151304 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.151821 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.310876 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.151304 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.151821 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 71.725220 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 71.725220 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79319.986565 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79319.986565 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81995.314330 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81995.314330 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80327.210711 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80327.210711 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81995.314330 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79783.830289 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79798.497915 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81995.314330 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79783.830289 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79798.497915 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 295163 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195036 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 195036 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206929 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 206929 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2560 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2560 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176640 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176640 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2560 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 383569 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 386129 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2560 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 383569 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 386129 # number of overall MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4301153024 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 4301153024 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14344315500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14344315500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184333500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184333500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12422598500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12422598500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184333500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26766914000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26951247500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184333500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26766914000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26951247500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990659 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990659 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268566 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268566 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310755 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100102 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100102 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.151820 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.151820 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 5474858 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731062 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212394 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 3599 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3599 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 1969834 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 2625695 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 6263 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 249937 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 196875 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 196875 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 770497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 770497 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 205240 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764596 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219739 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7984230 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8203969 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 927936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311400000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 312327936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 552340 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3292546 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.124310 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.329935 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 2883249 87.57% 87.57% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 409297 12.43% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3292546 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5102581952 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 307865483 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3901080066 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 179198 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 56643 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 195085 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 195085 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 206880 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 206880 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 179199 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514133 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514133 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1514133 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43599424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43599424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 43599424 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 932970 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 932970 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 932970 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 2244779968 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2432276830 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|