771 lines
88 KiB
Plaintext
771 lines
88 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.560955 # Number of seconds simulated
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sim_ticks 560955232000 # Number of ticks simulated
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final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 340981 # Simulator instruction rate (inst/s)
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host_op_rate 340981 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 205940379 # Simulator tick rate (ticks/s)
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host_mem_usage 308844 # Number of bytes of host memory used
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host_seconds 2723.87 # Real time elapsed on the host
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sim_insts 928789150 # Number of instructions simulated
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sim_ops 928789150 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 184896 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 18519872 # Number of bytes read from this memory
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system.physmem.bytes_read::total 18704768 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 184896 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 184896 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2889 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 289373 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 292262 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 329609 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 33014884 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 33344493 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 329609 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 329609 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 7607937 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 7607937 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 7607937 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 329609 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 33014884 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 40952430 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 292262 # Number of read requests accepted
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system.physmem.writeReqs 66683 # Number of write requests accepted
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system.physmem.readBursts 292262 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 18684608 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 18704768 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 18033 # Per bank write bursts
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system.physmem.perBankRdBursts::1 18359 # Per bank write bursts
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system.physmem.perBankRdBursts::2 18394 # Per bank write bursts
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system.physmem.perBankRdBursts::3 18332 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18249 # Per bank write bursts
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system.physmem.perBankRdBursts::5 18255 # Per bank write bursts
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system.physmem.perBankRdBursts::6 18314 # Per bank write bursts
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system.physmem.perBankRdBursts::7 18296 # Per bank write bursts
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system.physmem.perBankRdBursts::8 18227 # Per bank write bursts
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system.physmem.perBankRdBursts::9 18236 # Per bank write bursts
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system.physmem.perBankRdBursts::10 18229 # Per bank write bursts
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system.physmem.perBankRdBursts::11 18376 # Per bank write bursts
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system.physmem.perBankRdBursts::12 18263 # Per bank write bursts
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system.physmem.perBankRdBursts::13 18132 # Per bank write bursts
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system.physmem.perBankRdBursts::14 18061 # Per bank write bursts
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system.physmem.perBankRdBursts::15 18191 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4160 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4142 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4099 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4192 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4100 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 560955208000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 292262 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66683 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 291448 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 471 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 933 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 934 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4049 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 4051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4052 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4050 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 104067 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 220.533003 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 142.789866 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 268.043159 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 38344 36.85% 36.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 44004 42.28% 79.13% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 8921 8.57% 87.70% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 721 0.69% 88.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1145 1.10% 90.81% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 668 0.64% 91.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 598 0.57% 92.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8294 7.97% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 104067 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4050 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 71.768889 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 34.564435 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 763.185509 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4041 99.78% 99.78% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4050 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4050 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.461235 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.440549 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.842853 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3116 76.94% 76.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1 0.02% 76.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 932 23.01% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4050 # Writes before turning the bus around for reads
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system.physmem.totQLat 2934449500 # Total ticks spent queuing
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system.physmem.totMemAccLat 8408455750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1459735000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10051.31 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28801.31 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.32 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing
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system.physmem.readRowHits 202530 # Number of row buffer hits during reads
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system.physmem.writeRowHits 52011 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes
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system.physmem.avgGap 1562788.75 # Average gap between requests
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system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 1140391200 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 109486358955 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 240531047250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 388619465820 # Total energy per rank (pJ)
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system.physmem_0.averagePower 692.784540 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 399461576500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 18731440000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 142759852250 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 394276680 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 215131125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1136522400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 109506441195 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 240513431250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 388620069450 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 692.785616 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 399429681750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 18731440000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 142792236250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 125747709 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 81143389 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 12156447 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 103980471 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 83512685 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 80.315740 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 18691016 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 237537764 # DTB read hits
|
|
system.cpu.dtb.read_misses 198464 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 237736228 # DTB read accesses
|
|
system.cpu.dtb.write_hits 98304946 # DTB write hits
|
|
system.cpu.dtb.write_misses 7177 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 98312123 # DTB write accesses
|
|
system.cpu.dtb.data_hits 335842710 # DTB hits
|
|
system.cpu.dtb.data_misses 205641 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 336048351 # DTB accesses
|
|
system.cpu.itb.fetch_hits 316984906 # ITB hits
|
|
system.cpu.itb.fetch_misses 120 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 316985026 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 37 # Number of system calls
|
|
system.cpu.numCycles 1121910464 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 928789150 # Number of instructions committed
|
|
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 30861351 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.207928 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.827864 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 1059707465 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 62202999 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 776530 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4092.728000 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 322866540 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 413.599521 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.728000 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 648211872 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 648211872 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 224702494 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 224702494 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 98164046 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 98164046 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 322866540 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 322866540 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 322866540 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 322866540 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 137154 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 137154 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 849083 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 849083 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 849083 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 849083 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24904735500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 24904735500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9954481000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9954481000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 34859216500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 34859216500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 34859216500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 34859216500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 225414423 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 225414423 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 323715623 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 323715623 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 323715623 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 323715623 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 41055.134186 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 41055.134186 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 88497 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 88497 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68143 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 68457 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 68457 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 68457 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 68457 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24185998000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 24185998000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4992658500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4992658500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29178656500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 29178656500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29178656500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 29178656500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 10567 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1685.376446 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 316972597 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 12308 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 25753.379672 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376446 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 633982120 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 633982120 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 316972597 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 316972597 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 316972597 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 316972597 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 316972597 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 316972597 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 12309 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 12309 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 12309 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 12309 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 12309 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 12309 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 349738000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 349738000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 349738000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 349738000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 349738000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 349738000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 316984906 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 316984906 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 316984906 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 316984906 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 316984906 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 316984906 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 28413.193598 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 28413.193598 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 10567 # number of writebacks
|
|
system.cpu.icache.writebacks::total 10567 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12309 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 12309 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 12309 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 12309 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 12309 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 12309 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337430000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 337430000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337430000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 337430000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337430000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 337430000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 259935 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 32594.451091 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1218218 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 292671 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.162414 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 2600.597713 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 77.726752 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 29916.126627 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.079364 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002372 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.912968 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994704 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2660 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29372 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 13001938 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 13001938 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 88497 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 88497 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9419 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 9419 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488887 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 488887 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 9419 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 491253 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 500672 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 9419 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 491253 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 500672 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2890 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 2890 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222728 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 222728 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2890 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 289373 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 292263 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2890 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 289373 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 292263 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4864271500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4864271500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 220068500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 220068500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17985247000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 17985247000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 220068500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 22849518500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 23069587000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 220068500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 22849518500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 23069587000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 88497 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 88497 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 10567 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 10567 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12309 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 12309 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711615 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 711615 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 12309 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 780626 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 792935 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 12309 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 780626 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 792935 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.234788 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.234788 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312989 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312989 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.234788 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.370694 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.368584 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.234788 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.370694 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.368584 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.793533 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.793533 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76148.269896 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76148.269896 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80749.824899 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80749.824899 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76148.269896 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78962.164749 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 78934.339961 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76148.269896 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78962.164749 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 78934.339961 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66683 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2890 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2890 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222728 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222728 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2890 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 289373 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 292263 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2890 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 289373 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 292263 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4197821500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4197821500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 191178500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 191178500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15757967000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15757967000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 191178500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19955788500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 20146967000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 191178500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19955788500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 20146967000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.234788 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312989 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312989 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.368584 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.368584 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 1580032 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 2079 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2079 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 723923 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 155180 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 881285 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 12309 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35184 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 2372966 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 57087872 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 259935 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 1052870 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.001975 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.044393 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 1050791 99.80% 99.80% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 2079 0.20% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 1052870 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 889080000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 18462000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 225617 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 191173 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 225617 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842380 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 842380 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22972480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 550118 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 550118 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 550118 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 918693000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 1556459000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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