768 lines
88 KiB
Plaintext
768 lines
88 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.059474 # Number of seconds simulated
|
|
sim_ticks 59473862000 # Number of ticks simulated
|
|
final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 342067 # Simulator instruction rate (inst/s)
|
|
host_op_rate 342067 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 230037089 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 307480 # Number of bytes of host memory used
|
|
host_seconds 258.54 # Real time elapsed on the host
|
|
sim_insts 88438073 # Number of instructions simulated
|
|
sim_ops 88438073 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.inst 432448 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 10149376 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 10581824 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 432448 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 432448 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 7325760 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7325760 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.inst 6757 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 158584 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 165341 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 114465 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 114465 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 7271228 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 170652715 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 177923942 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 7271228 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 7271228 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 123176127 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 123176127 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 123176127 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 7271228 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 170652715 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 301100070 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 165341 # Number of read requests accepted
|
|
system.physmem.writeReqs 114465 # Number of write requests accepted
|
|
system.physmem.readBursts 165341 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 114465 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 10581376 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 7323904 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 10581824 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 10312 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 10359 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 10206 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 10057 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 10348 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 10339 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 9776 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 10207 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 10534 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 10607 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 10498 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 10228 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 10274 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 10561 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 10464 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 10564 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 7163 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 7274 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 7296 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 7002 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 7127 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 7187 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 6833 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 7099 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 7225 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 7000 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 7115 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 7034 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 6992 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 7299 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 7308 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 7482 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 59473838000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 165341 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 114465 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 163748 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 1560 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 772 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 786 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 7009 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 7043 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 7065 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 7061 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 7072 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 7070 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 7119 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 7112 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 7227 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 7132 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 7341 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 7041 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 54714 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 327.237051 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 194.297949 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 330.344141 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 19597 35.82% 35.82% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 11811 21.59% 57.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 5572 10.18% 67.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3684 6.73% 74.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2893 5.29% 79.61% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 2049 3.74% 83.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1621 2.96% 86.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 1502 2.75% 89.06% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 5985 10.94% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 54714 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 7041 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 23.479761 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 336.363256 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-1023 7038 99.96% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 7041 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 7041 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 16.252805 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 16.237164 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 0.745060 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 6251 88.78% 88.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 16 0.23% 89.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 606 8.61% 97.61% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 134 1.90% 99.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 28 0.40% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 4 0.06% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 7041 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1980163000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 5080175500 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 826670000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 11976.74 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 30726.74 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 177.92 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 123.14 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 177.92 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 123.18 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.35 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 143867 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 81182 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 87.02 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 212553.83 # Average gap between requests
|
|
system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 199175760 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 108677250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 636448800 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 369204480 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 12421725570 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 24786732000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 42406345140 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 713.051581 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 41087166750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1985880000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 16398707250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 214341120 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 116952000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 652938000 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 372237120 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 13062187260 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 24224923500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 42527960280 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 715.096508 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 40147172500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1985880000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 17338598750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 14666171 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 9489023 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 386095 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9897790 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 6385525 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 64.514654 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1708105 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 84877 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 20569903 # DTB read hits
|
|
system.cpu.dtb.read_misses 97320 # DTB read misses
|
|
system.cpu.dtb.read_acv 10 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 20667223 # DTB read accesses
|
|
system.cpu.dtb.write_hits 14665328 # DTB write hits
|
|
system.cpu.dtb.write_misses 9407 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 14674735 # DTB write accesses
|
|
system.cpu.dtb.data_hits 35235231 # DTB hits
|
|
system.cpu.dtb.data_misses 106727 # DTB misses
|
|
system.cpu.dtb.data_acv 10 # DTB access violations
|
|
system.cpu.dtb.data_accesses 35341958 # DTB accesses
|
|
system.cpu.itb.fetch_hits 25606544 # ITB hits
|
|
system.cpu.itb.fetch_misses 5228 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 25611772 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 4583 # Number of system calls
|
|
system.cpu.numCycles 118947724 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 88438073 # Number of instructions committed
|
|
system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 1106117 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.344983 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.743504 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 91473408 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 27474316 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 200766 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4070.683377 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 34616213 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 168.973324 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.683377 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993819 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993819 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3361 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 70176360 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 70176360 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20282952 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20282952 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 34616213 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 34616213 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 34616213 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 34616213 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 369536 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 369536 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 369536 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 369536 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4768019500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 4768019500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21708920500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 21708920500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 26476940000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 26476940000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 26476940000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 26476940000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 20372372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 20372372 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 34985749 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 34985749 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 34985749 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 34985749 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 71649.149203 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 71649.149203 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 168423 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 168423 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 28115 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136559 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 136559 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 164674 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 164674 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 164674 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 164674 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61305 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 61305 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 204862 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2680071500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2680071500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970928000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970928000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13650999500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 13650999500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13650999500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 13650999500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 152856 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1932.301021 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 25451639 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 154904 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 164.305886 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 42254913500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1932.301021 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.943506 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.943506 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 1041 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 51367992 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 51367992 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25451639 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25451639 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25451639 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25451639 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25451639 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25451639 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 154905 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 154905 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 154905 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 154905 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 154905 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 154905 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 2479923000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 2479923000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 2479923000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 2479923000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 2479923000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 2479923000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25606544 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25606544 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25606544 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25606544 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25606544 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25606544 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 16009.315387 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 16009.315387 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 152856 # number of writebacks
|
|
system.cpu.icache.writebacks::total 152856 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154905 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 154905 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 154905 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 154905 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 154905 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 154905 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325019000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 2325019000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325019000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 2325019000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325019000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 2325019000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15009.321842 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 133370 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 30430.165732 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 403981 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 165480 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 2.441268 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 26353.973497 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2093.222263 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 1982.969972 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.804259 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.063880 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.060515 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.928655 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1089 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11867 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18864 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 125 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 6016150 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 6016150 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 168423 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 168423 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 152856 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 152856 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12675 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 12675 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 148147 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 148147 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33603 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 33603 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 148147 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 46278 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 194425 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 148147 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 46278 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 194425 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130883 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130883 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6758 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 6758 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27701 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 27701 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 6758 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 158584 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 165342 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 6758 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 158584 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 165342 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10622451000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10622451000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 536913000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 536913000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2234805000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 2234805000 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 536913000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 12857256000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 13394169000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 536913000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 12857256000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 13394169000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 168423 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 168423 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 152856 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 152856 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143558 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143558 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 154905 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 154905 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61304 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 61304 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 154905 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 204862 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 359767 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 154905 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 204862 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 359767 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911708 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911708 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043627 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043627 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.451863 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.451863 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043627 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.774102 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.459581 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043627 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.774102 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.459581 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81159.898535 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81159.898535 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79448.505475 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79448.505475 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80675.968377 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80675.968377 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79448.505475 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81075.366998 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 81008.872519 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79448.505475 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81075.366998 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 81008.872519 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 114465 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 114465 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6758 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6758 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27701 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27701 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 6758 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 158584 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 165342 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 6758 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 158584 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 165342 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9313621000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9313621000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 469343000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 469343000 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1957795000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1957795000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 469343000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11271416000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 11740759000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 469343000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11271416000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 11740759000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911708 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911708 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043627 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451863 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451863 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.459581 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.459581 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 713389 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 353622 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 4036 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4036 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 216208 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 282888 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 152856 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 51248 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 154905 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462665 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1073155 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19696640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 43586880 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 133370 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 493137 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.008184 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.090096 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 489101 99.18% 99.18% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 4036 0.82% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 493137 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 677973500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 232357497 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 307299487 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 34458 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 114465 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 14983 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 130883 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 130883 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 34458 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460130 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 460130 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17907584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 17907584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 294789 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 294789 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 294789 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 822943500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 872924250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|