1100 lines
126 KiB
Plaintext
1100 lines
126 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.669525 # Number of seconds simulated
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sim_ticks 669525393000 # Number of ticks simulated
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final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 166227 # Simulator instruction rate (inst/s)
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host_op_rate 166227 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 64107392 # Simulator tick rate (ticks/s)
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host_mem_usage 299384 # Number of bytes of host memory used
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host_seconds 10443.81 # Real time elapsed on the host
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sim_insts 1736043781 # Number of instructions simulated
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sim_ops 1736043781 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125490432 # Number of bytes read from this memory
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system.physmem.bytes_read::total 125551424 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 65555904 # Number of bytes written to this memory
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system.physmem.bytes_written::total 65555904 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1960788 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1961741 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1024311 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1024311 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 91097 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 187431923 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 187523021 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 91097 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 91097 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 97913992 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 97913992 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 97913992 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 91097 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 187431923 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 285437013 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1961741 # Number of read requests accepted
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system.physmem.writeReqs 1024311 # Number of write requests accepted
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system.physmem.readBursts 1961741 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1024311 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 125468352 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 83072 # Total number of bytes read from write queue
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system.physmem.bytesWritten 65554688 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 125551424 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 118677 # Per bank write bursts
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system.physmem.perBankRdBursts::1 113900 # Per bank write bursts
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system.physmem.perBankRdBursts::2 116118 # Per bank write bursts
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system.physmem.perBankRdBursts::3 117645 # Per bank write bursts
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system.physmem.perBankRdBursts::4 117762 # Per bank write bursts
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system.physmem.perBankRdBursts::5 117513 # Per bank write bursts
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system.physmem.perBankRdBursts::6 119856 # Per bank write bursts
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system.physmem.perBankRdBursts::7 124646 # Per bank write bursts
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system.physmem.perBankRdBursts::8 127338 # Per bank write bursts
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system.physmem.perBankRdBursts::9 130111 # Per bank write bursts
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system.physmem.perBankRdBursts::10 128791 # Per bank write bursts
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system.physmem.perBankRdBursts::11 130502 # Per bank write bursts
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system.physmem.perBankRdBursts::12 126296 # Per bank write bursts
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system.physmem.perBankRdBursts::13 125424 # Per bank write bursts
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system.physmem.perBankRdBursts::14 122633 # Per bank write bursts
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system.physmem.perBankRdBursts::15 123231 # Per bank write bursts
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system.physmem.perBankWrBursts::0 61509 # Per bank write bursts
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system.physmem.perBankWrBursts::1 61765 # Per bank write bursts
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system.physmem.perBankWrBursts::2 60825 # Per bank write bursts
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system.physmem.perBankWrBursts::3 61513 # Per bank write bursts
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system.physmem.perBankWrBursts::4 61969 # Per bank write bursts
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system.physmem.perBankWrBursts::5 63433 # Per bank write bursts
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system.physmem.perBankWrBursts::6 64481 # Per bank write bursts
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system.physmem.perBankWrBursts::7 65997 # Per bank write bursts
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system.physmem.perBankWrBursts::8 65770 # Per bank write bursts
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system.physmem.perBankWrBursts::9 66158 # Per bank write bursts
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system.physmem.perBankWrBursts::10 65809 # Per bank write bursts
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system.physmem.perBankWrBursts::11 66082 # Per bank write bursts
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system.physmem.perBankWrBursts::12 64703 # Per bank write bursts
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system.physmem.perBankWrBursts::13 64664 # Per bank write bursts
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system.physmem.perBankWrBursts::14 65021 # Per bank write bursts
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system.physmem.perBankWrBursts::15 64593 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 669525297500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1961741 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1024311 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1618506 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 241044 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 69880 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 30998 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 26356 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 27917 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 49392 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 56811 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 59370 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 60627 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 60983 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 61171 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 61281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 61428 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 61383 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 61603 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 62346 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 63632 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 65011 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 62797 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 61721 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 60222 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 183 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1769975 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 107.923423 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 82.935475 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 137.553027 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1375598 77.72% 77.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 270762 15.30% 93.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 53515 3.02% 96.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 21283 1.20% 97.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 12968 0.73% 97.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6460 0.36% 98.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 4828 0.27% 98.61% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3885 0.22% 98.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 20676 1.17% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1769975 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 60095 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 32.621932 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 151.728866 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-511 59931 99.73% 99.73% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::512-1023 120 0.20% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-1535 12 0.02% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::9216-9727 2 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 60095 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 60095 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.044546 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.002519 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.231700 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 31758 52.85% 52.85% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1379 2.29% 55.14% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 21272 35.40% 90.54% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 4591 7.64% 98.18% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 816 1.36% 99.54% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 185 0.31% 99.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 43 0.07% 99.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 20 0.03% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 5 0.01% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 60095 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 40550197000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 77308503250 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 9802215000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 20684.20 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 39434.20 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 187.40 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 97.91 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 187.52 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 97.91 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.23 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 792754 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 422001 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 41.20 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 224217.56 # Average gap between requests
|
|
system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 6484552200 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 3538198125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 7379689200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3249668160 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 304192019700 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 134879490000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 503453674665 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 751.957257 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 222404009750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 22356880000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 424763715750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 6896443680 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 3762940500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 7911594600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3387744000 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 311181502770 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 128748364500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 505618647330 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 755.190855 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 212167441250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 22356880000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 435000017500 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 409350195 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 318164532 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15963584 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 282308187 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 278578841 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 98.678981 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 26172152 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 644938332 # DTB read hits
|
|
system.cpu.dtb.read_misses 12159455 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 657097787 # DTB read accesses
|
|
system.cpu.dtb.write_hits 218091822 # DTB write hits
|
|
system.cpu.dtb.write_misses 7511788 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 225603610 # DTB write accesses
|
|
system.cpu.dtb.data_hits 863030154 # DTB hits
|
|
system.cpu.dtb.data_misses 19671243 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 882701397 # DTB accesses
|
|
system.cpu.itb.fetch_hits 420624983 # ITB hits
|
|
system.cpu.itb.fetch_misses 37 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 420625020 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
system.cpu.numCycles 1339050787 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 431760433 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 3409990757 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 409350195 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 304750993 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 884524854 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 45382362 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 420624983 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 8290664 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1338978167 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.546711 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.150697 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 713970324 53.32% 53.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 47658259 3.56% 56.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 24222568 1.81% 58.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 45103345 3.37% 62.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 142790906 10.66% 72.72% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 65943786 4.92% 77.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 43594409 3.26% 80.90% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 29428241 2.20% 83.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 226266329 16.90% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1338978167 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.305702 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.546573 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 353776569 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 403484138 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 524228681 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 34798314 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 22690465 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 62024721 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3256106209 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2093 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 22690465 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 372012141 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 212467548 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 7342 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 537162613 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 194638058 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3173768927 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1816422 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 20455726 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 148599653 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 30860374 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 2371827952 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 4117690277 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 4117553850 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 136426 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 995624989 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 146 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 99592668 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 717246268 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 272455740 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 90411000 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 58626283 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2884178650 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2620049271 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1544769 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 1148134993 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 502709027 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1338978167 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.956753 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.148253 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 535496202 39.99% 39.99% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 169647302 12.67% 52.66% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 157966093 11.80% 64.46% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 149142376 11.14% 75.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 126023638 9.41% 85.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 84181895 6.29% 91.30% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 68010869 5.08% 96.38% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 34104922 2.55% 98.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 14404870 1.08% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1338978167 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 13158801 35.84% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 18966749 51.66% 87.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4591786 12.51% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1716928227 65.53% 65.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 896664 0.03% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 671542182 25.63% 91.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 230681845 8.80% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2620049271 # Type of FU issued
|
|
system.cpu.iq.rate 1.956647 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36717336 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.014014 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6615397697 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 4031207578 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2518612422 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 1941117 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1249905 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 887144 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2655798760 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 967847 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 69398293 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 272650605 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 374228 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 146038 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 111727238 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 239 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 6310160 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 22690465 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 149836338 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 21229362 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3035183152 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6595413 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 717246268 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 272455740 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 801803 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 20684202 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 146038 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 10633994 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8701055 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19335049 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2574897906 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 657097795 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 45151365 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 151004377 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 882701473 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 315482828 # Number of branches executed
|
|
system.cpu.iew.exec_stores 225603678 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.922928 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2549323154 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2519499566 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1487497634 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1918379503 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.881556 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.775393 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 998640819 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15962868 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1200994355 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.515228 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.548533 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 712309125 59.31% 59.31% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 159609736 13.29% 72.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 79494019 6.62% 79.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 52028691 4.33% 83.55% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 28473987 2.37% 85.92% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 19488340 1.62% 87.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 19957354 1.66% 89.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 23050317 1.92% 91.13% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106582786 8.87% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1200994355 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 605324165 # Number of memory references committed
|
|
system.cpu.commit.loads 444595663 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 214632552 # Number of branches committed
|
|
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 106582786 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 3827053314 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5774960362 # The number of ROB writes
|
|
system.cpu.timesIdled 711 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 72620 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.771323 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.771323 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.296473 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.296473 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3463595596 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2019348323 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 39740 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 588 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 9207181 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4087.441061 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 712353360 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9211277 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 77.334919 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441061 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997910 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997910 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 698 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2969 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1470163219 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1470163219 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 556855010 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 556855010 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 155498347 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 155498347 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 712353357 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 712353357 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 712353357 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 712353357 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 12892455 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 12892455 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5230155 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5230155 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 18122610 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 18122610 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 18122610 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 18122610 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 411787652500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 315044398573 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 726832051073 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 726832051073 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 726832051073 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 726832051073 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 569747465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 569747465 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 730475967 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 730475967 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 730475967 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 730475967 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022628 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022628 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032540 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032540 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.024809 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.024809 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.024809 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.024809 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 40106.367188 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 40106.367188 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 15689743 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 9578184 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1104687 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 68028 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.202886 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 140.797672 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3727717 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3727717 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5560371 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5560371 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350963 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3350963 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 8911334 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 8911334 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 8911334 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 8911334 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332084 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7332084 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879192 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1879192 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9211276 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9211276 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9211276 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9211276 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84332021587 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 84332021587 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 267288661587 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 267288661587 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 755.122971 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 420623501 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 953 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 441367.786988 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 755.122971 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.368712 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.368712 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 952 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 886 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.464844 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 841250919 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 841250919 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 420623501 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 420623501 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 420623501 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 420623501 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 420623501 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 420623501 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1482 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 113433000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 113433000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 113433000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 113433000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 113433000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 113433000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 420624983 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 420624983 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 420624983 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 420624983 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 420624983 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 420624983 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 76540.485830 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 76540.485830 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu.icache.writebacks::total 1 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 529 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 529 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 529 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 529 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 953 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 953 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 953 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 953 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79168000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 79168000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79168000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 79168000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79168000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 79168000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83072.402938 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83072.402938 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83072.402938 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 83072.402938 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83072.402938 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 83072.402938 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1929037 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31408.501295 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 14580101 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1958824 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 7.443293 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 28140218000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14352.871617 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.846080 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.783598 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.438015 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000789 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.519708 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.958511 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 977 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17550 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10488 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 151193328 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 151193328 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 3727717 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 3727717 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1106791 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1106791 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6143698 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 6143698 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7250489 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7250489 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7250489 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7250489 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 772417 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 772417 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 953 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 953 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1188371 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 1188371 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 953 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1960788 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1961741 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 953 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1960788 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1961741 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69331694500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 69331694500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 77733500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 77733500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106499450500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 106499450500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 77733500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 175831145000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 175908878500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 77733500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 175831145000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 175908878500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 3727717 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 3727717 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879208 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1879208 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 953 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 953 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7332069 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 7332069 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 953 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9211277 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9212230 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 953 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9211277 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9212230 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411033 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.411033 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162079 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162079 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.212868 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.212950 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.212868 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.212950 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89759.410396 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89759.410396 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81567.156348 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89618.015334 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 89669.777254 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1024311 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1024311 # number of writebacks
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772417 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 772417 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188371 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188371 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1960788 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1961741 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1960788 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1961741 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61607524500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61607524500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68203500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68203500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94615740500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94615740500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68203500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68203500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411033 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411033 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162079 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162079 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.212950 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.212950 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 18419412 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207182 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 1280 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7333022 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 4752028 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 6384190 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1879208 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1879208 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 953 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332069 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1907 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629735 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 27631642 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828095616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 828156672 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 1929037 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 11141267 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.010718 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 11139987 99.99% 99.99% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 1280 0.01% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 11141267 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 12937424000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1429500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 13816915500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 1189324 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 1024311 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 903686 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 772417 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 772417 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 1189324 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851479 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 5851479 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191107328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 191107328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 3889738 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 3889738 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 3889738 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 8475624000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 10684646000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|