1579 lines
188 KiB
Plaintext
1579 lines
188 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 51.667600 # Number of seconds simulated
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sim_ticks 51667599599000 # Number of ticks simulated
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final_tick 51667599599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 178939 # Simulator instruction rate (inst/s)
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host_op_rate 210249 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 10020424354 # Simulator tick rate (ticks/s)
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host_mem_usage 726764 # Number of bytes of host memory used
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host_seconds 5156.23 # Real time elapsed on the host
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sim_insts 922648651 # Number of instructions simulated
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sim_ops 1084091117 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 355648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 310272 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 9988672 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 94253512 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory
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system.physmem.bytes_read::total 105321992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 9988672 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 9988672 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 87921472 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
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system.physmem.bytes_written::total 87942052 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 5557 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 4848 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 156073 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1472724 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1645669 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1373773 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1376346 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 6883 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 6005 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 193326 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1824229 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 8011 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2038453 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 193326 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 193326 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 1701675 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 1702073 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 1701675 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 6883 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 6005 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 193326 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1824627 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 8011 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3740527 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1645669 # Number of read requests accepted
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system.physmem.writeReqs 1376346 # Number of write requests accepted
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system.physmem.readBursts 1645669 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1376346 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 105266752 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 56064 # Total number of bytes read from write queue
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system.physmem.bytesWritten 87940608 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 105321992 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 87942052 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 876 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 378251 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 98784 # Per bank write bursts
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system.physmem.perBankRdBursts::1 105100 # Per bank write bursts
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system.physmem.perBankRdBursts::2 100845 # Per bank write bursts
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system.physmem.perBankRdBursts::3 95977 # Per bank write bursts
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system.physmem.perBankRdBursts::4 103819 # Per bank write bursts
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system.physmem.perBankRdBursts::5 113338 # Per bank write bursts
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system.physmem.perBankRdBursts::6 98145 # Per bank write bursts
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system.physmem.perBankRdBursts::7 99955 # Per bank write bursts
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system.physmem.perBankRdBursts::8 93968 # Per bank write bursts
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system.physmem.perBankRdBursts::9 154563 # Per bank write bursts
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system.physmem.perBankRdBursts::10 98779 # Per bank write bursts
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system.physmem.perBankRdBursts::11 100711 # Per bank write bursts
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system.physmem.perBankRdBursts::12 92945 # Per bank write bursts
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system.physmem.perBankRdBursts::13 97659 # Per bank write bursts
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system.physmem.perBankRdBursts::14 91699 # Per bank write bursts
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system.physmem.perBankRdBursts::15 98506 # Per bank write bursts
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system.physmem.perBankWrBursts::0 83240 # Per bank write bursts
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system.physmem.perBankWrBursts::1 87253 # Per bank write bursts
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system.physmem.perBankWrBursts::2 86416 # Per bank write bursts
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system.physmem.perBankWrBursts::3 83797 # Per bank write bursts
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system.physmem.perBankWrBursts::4 90075 # Per bank write bursts
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system.physmem.perBankWrBursts::5 95693 # Per bank write bursts
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system.physmem.perBankWrBursts::6 84431 # Per bank write bursts
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system.physmem.perBankWrBursts::7 87097 # Per bank write bursts
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system.physmem.perBankWrBursts::8 83064 # Per bank write bursts
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system.physmem.perBankWrBursts::9 88599 # Per bank write bursts
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system.physmem.perBankWrBursts::10 84727 # Per bank write bursts
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system.physmem.perBankWrBursts::11 86277 # Per bank write bursts
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system.physmem.perBankWrBursts::12 82015 # Per bank write bursts
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system.physmem.perBankWrBursts::13 84756 # Per bank write bursts
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system.physmem.perBankWrBursts::14 80845 # Per bank write bursts
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system.physmem.perBankWrBursts::15 85787 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
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system.physmem.totGap 51667597819500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 13 # Read request sizes (log2)
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system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1645654 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 1 # Write request sizes (log2)
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system.physmem.writePktSize::3 2572 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1373773 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1321004 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 317364 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 977 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 363 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 545 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 512 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1186 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 669 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 302 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 350 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 124 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::15 15051 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 17153 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 65956 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::18 81050 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 83118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 82838 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 83953 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::22 83921 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 85569 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 84918 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 85424 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 90109 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 84668 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 83357 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 92346 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 82532 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 83696 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 80480 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1093 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 699 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 466 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 417 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 387 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 390 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 303 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 302 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 352 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 236 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 252 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::46 215 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 268 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 175 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 155 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 53 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::60 61 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 648118 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 298.103938 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 174.284544 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 324.148793 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 253468 39.11% 39.11% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 156556 24.16% 63.26% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::256-383 60545 9.34% 72.61% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::384-511 34961 5.39% 78.00% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::512-639 26042 4.02% 82.02% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::640-767 18689 2.88% 84.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 14146 2.18% 87.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 13035 2.01% 89.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 70676 10.90% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 648118 # Bytes accessed per row activation
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|
system.physmem.rdPerTurnAround::samples 79768 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::mean 20.619672 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 282.463170 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-4095 79765 100.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 79768 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 79768 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 17.225855 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::gmean 16.793439 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 6.200790 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 77436 97.08% 97.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 326 0.41% 97.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 71 0.09% 97.57% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 315 0.39% 97.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 43 0.05% 98.02% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 360 0.45% 98.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 211 0.26% 98.74% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 25 0.03% 98.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 65 0.08% 98.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 125 0.16% 99.01% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 20 0.03% 99.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 34 0.04% 99.08% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 501 0.63% 99.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 33 0.04% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 30 0.04% 99.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 120 0.15% 99.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 8 0.01% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 3 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.00% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 4 0.01% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 23 0.03% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 4 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 79768 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 26467861730 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 57307730480 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 8223965000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 16091.91 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 34841.91 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 1338706 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 1032034 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 17097068.62 # Average gap between requests
|
|
system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 2524404960 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 1377403500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 6364503600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 4523001120 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 1325410671600 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 29837914926750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 34552790914410 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 668.751704 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 49637080843701 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 1725294480000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 305218373299 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 2375306640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 1296050250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 6464827200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 4380881760 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3374676002880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 1318079999925 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 29844345348750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 34551618417405 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 668.729010 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 49647781129555 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1725294480000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 294523106445 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
|
|
system.cpu.branchPred.lookups 252640803 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 176566458 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 11942340 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 185523828 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 131623059 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 70.946714 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 30927608 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 2129490 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 561342 # Table walker walks requested
|
|
system.cpu.dtb.walker.walksLong 561342 # Table walker walks initiated with long descriptors
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20890 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 179371 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.dtb.walker.walkWaitTime::samples 561342 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::0 561342 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::total 561342 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 200261 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 26959.987217 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 22796.816332 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 20928.483641 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::0-65535 197960 98.85% 98.85% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 98.85% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1973 0.99% 99.84% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::262144-327679 114 0.06% 99.92% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::327680-393215 41 0.02% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::393216-458751 90 0.04% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::total 200261 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walkPageSizes::4K 179372 89.57% 89.57% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::2M 20890 10.43% 100.00% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::total 200262 # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 561342 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 561342 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 200262 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 200262 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 761604 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 178417728 # DTB read hits
|
|
system.cpu.dtb.read_misses 463663 # DTB read misses
|
|
system.cpu.dtb.write_hits 158017805 # DTB write hits
|
|
system.cpu.dtb.write_misses 97679 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 77601 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 1384 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 14410 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 178881391 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 158115484 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 336435533 # DTB hits
|
|
system.cpu.dtb.misses 561342 # DTB misses
|
|
system.cpu.dtb.accesses 336996875 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 135051 # Table walker walks requested
|
|
system.cpu.itb.walker.walksLong 135051 # Table walker walks initiated with long descriptors
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1071 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walksLongTerminationLevel::Level3 117673 # Level at which table walker walks with long descriptors terminate
|
|
system.cpu.itb.walker.walkWaitTime::samples 135051 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 135051 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 135051 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkCompletionTime::samples 118744 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::mean 30328.088156 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 25835.192345 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 23534.472369 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::0-32767 58823 49.54% 49.54% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::32768-65535 57227 48.19% 97.73% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.73% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::98304-131071 5 0.00% 97.74% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::131072-163839 2006 1.69% 99.43% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::163840-196607 464 0.39% 99.82% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::196608-229375 29 0.02% 99.84% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::229376-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::262144-294911 88 0.07% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::294912-327679 29 0.02% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::327680-360447 14 0.01% 99.98% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::360448-393215 13 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::393216-425983 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::total 118744 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walkPageSizes::4K 117673 99.10% 99.10% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::2M 1071 0.90% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 118744 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 135051 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 135051 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118744 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 118744 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 253795 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 439141642 # ITB inst hits
|
|
system.cpu.itb.inst_misses 135051 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 55572 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 356769 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 439276693 # ITB inst accesses
|
|
system.cpu.itb.hits 439141642 # DTB hits
|
|
system.cpu.itb.misses 135051 # DTB misses
|
|
system.cpu.itb.accesses 439276693 # DTB accesses
|
|
system.cpu.numCycles 2565959423 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 922648651 # Number of instructions committed
|
|
system.cpu.committedOps 1084091117 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 92858708 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching
|
|
system.cpu.quiesceCycles 100770378430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu.cpi 2.781080 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.359573 # IPC: instructions per cycle
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed
|
|
system.cpu.tickCycles 1742118066 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 823841357 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 10735802 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.930082 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 320587267 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 10736314 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 29.860087 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.930082 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1346721008 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1346721008 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 164117651 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 164117651 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 147554232 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 147554232 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 511700 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 511700 # number of SoftPFReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::cpu.data 336216 # number of WriteLineReq hits
|
|
system.cpu.dcache.WriteLineReq_hits::total 336216 # number of WriteLineReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3856271 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 3856271 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 4163172 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 4163172 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 311671883 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 311671883 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 312183583 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 312183583 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 6375380 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 6375380 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 4133213 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 4133213 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 1400858 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 1400858 # number of SoftPFReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::cpu.data 1238861 # number of WriteLineReq misses
|
|
system.cpu.dcache.WriteLineReq_misses::total 1238861 # number of WriteLineReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 308609 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 308609 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 10508593 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 10508593 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 11909451 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 11909451 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 117756219000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 117756219000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 201470838000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 201470838000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84198421500 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.WriteLineReq_miss_latency::total 84198421500 # number of WriteLineReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5139608000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 5139608000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 319227057000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 319227057000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 319227057000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 319227057000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 170493031 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 170493031 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 151687445 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 151687445 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1912558 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 1912558 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1575077 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteLineReq_accesses::total 1575077 # number of WriteLineReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164880 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 4164880 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163173 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 4163173 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 322180476 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 322180476 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 324093034 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 324093034 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037394 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.037394 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027248 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.027248 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732453 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.732453 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786540 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_miss_rate::total 0.786540 # miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074098 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074098 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.032617 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.032617 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.036747 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.036747 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18470.462780 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 18470.462780 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48744.363767 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 48744.363767 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 67964.381395 # average WriteLineReq miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 67964.381395 # average WriteLineReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16654.109245 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16654.109245 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 30377.716313 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 30377.716313 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26804.514918 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 26804.514918 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 8239619 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 8239619 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 773301 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 773301 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821450 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1821450 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 142 # number of WriteLineReq MSHR hits
|
|
system.cpu.dcache.WriteLineReq_mshr_hits::total 142 # number of WriteLineReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70152 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 70152 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 2594751 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 2594751 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 2594751 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 2594751 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5602079 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 5602079 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2311763 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2311763 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1393294 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1393294 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238719 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.WriteLineReq_mshr_misses::total 1238719 # number of WriteLineReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 238457 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 238457 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 7913842 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 7913842 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9307136 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9307136 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96321163500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 96321163500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106904157500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 106904157500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26939627500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26939627500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 82952613500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 82952613500 # number of WriteLineReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3468831500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3468831500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 203225321000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 203225321000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230164948500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 230164948500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6198462000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6198462000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207588500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207588500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12406050500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 12406050500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032858 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032858 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015240 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015240 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728498 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728498 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786450 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786450 # mshr miss rate for WriteLineReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057254 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057254 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024563 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.024563 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028717 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.028717 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17193.824560 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17193.824560 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46243.562813 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46243.562813 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19335.206712 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19335.206712 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66966.449614 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66966.449614 # average WriteLineReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14546.989604 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14546.989604 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25679.729391 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25679.729391 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24729.943615 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24729.943615 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183946.998249 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183946.998249 # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184168.649499 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184168.649499 # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184057.838672 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184057.838672 # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 24189642 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 414582353 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 24190154 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 17.138475 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 462962680 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 462962680 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 414582353 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 414582353 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 414582353 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 414582353 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 414582353 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 414582353 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 24190164 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 24190164 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 24190164 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 24190164 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 24190164 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 24190164 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327340789000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 327340789000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 327340789000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 327340789000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 327340789000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 327340789000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 438772517 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 438772517 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 438772517 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 438772517 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 438772517 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 438772517 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055131 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.055131 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.055131 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.055131 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.055131 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.055131 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13531.978907 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13531.978907 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13531.978907 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13531.978907 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13531.978907 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13531.978907 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 24189642 # number of writebacks
|
|
system.cpu.icache.writebacks::total 24189642 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24190164 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 24190164 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 24190164 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 24190164 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 24190164 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 24190164 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303150626000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 303150626000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303150626000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 303150626000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303150626000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 303150626000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746864000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746864000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746864000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 6746864000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055131 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.055131 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055131 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.055131 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12531.978948 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12531.978948 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12531.978948 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12531.978948 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12531.978948 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12531.978948 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.940182 # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.940182 # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.940182 # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1495284 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 65229.781494 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 65922487 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1558468 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 42.299545 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 36600562500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 36948.253650 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 327.788805 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 379.909026 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7890.502586 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 19683.327428 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.563786 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005797 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120400 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.300344 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.995327 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62947 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 237 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 502 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2422 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54486 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960495 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 573928107 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 573928107 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 915811 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 279303 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1195114 # number of ReadReq hits
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 8239619 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 8239619 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 24185917 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 24185917 # number of WritebackClean hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 10440 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 10440 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1637843 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1637843 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24086368 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 24086368 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6914406 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 6914406 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.InvalidateReq_hits::cpu.data 709945 # number of InvalidateReq hits
|
|
system.cpu.l2cache.InvalidateReq_hits::total 709945 # number of InvalidateReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 915811 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 279303 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 24086368 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 8552249 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 33833731 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 915811 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 279303 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 24086368 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 8552249 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 33833731 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5557 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4848 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 10405 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 37520 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 37520 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 626190 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 626190 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 103793 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 103793 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 319194 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 319194 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.InvalidateReq_misses::cpu.data 528774 # number of InvalidateReq misses
|
|
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|
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system.cpu.l2cache.overall_misses::cpu.dtb.walker 5557 # number of overall misses
|
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|
|
system.cpu.l2cache.overall_misses::cpu.inst 103793 # number of overall misses
|
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system.cpu.l2cache.overall_misses::cpu.data 945384 # number of overall misses
|
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system.cpu.l2cache.overall_misses::total 1059582 # number of overall misses
|
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system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 763202000 # number of ReadReq miss cycles
|
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system.cpu.l2cache.ReadReq_miss_latency::total 1426208000 # number of ReadReq miss cycles
|
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system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1483103000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 1483103000 # number of UpgradeReq miss cycles
|
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system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles
|
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system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 83070292000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 83070292000 # number of ReadExReq miss cycles
|
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system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13727586500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 13727586500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42966847500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 42966847500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73371785500 # number of InvalidateReq miss cycles
|
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system.cpu.l2cache.InvalidateReq_miss_latency::total 73371785500 # number of InvalidateReq miss cycles
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system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 763202000 # number of demand (read+write) miss cycles
|
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system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 663006000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 13727586500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 126037139500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 141190934000 # number of demand (read+write) miss cycles
|
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system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 763202000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 663006000 # number of overall miss cycles
|
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system.cpu.l2cache.overall_miss_latency::cpu.inst 13727586500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 126037139500 # number of overall miss cycles
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|
system.cpu.l2cache.overall_miss_latency::total 141190934000 # number of overall miss cycles
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|
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system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 284151 # number of ReadReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadReq_accesses::total 1205519 # number of ReadReq accesses(hits+misses)
|
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system.cpu.l2cache.WritebackDirty_accesses::writebacks 8239619 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 8239619 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 24185917 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 24185917 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 47960 # number of UpgradeReq accesses(hits+misses)
|
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system.cpu.l2cache.UpgradeReq_accesses::total 47960 # number of UpgradeReq accesses(hits+misses)
|
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system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.data 2264033 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2264033 # number of ReadExReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24190161 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 24190161 # number of ReadCleanReq accesses(hits+misses)
|
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system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7233600 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.ReadSharedReq_accesses::total 7233600 # number of ReadSharedReq accesses(hits+misses)
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system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238719 # number of InvalidateReq accesses(hits+misses)
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system.cpu.l2cache.InvalidateReq_accesses::total 1238719 # number of InvalidateReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses::cpu.dtb.walker 921368 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.itb.walker 284151 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_accesses::cpu.inst 24190161 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses::cpu.dtb.walker 921368 # number of overall (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::cpu.itb.walker 284151 # number of overall (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::cpu.inst 24190161 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9497633 # number of overall (read+write) accesses
|
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system.cpu.l2cache.overall_accesses::total 34893313 # number of overall (read+write) accesses
|
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system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006031 # miss rate for ReadReq accesses
|
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system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.017061 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.008631 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782319 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782319 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.276582 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.276582 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004291 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004291 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.044127 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.044127 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.426872 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.426872 # miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006031 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.017061 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004291 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.099539 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.030366 # miss rate for demand accesses
|
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system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006031 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.017061 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004291 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.099539 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.030366 # miss rate for overall accesses
|
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137340.651431 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136758.663366 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137069.485824 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39528.331557 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39528.331557 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132659.882783 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132659.882783 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132259.270856 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132259.270856 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134610.448505 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134610.448505 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138758.307897 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138758.307897 # average InvalidateReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137340.651431 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136758.663366 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132259.270856 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133318.460541 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 133251.540702 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137340.651431 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136758.663366 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132259.270856 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133318.460541 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 133251.540702 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
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system.cpu.l2cache.writebacks::writebacks 1267142 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1267142 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits
|
|
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|
|
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|
|
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|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
|
|
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|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
|
|
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|
|
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|
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|
|
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|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 10405 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses
|
|
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|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37520 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 37520 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 626190 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::total 626190 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 103790 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.ReadCleanReq_mshr_misses::total 103790 # number of ReadCleanReq MSHR misses
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system.cpu.l2cache.ReadSharedReq_mshr_misses::total 319173 # number of ReadSharedReq MSHR misses
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system.cpu.l2cache.InvalidateReq_mshr_misses::total 528774 # number of InvalidateReq MSHR misses
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|
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|
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system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5819359500 # number of WriteReq MSHR uncacheable cycles
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|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11596549000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 17532623000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008631 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782319 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782319 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.276582 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.276582 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004291 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.044124 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.044124 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.426872 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.426872 # mshr miss rate for InvalidateReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.030366 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006031 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017061 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004291 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099537 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.030366 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127069.485824 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70780.463753 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70780.463753 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122659.882783 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122659.882783 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122260.477888 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122260.477888 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124612.188374 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124612.188374 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128758.307897 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128758.307897 # average InvalidateReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127340.651431 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126758.663366 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122260.477888 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123319.019255 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123252.158919 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171445.217675 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136191.236658 # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172650.551831 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172650.551831 # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172047.965224 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146456.687717 # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 70595106 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 35668602 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4412 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 2257 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2257 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 1731880 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 33156424 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 9613409 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 24185917 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 2732498 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 47963 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 47964 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2264033 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2264033 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 24190164 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 7242479 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateReq 1345383 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::InvalidateResp 1238719 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72670859 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32439334 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687653 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2163740 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 107961586 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3099416704 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135424530 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2273208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7370944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 4244485386 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 2167477 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 38466398 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.018246 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.133841 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 37764532 98.18% 98.18% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 701866 1.82% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 38466398 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 68278869995 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1476392 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 36370852681 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14941078957 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 403557888 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 1242412419 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 40327 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 40327 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 42171500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 25807000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 34147000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 120500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 565729644 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 42000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 147772000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 115488 # number of replacements
|
|
system.iocache.tags.tagsinuse 10.440019 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 115504 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 13160148501000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_blocks::realview.ide 6.919178 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 1039911 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 1039911 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
|
|
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 8882 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
|
|
system.iocache.overall_misses::realview.ide 8842 # number of overall misses
|
|
system.iocache.overall_misses::total 8882 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::realview.ide 1658170108 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 1663256608 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::realview.ide 13863609036 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 13863609036 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 1658170108 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 1663607608 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 1658170108 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 1663607608 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 187533.375707 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 187324.767204 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.584077 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 129974.584077 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 187301.014186 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 187533.375707 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 187301.014186 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 34622 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.886351 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 106631 # number of writebacks
|
|
system.iocache.writebacks::total 106631 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1216070108 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 1219306608 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530409036 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 8530409036 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 1216070108 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 1219507608 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 1216070108 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 1219507608 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137533.375707 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 137324.767204 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.584077 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.584077 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 137533.375707 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 137301.014186 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 86006 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 528253 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 33706 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 33706 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 1373773 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 233285 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 38309 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1154179 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1154179 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 442247 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4854992 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4984644 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341559 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 341559 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 5326203 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186025772 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186196178 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 7238272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 193434450 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3077 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 3470793 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 3470793 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 3470793 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 102553500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 5511000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 9297161713 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 8798501817 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 227863618 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.txBytes 966 # Bytes Transmitted
|
|
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
|
|
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
|
|
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
|
|
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
|
|
system.realview.ethernet.totPackets 3 # Total Packets
|
|
system.realview.ethernet.totBytes 966 # Total Bytes
|
|
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
|
|
system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
|
|
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
|
|
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
|
|
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
|
|
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
|
|
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
|
|
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
|
|
|
|
---------- End Simulation Statistics ----------
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