895 lines
103 KiB
Plaintext
895 lines
103 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.363578 # Number of seconds simulated
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sim_ticks 363578056500 # Number of ticks simulated
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final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 237399 # Simulator instruction rate (inst/s)
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host_op_rate 257134 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 170382928 # Simulator tick rate (ticks/s)
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host_mem_usage 321244 # Number of bytes of host memory used
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host_seconds 2133.89 # Real time elapsed on the host
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sim_insts 506582156 # Number of instructions simulated
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sim_ops 548695379 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory
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system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory
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system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 143938 # Number of read requests accepted
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system.physmem.writeReqs 97172 # Number of write requests accepted
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system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
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system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 9337 # Per bank write bursts
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system.physmem.perBankRdBursts::1 8920 # Per bank write bursts
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system.physmem.perBankRdBursts::2 8993 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8670 # Per bank write bursts
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system.physmem.perBankRdBursts::4 9385 # Per bank write bursts
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system.physmem.perBankRdBursts::5 9354 # Per bank write bursts
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system.physmem.perBankRdBursts::6 8954 # Per bank write bursts
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system.physmem.perBankRdBursts::7 8104 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8602 # Per bank write bursts
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system.physmem.perBankRdBursts::9 8629 # Per bank write bursts
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system.physmem.perBankRdBursts::10 8738 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9458 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9338 # Per bank write bursts
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system.physmem.perBankRdBursts::13 9514 # Per bank write bursts
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system.physmem.perBankRdBursts::14 8722 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9109 # Per bank write bursts
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system.physmem.perBankWrBursts::0 6210 # Per bank write bursts
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system.physmem.perBankWrBursts::1 6096 # Per bank write bursts
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system.physmem.perBankWrBursts::2 6031 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5885 # Per bank write bursts
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system.physmem.perBankWrBursts::4 6239 # Per bank write bursts
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system.physmem.perBankWrBursts::5 6240 # Per bank write bursts
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system.physmem.perBankWrBursts::6 6045 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5507 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5786 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5860 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5977 # Per bank write bursts
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system.physmem.perBankWrBursts::11 6497 # Per bank write bursts
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system.physmem.perBankWrBursts::12 6353 # Per bank write bursts
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system.physmem.perBankWrBursts::13 6323 # Per bank write bursts
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system.physmem.perBankWrBursts::14 6005 # Per bank write bursts
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system.physmem.perBankWrBursts::15 6089 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 363578030500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 143938 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 97172 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads
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system.physmem.totQLat 1537591000 # Total ticks spent queuing
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system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.33 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing
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system.physmem.readRowHits 110822 # Number of row buffer hits during reads
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system.physmem.writeRowHits 64690 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes
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system.physmem.avgGap 1507934.26 # Average gap between requests
|
|
system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 684.723644 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 684.636777 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 131892190 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 727156113 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 506582156 # Number of instructions committed
|
|
system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.435416 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.696662 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 1139983 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 168191146 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1555406 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1068257 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 17711 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 199302654 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 19583 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 19583 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 19583 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 19583 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 19583 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 449788500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 449788500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 449788500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 449788500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 449788500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 449788500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 199322237 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 199322237 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 199322237 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 199322237 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 199322237 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 199322237 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 22968.314354 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 22968.314354 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks::writebacks 17711 # number of writebacks
|
|
system.cpu.icache.writebacks::total 17711 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19583 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 19583 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 19583 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 19583 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 19583 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 19583 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 430205500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 430205500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 430205500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 430205500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 430205500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 430205500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21968.314354 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 112366 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 27636.027175 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1768435 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 143575 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 12.317151 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 163253484000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 23509.918170 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.069777 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.039228 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.717466 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009402 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.116517 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.843385 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31209 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4938 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25851 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952423 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 19031534 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 19031534 # Number of data accesses
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 1068257 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 1068257 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 17475 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 17475 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 255492 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 255492 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16775 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 16775 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747442 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 747442 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 16775 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1002934 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1019709 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 16775 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1002934 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1019709 # number of overall hits
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 100923 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 100923 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2808 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 2808 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40222 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 40222 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2808 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 141145 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 143953 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2808 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 141145 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 143953 # number of overall misses
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7911788000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7911788000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224015500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 224015500 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3310285500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 3310285500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 224015500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11222073500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11446089000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 224015500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11222073500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11446089000 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068257 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 1068257 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 17475 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 17475 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19583 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 19583 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787664 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 787664 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 19583 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1144079 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1163662 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 19583 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1144079 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1163662 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283161 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.283161 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.143390 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.143390 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051065 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051065 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143390 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.123370 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.123707 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143390 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.123370 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.123707 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78394.300605 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78394.300605 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79777.599715 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79777.599715 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82300.370444 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82300.370444 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 79512.681222 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 79512.681222 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 97172 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 97172 # number of writebacks
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100923 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 100923 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2807 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2807 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40208 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40208 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2807 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 141131 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 143938 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2807 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141131 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 143938 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6902558000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6902558000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195877500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195877500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2907247000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2907247000 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195877500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9809805000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10005682500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 112366 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadResp 43015 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 12571 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 100923 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 100923 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 253681 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 253681 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|