1805 lines
207 KiB
Plaintext
1805 lines
207 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 1.977709 # Number of seconds simulated
|
|
sim_ticks 1977709274000 # Number of ticks simulated
|
|
final_tick 1977709274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 1549555 # Simulator instruction rate (inst/s)
|
|
host_op_rate 1549555 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 51561372502 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 334884 # Number of bytes of host memory used
|
|
host_seconds 38.36 # Real time elapsed on the host
|
|
sim_insts 59435338 # Number of instructions simulated
|
|
sim_ops 59435338 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 23907392 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 165888 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 1310592 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 26079168 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 165888 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 860224 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 7747712 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 7747712 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 373553 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 2592 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 20478 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 407487 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 121058 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 121058 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.inst 351081 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 12088426 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 83879 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 662682 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::tsunami.ide 485 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 13186553 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 351081 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 83879 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 434960 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 3917518 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 3917518 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 3917518 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 351081 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 12088426 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 83879 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 662682 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::tsunami.ide 485 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 17104071 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 407487 # Number of read requests accepted
|
|
system.physmem.writeReqs 121058 # Number of write requests accepted
|
|
system.physmem.readBursts 407487 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 121058 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 26071296 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 7746112 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 26079168 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 7747712 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 306935 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 25840 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 26009 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 26271 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 25739 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 24904 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 25588 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 25282 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 25179 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 24919 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 24911 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 25224 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 25266 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 25817 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 25627 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 25517 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 25271 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 8076 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 7966 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 8289 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 8035 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 7145 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 7755 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 7349 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 7181 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 6971 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 7004 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 7220 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 7086 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 7863 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 7891 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 7798 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 7404 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 19 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 1977655892500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 407487 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 121058 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 407280 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 71 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 2225 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 5815 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 5820 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 6408 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 6734 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 6151 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 6513 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 8012 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 8348 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 8437 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 8803 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 7622 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 6918 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 5930 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 5620 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 157 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 153 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 207 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 101 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 123 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 153 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 65 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 68003 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 497.292884 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 300.084252 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 405.105473 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 16504 24.27% 24.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 12590 18.51% 42.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 5294 7.78% 50.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3182 4.68% 55.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 2479 3.65% 58.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 4294 6.31% 65.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 1483 2.18% 67.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 2078 3.06% 70.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 20099 29.56% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 68003 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 5421 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 75.144069 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 2865.262786 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-8191 5418 99.94% 99.94% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 5421 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 5421 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 22.326692 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 19.006479 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 21.134399 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4779 88.16% 88.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 22 0.41% 88.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 23 0.42% 88.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 175 3.23% 92.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 9 0.17% 92.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 25 0.46% 92.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 50 0.92% 93.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 2 0.04% 93.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 13 0.24% 94.04% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 19 0.35% 94.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 1 0.02% 94.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 6 0.11% 94.52% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 8 0.15% 94.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 2 0.04% 94.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 22 0.41% 95.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 20 0.37% 95.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 4 0.07% 95.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 34 0.63% 96.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.02% 96.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 2 0.04% 96.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 161 2.97% 99.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.04% 99.24% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.26% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 3 0.06% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 2 0.04% 99.35% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 6 0.11% 99.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::164-167 5 0.09% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::168-171 3 0.06% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::180-183 16 0.30% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-219 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5421 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 2796894000 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 10434969000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2036820000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 6865.83 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 25615.83 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.18 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.19 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.13 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 363824 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 96570 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 89.31 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 79.77 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3741698.23 # Average gap between requests
|
|
system.physmem.pageHitRate 87.13 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 262483200 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 143220000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1597533600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 400438080 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 73962048600 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1121745657750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1327285621230 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 671.123235 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1865834845500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 66040000000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 45832914500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 251619480 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 137292375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1579905600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 383855760 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 73584887580 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1122076500750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1327188301545 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 671.074027 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1866389529250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 66040000000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 45278230750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 5727753 # DTB read hits
|
|
system.cpu0.dtb.read_misses 7442 # DTB read misses
|
|
system.cpu0.dtb.read_acv 210 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 490672 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 3981122 # DTB write hits
|
|
system.cpu0.dtb.write_misses 812 # DTB write misses
|
|
system.cpu0.dtb.write_acv 134 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 187451 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 9708875 # DTB hits
|
|
system.cpu0.dtb.data_misses 8254 # DTB misses
|
|
system.cpu0.dtb.data_acv 344 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 678123 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 3124468 # ITB hits
|
|
system.cpu0.itb.fetch_misses 3871 # ITB misses
|
|
system.cpu0.itb.fetch_acv 184 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 3128339 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numCycles 3955086246 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 4843 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 129735 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 41337 38.33% 38.33% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 131 0.12% 38.45% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1972 1.83% 40.28% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 64391 59.71% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 107848 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 40894 48.75% 48.75% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1972 2.35% 51.25% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 17 0.02% 51.27% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 40877 48.73% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 83891 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1907093255000 96.44% 96.44% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 94033500 0.00% 96.44% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 783814000 0.04% 96.48% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 14262000 0.00% 96.48% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 69557728500 3.52% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1977543093000 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.989283 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.634825 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.777863 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
|
|
system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 222 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 93 0.08% 0.08% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 1998 1.74% 1.82% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 51 0.04% 1.87% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.01% 1.87% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 101884 88.63% 90.50% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 6548 5.70% 96.19% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.20% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 3 0.00% 96.20% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 9 0.01% 96.21% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 96.21% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 3843 3.34% 99.55% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 381 0.33% 99.88% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 136 0.12% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 114960 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 5413 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1282
|
|
system.cpu0.kern.mode_good::user 1282
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.236837 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.382972 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1972827474000 99.80% 99.80% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 3894173000 0.20% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 1999 # number of times the context was actually changed
|
|
system.cpu0.committedInsts 36251265 # Number of instructions committed
|
|
system.cpu0.committedOps 36251265 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 33727452 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 135758 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 876834 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4248905 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 33727452 # number of integer instructions
|
|
system.cpu0.num_fp_insts 135758 # number of float instructions
|
|
system.cpu0.num_int_register_reads 46333717 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 25193797 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 65701 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 66416 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 9739707 # number of memory refs
|
|
system.cpu0.num_load_insts 5749561 # Number of load instructions
|
|
system.cpu0.num_store_insts 3990146 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 3736968981.972937 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 218117264.027063 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.055149 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.944851 # Percentage of idle cycles
|
|
system.cpu0.Branches 5398761 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 1979626 5.46% 5.46% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 23753610 65.51% 70.97% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 36908 0.10% 71.07% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 71.07% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 22960 0.06% 71.13% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 1656 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.14% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 5882505 16.22% 87.36% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 3995282 11.02% 98.38% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 587316 1.62% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 36259863 # Class of executed instruction
|
|
system.cpu0.dcache.tags.replacements 822072 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 480.504845 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 8885001 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 822496 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 10.802485 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.504845 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938486 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.938486 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 39682070 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 39682070 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 5000163 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 5000163 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3644006 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3644006 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117543 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 117543 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123259 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 123259 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 8644169 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 8644169 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 8644169 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 8644169 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 612538 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 612538 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 209263 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 209263 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6851 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 6851 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 636 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 636 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 821801 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 821801 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 821801 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 821801 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38657814000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 38657814000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 14917066000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 14917066000 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93675500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 93675500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8969500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 8969500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 53574880000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 53574880000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 53574880000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 53574880000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5612701 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 5612701 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3853269 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 3853269 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124394 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 124394 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 123895 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 9465970 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 9465970 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 9465970 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 9465970 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.109134 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.109134 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054308 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.054308 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055075 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055075 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005133 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005133 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086816 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.086816 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086816 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.086816 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 63110.882917 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 63110.882917 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 366665 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 366665 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 612538 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 612538 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 209263 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 209263 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6851 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6851 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 636 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 636 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 821801 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 821801 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 821801 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 821801 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4814 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8193 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 13007 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38045276000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38045276000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 14707803000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 14707803000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86824500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86824500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 8333500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 8333500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 52753079000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 52753079000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 52753079000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 52753079000 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1072338000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1072338000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1840159000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1840159000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2912497000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2912497000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.109134 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.109134 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054308 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054308 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055075 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055075 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005133 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005133 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.086816 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.086816 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 62110.882917 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 62110.882917 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 70283.819882 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70283.819882 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12673.259378 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.259378 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13102.987421 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13102.987421 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222754.050686 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222754.050686 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 224601.367021 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224601.367021 # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 490042 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 506.476572 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 35769214 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 490554 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 72.915956 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.476572 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989212 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.989212 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 296 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 36750512 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 36750512 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 35769214 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 35769214 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 35769214 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 35769214 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 35769214 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 35769214 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 490649 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 490649 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 490649 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 490649 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 490649 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 490649 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7808174000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 7808174000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 7808174000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 7808174000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 7808174000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 7808174000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 36259863 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 36259863 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 36259863 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 36259863 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 36259863 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 36259863 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013531 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.013531 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013531 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.013531 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013531 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.013531 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 15913.971087 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 15913.971087 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.writebacks::writebacks 490042 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 490042 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490649 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 490649 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 490649 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 490649 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 490649 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 490649 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7317525000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7317525000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7317525000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 7317525000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7317525000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 7317525000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013531 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.013531 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.013531 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 3965416 # DTB read hits
|
|
system.cpu1.dtb.read_misses 2993 # DTB read misses
|
|
system.cpu1.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 239364 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 2725894 # DTB write hits
|
|
system.cpu1.dtb.write_misses 342 # DTB write misses
|
|
system.cpu1.dtb.write_acv 29 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 105248 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 6691310 # DTB hits
|
|
system.cpu1.dtb.data_misses 3335 # DTB misses
|
|
system.cpu1.dtb.data_acv 29 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 344612 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 2218092 # ITB hits
|
|
system.cpu1.itb.fetch_misses 1216 # ITB misses
|
|
system.cpu1.itb.fetch_acv 0 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 2219308 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numCycles 3955418548 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 3977 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 108865 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 40405 40.60% 40.60% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1966 1.98% 42.57% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 93 0.09% 42.67% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 57058 57.33% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 99522 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 39471 48.79% 48.79% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1966 2.43% 51.21% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 93 0.11% 51.33% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 39378 48.67% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 80908 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1902956585000 96.22% 96.22% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 734079500 0.04% 96.26% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 70449000 0.00% 96.26% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 73947425500 3.74% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1977708539000 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.976884 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.690140 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.812966 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
|
|
system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 104 # number of syscalls executed
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 2247 2.20% 2.22% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 3 0.00% 2.22% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 2.23% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 94014 91.97% 94.20% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2296 2.25% 96.44% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 96.44% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 4 0.00% 96.45% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.00% 96.45% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3448 3.37% 99.82% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 136 0.13% 99.96% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 44 0.04% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 102224 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 2738 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 463 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2043 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 518
|
|
system.cpu1.kern.mode_good::user 463
|
|
system.cpu1.kern.mode_good::idle 55
|
|
system.cpu1.kern.mode_switch_good::kernel 0.189189 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.026921 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.197559 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 70603027000 3.57% 3.57% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 1708148000 0.09% 3.66% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1905397362000 96.34% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 2248 # number of times the context was actually changed
|
|
system.cpu1.committedInsts 23184073 # Number of instructions committed
|
|
system.cpu1.committedOps 23184073 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 21342235 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 193178 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 708348 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2510657 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 21342235 # number of integer instructions
|
|
system.cpu1.num_fp_insts 193178 # number of float instructions
|
|
system.cpu1.num_int_register_reads 29195011 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 15673593 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 100176 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 102374 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 6716060 # number of memory refs
|
|
system.cpu1.num_load_insts 3980976 # Number of load instructions
|
|
system.cpu1.num_store_insts 2735084 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 3859200221.998049 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 96218326.001951 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.024326 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.975674 # Percentage of idle cycles
|
|
system.cpu1.Branches 3468812 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 1369332 5.91% 5.91% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 14462485 62.37% 68.28% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 32790 0.14% 68.42% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 68.42% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 15288 0.07% 68.48% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 68.48% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 68.48% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 68.48% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 1986 0.01% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.49% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 4085109 17.62% 86.11% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 2736216 11.80% 97.91% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 484231 2.09% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 23187437 # Class of executed instruction
|
|
system.cpu1.dcache.tags.replacements 637928 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 487.645459 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 6059697 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 638440 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 9.491412 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 77414441500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.645459 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.952433 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.952433 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 27453473 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 27453473 # Number of data accesses
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 3383453 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 3383453 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 2527183 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 2527183 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 67642 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 67642 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79428 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 79428 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 5910636 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 5910636 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 5910636 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 5910636 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 511536 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 511536 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 119772 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 119772 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12967 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 12967 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 653 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 653 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 631308 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 631308 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 631308 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 631308 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6625803500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 6625803500 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3933748500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3933748500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 167428500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 167428500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 10386500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 10386500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 10559552000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 10559552000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 10559552000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 10559552000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 3894989 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 3894989 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 2646955 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 2646955 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 80609 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 80609 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80081 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 80081 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 6541944 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 6541944 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 6541944 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 6541944 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131332 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.131332 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045249 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.045249 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160863 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160863 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.008154 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.008154 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.096502 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.096502 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.096502 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.096502 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 16726.466321 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 16726.466321 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 496006 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 496006 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 511536 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 511536 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 119772 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 119772 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12967 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12967 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 653 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 653 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 631308 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 631308 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 631308 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 631308 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2385 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4228 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6613 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 6114267500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 6114267500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3813976500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3813976500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 154461500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 154461500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 9733500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 9733500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9928244000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 9928244000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9928244000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 9928244000 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520029500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520029500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 992921500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 992921500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1512951000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1512951000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.131332 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.131332 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045249 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045249 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160863 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160863 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.008154 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.008154 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.096502 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.096502 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602 # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.icache.tags.replacements 510167 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 496.053321 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 22676720 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 510679 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 44.405037 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 117353975500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.053321 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968854 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.968854 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 23698156 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 23698156 # Number of data accesses
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 22676720 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 22676720 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 22676720 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 22676720 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 22676720 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 22676720 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 510718 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 510718 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 510718 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 510718 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 510718 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 510718 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7116614500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 7116614500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 7116614500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 7116614500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 7116614500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 7116614500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 23187438 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 23187438 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 23187438 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 23187438 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 23187438 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 23187438 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022026 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.022026 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022026 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.022026 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022026 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.022026 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13934.528448 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13934.528448 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.writebacks::writebacks 510167 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 510167 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 510718 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 510718 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 510718 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 510718 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 510718 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 510718 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6605896500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 6605896500 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6605896500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 6605896500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6605896500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 6605896500 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022026 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.022026 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.022026 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 53973 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 53973 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10632 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 39240 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 122698 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 68786 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2730426 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 11275500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 391000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 174500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6042000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 211500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 130500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer29.occupancy 215040242 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 26819000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41954000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 41699 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.491123 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1769281205000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.491123 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.030695 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.030695 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375561 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375561 # Number of data accesses
|
|
system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 177 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 177 # number of overall misses
|
|
system.iocache.overall_misses::total 177 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22195883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22195883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429420359 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 5429420359 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 22195883 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 22195883 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 22195883 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 22195883 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 125400.468927 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 125400.468927 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 125400.468927 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 9.250000 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 41522 # number of writebacks
|
|
system.iocache.writebacks::total 41522 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13345883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13345883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351820359 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 3351820359 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 13345883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 13345883 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 13345883 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 13345883 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 342255 # number of replacements
|
|
system.l2c.tags.tagsinuse 65190.453062 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 3793407 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 407257 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 9.314529 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 54971.310995 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 3771.999936 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 4805.186829 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1123.175084 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 518.780218 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.838796 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.057556 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.073321 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.017138 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.007916 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.994727 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65002 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 1065 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 4849 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 6325 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 52587 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.991852 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 36989627 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 36989627 # Number of data accesses
|
|
system.l2c.WritebackDirty_hits::writebacks 862671 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 862671 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 732220 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 732220 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 102038 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 98486 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 200524 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 479778 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 508114 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 987892 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 344131 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 495524 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 839655 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 479778 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 446169 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 508114 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 594010 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2028071 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 479778 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 446169 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 508114 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 594010 # number of overall hits
|
|
system.l2c.overall_hits::total 2028071 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 2602 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 3085 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 77 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 94 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 103258 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 19364 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 122622 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 10849 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 2603 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 13452 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 270704 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 1159 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 271863 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 373962 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2603 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20523 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 407937 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 373962 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2603 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20523 # number of overall misses
|
|
system.l2c.overall_misses::total 407937 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 3090000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 2769500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 5859500 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 569500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 892000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 1461500 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 13105172500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 2555486000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 15660658500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1419877000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 342190500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1762067500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 33554759000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 151782000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 33706541000 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1419877000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 46659931500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 342190500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 2707268000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 51129267000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1419877000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 46659931500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 342190500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 2707268000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 51129267000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 862671 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 862671 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 732220 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 732220 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 2743 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 570 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 3313 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 102 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 120 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 222 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 205296 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 117850 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 323146 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 490627 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 510717 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1001344 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 614835 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 496683 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1111518 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 490627 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 820131 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 510717 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 614533 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2436008 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 490627 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 820131 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 510717 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 614533 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2436008 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948596 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847368 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.931180 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.754902 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.783333 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.770270 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.502971 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.164311 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.379463 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.022113 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005097 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.013434 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.440287 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.244587 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.022113 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.455978 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.005097 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.033396 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.167461 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.022113 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.455978 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.005097 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.033396 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.167461 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1187.548040 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5733.954451 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 1899.351702 # average UpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7396.103896 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9489.361702 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::total 8546.783626 # average SCUpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126916.776424 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131970.977071 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 127714.916573 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130876.301963 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131460.046101 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 130989.258103 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123953.687422 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130959.447800 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 123983.554217 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 125336.184264 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 125336.184264 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 79536 # number of writebacks
|
|
system.l2c.writebacks::total 79536 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 2602 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 3085 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 77 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 103258 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 19364 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 122622 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10849 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2592 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 13441 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 270704 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1159 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 271863 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 10849 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 373962 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2592 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 20523 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 407926 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 10849 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 373962 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2592 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 20523 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 407926 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 12421 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 19620 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186370500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34557500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 220928000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5513500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6719500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 12233000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 12072592500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2361846000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 14434438500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1311387000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 314915500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1626302500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30847719000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 140192000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 30987911000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 1311387000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 42920311500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 314915500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 2502038000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 47048652000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 1311387000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 42920311500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 314915500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 2502038000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 47048652000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1012133000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 490208000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1502341000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1745847000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 944283500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 2690130500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2757980000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1434491500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4192471500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948596 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847368 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.931180 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.754902 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.783333 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502971 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.164311 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.379463 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013423 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.440287 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244587 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.167457 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.167457 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591 # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307 # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675 # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691 # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 7199 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 292680 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 12421 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 12421 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 121058 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 261934 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4921 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 1238 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3449 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 122558 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 122429 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39240 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1166399 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1205639 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124831 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 124831 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1330470 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68786 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31168512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31237298 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2658368 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 33895666 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 3262 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 858545 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 858545 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 858545 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 36672500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1323961648 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2184136804 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 69798217 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.snoop_filter.tot_requests 4935792 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2467069 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 374533 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1179 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2152619 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 12421 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 12421 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 983748 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 732220 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 760785 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 4956 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 1289 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 6245 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 324079 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 324079 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1001367 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1144069 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1377223 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478366 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1357708 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1834010 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7047307 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56740736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 76009449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 54207360 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 71099081 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 258056626 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 461903 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 2920905 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.337667 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 2538432 86.91% 86.91% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 382238 13.09% 99.99% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2920905 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 4346798496 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 736191563 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1248608962 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 767009132 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 969915969 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
---------- End Simulation Statistics ----------
|