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gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

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X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
sim_seconds 5.200396 # Number of seconds simulated
sim_ticks 5200396150000 # Number of ticks simulated
final_tick 5200396150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
host_inst_rate 778841 # Simulator instruction rate (inst/s)
host_op_rate 1501355 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 31560622919 # Simulator tick rate (ticks/s)
host_mem_usage 627712 # Number of bytes of host memory used
host_seconds 164.77 # Real time elapsed on the host
sim_insts 128333376 # Number of instructions simulated
sim_ops 247385531 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::pc.south_bridge.ide 2886336 # Number of bytes read from this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bytes_read::cpu.inst 825216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8967296 # Number of bytes read from this memory
system.physmem.bytes_read::total 12679232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 825216 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 825216 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8106560 # Number of bytes written to this memory
system.physmem.bytes_written::total 8106560 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 45099 # Number of read requests responded to by this memory
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.num_reads::cpu.inst 12894 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 140114 # Number of read requests responded to by this memory
system.physmem.num_reads::total 198113 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 126665 # Number of write requests responded to by this memory
system.physmem.num_writes::total 126665 # Number of write requests responded to by this memory
system.physmem.bw_read::pc.south_bridge.ide 555022 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_read::cpu.inst 158683 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1724349 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2438128 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 158683 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 158683 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1558835 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1558835 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1558835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 555022 # Total bandwidth to/from this memory (bytes/s)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.bw_total::cpu.inst 158683 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1724349 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3996963 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198113 # Number of read requests accepted
system.physmem.writeReqs 126665 # Number of write requests accepted
system.physmem.readBursts 198113 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 126665 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
system.physmem.bytesWritten 8105536 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12679232 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8106560 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.neitherReadNorWriteReqs 1623 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12177 # Per bank write bursts
system.physmem.perBankRdBursts::1 12548 # Per bank write bursts
system.physmem.perBankRdBursts::2 13053 # Per bank write bursts
system.physmem.perBankRdBursts::3 12620 # Per bank write bursts
system.physmem.perBankRdBursts::4 12592 # Per bank write bursts
system.physmem.perBankRdBursts::5 12288 # Per bank write bursts
system.physmem.perBankRdBursts::6 11961 # Per bank write bursts
system.physmem.perBankRdBursts::7 12236 # Per bank write bursts
system.physmem.perBankRdBursts::8 11972 # Per bank write bursts
system.physmem.perBankRdBursts::9 11957 # Per bank write bursts
system.physmem.perBankRdBursts::10 12338 # Per bank write bursts
system.physmem.perBankRdBursts::11 12177 # Per bank write bursts
system.physmem.perBankRdBursts::12 12807 # Per bank write bursts
system.physmem.perBankRdBursts::13 12813 # Per bank write bursts
system.physmem.perBankRdBursts::14 12433 # Per bank write bursts
system.physmem.perBankRdBursts::15 12012 # Per bank write bursts
system.physmem.perBankWrBursts::0 7757 # Per bank write bursts
system.physmem.perBankWrBursts::1 8145 # Per bank write bursts
system.physmem.perBankWrBursts::2 8603 # Per bank write bursts
system.physmem.perBankWrBursts::3 8164 # Per bank write bursts
system.physmem.perBankWrBursts::4 8201 # Per bank write bursts
system.physmem.perBankWrBursts::5 7973 # Per bank write bursts
system.physmem.perBankWrBursts::6 7511 # Per bank write bursts
system.physmem.perBankWrBursts::7 7789 # Per bank write bursts
system.physmem.perBankWrBursts::8 7356 # Per bank write bursts
system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
system.physmem.perBankWrBursts::10 7874 # Per bank write bursts
system.physmem.perBankWrBursts::11 7684 # Per bank write bursts
system.physmem.perBankWrBursts::12 8313 # Per bank write bursts
system.physmem.perBankWrBursts::13 8300 # Per bank write bursts
system.physmem.perBankWrBursts::14 7968 # Per bank write bursts
system.physmem.perBankWrBursts::15 7488 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 5200396086500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.readPktSize::6 198113 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.writePktSize::6 126665 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 153621 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2695 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 4322 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 4544 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 4208 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 3990 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3280 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2652 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 2195 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1870 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1376 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1254 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 1028 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 1144 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 834 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 668 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 612 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::15 1639 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1812 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5075 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5183 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5335 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5509 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5985 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6946 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6999 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7260 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 7801 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 7668 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7468 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 2018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2636 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2551 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::38 2242 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::39 1885 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1536 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 897 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 721 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 59433 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 349.577642 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 202.117781 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 357.932182 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 20505 34.50% 34.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 13774 23.18% 57.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5765 9.70% 67.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3461 5.82% 73.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2240 3.77% 76.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1591 2.68% 79.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1115 1.88% 81.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 921 1.55% 83.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10061 16.93% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 59433 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6976 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.380447 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 572.057676 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6975 99.99% 99.99% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.rdPerTurnAround::total 6976 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6976 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.154960 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.623474 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 5.583584 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-17 4785 68.59% 68.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18-19 1454 20.84% 89.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-21 33 0.47% 89.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22-23 125 1.79% 91.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-25 57 0.82% 92.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26-27 47 0.67% 93.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-29 75 1.08% 94.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30-31 59 0.85% 95.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-33 41 0.59% 95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::34-35 19 0.27% 95.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-37 30 0.43% 96.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::38-39 56 0.80% 97.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-41 145 2.08% 99.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42-43 17 0.24% 99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-45 4 0.06% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::46-47 11 0.16% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-49 3 0.04% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::50-51 3 0.04% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-53 2 0.03% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::54-55 2 0.03% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-57 1 0.01% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::58-59 1 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-61 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::62-63 3 0.04% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-69 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6976 # Writes before turning the bus around for reads
system.physmem.totQLat 5514862500 # Total ticks spent queuing
system.physmem.totMemAccLat 9227062500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
system.physmem.avgQLat 27855.09 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgMemAccLat 46605.09 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
system.physmem.readRowHits 166366 # Number of row buffer hits during reads
system.physmem.writeRowHits 98833 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
system.physmem.avgGap 16012156.26 # Average gap between requests
system.physmem.pageHitRate 81.69 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 4979189621500 # Time in different power states
system.physmem.memoryStateTime::REF 173652440000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 47553973500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 4356964 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 623381 # Transaction distribution
system.membus.trans_dist::ReadResp 623381 # Transaction distribution
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.trans_dist::WriteReq 13777 # Transaction distribution
system.membus.trans_dist::WriteResp 13777 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.trans_dist::Writeback 126665 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1641 # Transaction distribution
system.membus.trans_dist::ReadExReq 159285 # Transaction distribution
system.membus.trans_dist::ReadExResp 159285 # Transaction distribution
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.trans_dist::MessageReq 1656 # Transaction distribution
system.membus.trans_dist::MessageResp 1656 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390454 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139322 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 139322 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1723534 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14912768 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16579445 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5873024 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 5873024 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 22459093 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 22459093 # Total data (bytes)
system.membus.snoop_data_through_bus 198848 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 256797000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.reqLayer3.occupancy 1351243000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer2.occupancy 2609486505 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.respLayer4.occupancy 429020250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.replacements 47501 # number of replacements
system.iocache.tags.tagsinuse 0.128246 # Cycle average of tags in use
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.warmup_cycle 5049779388000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128246 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008015 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.008015 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.tags.tag_accesses 428004 # Number of tag accesses
system.iocache.tags.data_accesses 428004 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses
system.iocache.ReadReq_misses::total 836 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses
system.iocache.demand_misses::total 47556 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses
system.iocache.overall_misses::total 47556 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140309686 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 140309686 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12229393602 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 12229393602 # number of WriteReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 12369703288 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 12369703288 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 12369703288 # number of overall miss cycles
system.iocache.overall_miss_latency::total 12369703288 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 167834.552632 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 261759.280865 # average WriteReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 260108.152242 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 260108.152242 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 207651 # number of cycles access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.blocked::no_mshrs 17427 # number of cycles access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 11.915476 # average number of cycles each access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96812686 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 96812686 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9797946102 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 9797946102 # number of WriteReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9894758788 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 9894758788 # number of overall MSHR miss cycles
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115 # average WriteReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.throughput 630779 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 230141 # Transaction distribution
system.iobus.trans_dist::ReadResp 230141 # Transaction distribution
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.pkt_count::total 578752 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.tot_pkt_size::total 3280300 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 3280300 # Total data (bytes)
system.iobus.reqLayer0.occupancy 3954900 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.reqLayer18.occupancy 424640038 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.iobus.respLayer1.occupancy 53686750 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.numCycles 10400792300 # number of cpu cycles simulated
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.committedInsts 128333376 # Number of instructions committed
system.cpu.committedOps 247385531 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 231978349 # Number of integer alu accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_func_calls 2299991 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23168967 # number of instructions that are conditional controls
system.cpu.num_int_insts 231978349 # number of integer instructions
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_int_register_reads 434511356 # number of times the integer registers were read
system.cpu.num_int_register_writes 197852349 # number of times the integer registers were written
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.num_cc_register_reads 132811982 # number of times the CC registers were read
system.cpu.num_cc_register_writes 95533715 # number of times the CC registers were written
system.cpu.num_mem_refs 22244872 # number of memory refs
system.cpu.num_load_insts 13879055 # Number of load instructions
system.cpu.num_store_insts 8365817 # Number of store instructions
system.cpu.num_idle_cycles 9793794512.998117 # Number of idle cycles
system.cpu.num_busy_cycles 606997787.001883 # Number of busy cycles
system.cpu.not_idle_fraction 0.058361 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.941639 # Percentage of idle cycles
system.cpu.Branches 26307123 # Number of branches fetched
system.cpu.op_class::No_OpClass 174810 0.07% 0.07% # Class of executed instruction
system.cpu.op_class::IntAlu 224704553 90.83% 90.90% # Class of executed instruction
system.cpu.op_class::IntMult 139755 0.06% 90.96% # Class of executed instruction
system.cpu.op_class::IntDiv 123089 0.05% 91.01% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction
system.cpu.op_class::MemRead 13879055 5.61% 96.62% # Class of executed instruction
system.cpu.op_class::MemWrite 8365817 3.38% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 247387079 # Class of executed instruction
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.replacements 791030 # number of replacements
system.cpu.icache.tags.tagsinuse 510.352813 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 144579864 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 791542 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 182.655960 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 161437750250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.352813 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996783 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.996783 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.tag_accesses 146162962 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146162962 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 144579864 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 144579864 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 144579864 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 144579864 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 144579864 # number of overall hits
system.cpu.icache.overall_hits::total 144579864 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 791549 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 791549 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 791549 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 791549 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 791549 # number of overall misses
system.cpu.icache.overall_misses::total 791549 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108553755 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11108553755 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11108553755 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11108553755 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11108553755 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11108553755 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 145371413 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 145371413 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 145371413 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 145371413 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 145371413 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 145371413 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005445 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005445 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005445 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.005445 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.005445 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.005445 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14033.943262 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14033.943262 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791549 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 791549 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 791549 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 791549 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 791549 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 791549 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9520697745 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 9520697745 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9520697745 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 9520697745 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9520697745 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 9520697745 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005445 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.005445 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.005445 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.tags.replacements 3407 # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse 3.079507 # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs 7935 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3418 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.321533 # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.079507 # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192469 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.192469 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses 28718 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 28718 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7937 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7937 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7939 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7939 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7939 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7939 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4280 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4280 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4280 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4280 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4280 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4280 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42457500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42457500 # number of ReadReq miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42457500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.demand_miss_latency::total 42457500 # number of demand (read+write) miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42457500 # number of overall miss cycles
system.cpu.itb_walker_cache.overall_miss_latency::total 42457500 # number of overall miss cycles
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.350332 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.350332 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.350274 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.350274 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.350274 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.350274 # miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9919.976636 # average ReadReq miss latency
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9919.976636 # average ReadReq miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9919.976636 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9919.976636 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 704 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 704 # number of writebacks
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4280 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4280 # number of ReadReq MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4280 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.demand_mshr_misses::total 4280 # number of demand (read+write) MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4280 # number of overall MSHR misses
system.cpu.itb_walker_cache.overall_mshr_misses::total 4280 # number of overall MSHR misses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33895500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33895500 # number of ReadReq MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33895500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33895500 # number of demand (read+write) MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33895500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33895500 # number of overall MSHR miss cycles
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.350332 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.350332 # mshr miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.350274 # mshr miss rate for demand accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.350274 # mshr miss rate for overall accesses
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7919.509346 # average ReadReq mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb_walker_cache.tags.replacements 7502 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.061351 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 13282 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 7516 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.767163 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061351 # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316334 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316334 # Average percentage of cache occupancy
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb_walker_cache.tags.tag_accesses 52668 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 52668 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13284 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 13284 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13284 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 13284 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13284 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 13284 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8700 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8700 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8700 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8700 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8700 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8700 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92345000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92345000 # number of ReadReq miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92345000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.demand_miss_latency::total 92345000 # number of demand (read+write) miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92345000 # number of overall miss cycles
system.cpu.dtb_walker_cache.overall_miss_latency::total 92345000 # number of overall miss cycles
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21984 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21984 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21984 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21984 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21984 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21984 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395742 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395742 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395742 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395742 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395742 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395742 # miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816 # average ReadReq miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816 # average ReadReq miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 3054 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 3054 # number of writebacks
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8700 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8700 # number of ReadReq MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8700 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8700 # number of demand (read+write) MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8700 # number of overall MSHR misses
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8700 # number of overall MSHR misses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74944500 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74944500 # number of ReadReq MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74944500 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74944500 # number of demand (read+write) MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74944500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74944500 # number of overall MSHR miss cycles
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395742 # mshr miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395742 # mshr miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395742 # mshr miss rate for overall accesses
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8614.310345 # average ReadReq mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.replacements 1620643 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.997078 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 20036158 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1621155 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.359187 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997078 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.tags.tag_accesses 88250512 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88250512 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 11993410 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 11993410 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8040535 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8040535 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 20033945 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20033945 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20033945 # number of overall hits
system.cpu.dcache.overall_hits::total 20033945 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1308416 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308416 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 314973 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 314973 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1623389 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1623389 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1623389 # number of overall misses
system.cpu.dcache.overall_misses::total 1623389 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18840132304 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 18840132304 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10814294936 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10814294936 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 29654427240 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 29654427240 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 29654427240 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 29654427240 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13301826 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13301826 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8355508 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8355508 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21657334 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21657334 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21657334 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21657334 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098364 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.098364 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037696 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037696 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.074958 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.074958 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074958 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074958 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 18266.987912 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18266.987912 # average overall miss latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.writebacks::writebacks 1537613 # number of writebacks
system.cpu.dcache.writebacks::total 1537613 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308416 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1308416 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314973 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 314973 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1623389 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1623389 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1623389 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1623389 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16214330696 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16214330696 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10132215064 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10132215064 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26346545760 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26346545760 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26346545760 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 26346545760 # number of overall MSHR miss cycles
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537738000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537738000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752410500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752410500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098364 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098364 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037696 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037696 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.074958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074958 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.throughput 49146383 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2695227 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2694701 # Transaction distribution
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 1541371 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2213 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 359480 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 312780 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583085 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973901 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7764 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18139 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7582889 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50658304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203802165 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 222976 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 604096 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 255287541 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 255266421 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 314240 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3830515500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 1189702505 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 3051756740 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 6421000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 13050250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.replacements 86651 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64733.611120 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3487942 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 151340 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 23.047060 # Average number of references to valid blocks.
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027833 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141473 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3434.458363 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.766140 # Average percentage of cache occupancy
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052406 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169208 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.987757 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64689 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2880 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4787 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56896 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987076 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 32180689 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 32180689 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6384 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2775 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 778641 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1279470 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2067270 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1541371 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1541371 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 305 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 199944 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 199944 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6384 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 2775 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 778641 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1479414 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2267214 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6384 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 2775 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 778641 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1479414 # number of overall hits
system.cpu.l2cache.overall_hits::total 2267214 # number of overall hits
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 12895 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 28198 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 41099 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 112812 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 112812 # number of ReadExReq misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 12895 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 141010 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 153911 # number of demand (read+write) misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 12895 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 141010 # number of overall misses
system.cpu.l2cache.overall_misses::total 153911 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 942725495 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2110465196 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 3053644941 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16120870 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 16120870 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7781341940 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 7781341940 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 942725495 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9891807136 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10834986881 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 942725495 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9891807136 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10834986881 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6385 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2780 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791536 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307668 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2108369 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1541371 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1541371 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1699 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1699 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 312756 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 312756 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6385 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2780 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 791536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1620424 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2421125 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6385 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 791536 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1620424 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2421125 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001799 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016291 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021564 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.019493 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820483 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820483 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360703 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.360703 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001799 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016291 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087020 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.063570 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001799 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016291 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087020 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.063570 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73107.832105 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74844.499468 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 74299.738217 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11564.469154 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11564.469154 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68976.189944 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68976.189944 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70397.742078 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70397.742078 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.writebacks::writebacks 79998 # number of writebacks
system.cpu.l2cache.writebacks::total 79998 # number of writebacks
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12895 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28198 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 41099 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1394 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1394 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112812 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 112812 # number of ReadExReq MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12895 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 141010 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 153911 # number of demand (read+write) MSHR misses
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12895 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141010 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 153911 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 781175005 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1757280304 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2538833059 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14868876 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14868876 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6370597060 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6370597060 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 781175005 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8127877364 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8909430119 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 781175005 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8127877364 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8909430119 # number of overall MSHR miss cycles
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371075000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371075000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026944000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026944000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021564 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019493 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820483 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820483 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360703 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360703 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063570 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063570 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
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