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gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 0.057719 # Number of seconds simulated
sim_ticks 57719377000 # Number of ticks simulated
final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 125223 # Simulator instruction rate (inst/s)
host_op_rate 125847 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 79786059 # Simulator tick rate (ticks/s)
host_mem_usage 443544 # Number of bytes of host memory used
host_seconds 723.43 # Real time elapsed on the host
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
sim_insts 90589798 # Number of instructions simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
sim_ops 91041029 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory
system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory
system.physmem.bytes_written::total 19776 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory
system.physmem.num_writes::total 309 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15872 # Number of read requests accepted
system.physmem.writeReqs 309 # Number of write requests accepted
system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue
system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 999 # Per bank write bursts
system.physmem.perBankRdBursts::1 876 # Per bank write bursts
system.physmem.perBankRdBursts::2 956 # Per bank write bursts
system.physmem.perBankRdBursts::3 1023 # Per bank write bursts
system.physmem.perBankRdBursts::4 1064 # Per bank write bursts
system.physmem.perBankRdBursts::5 1127 # Per bank write bursts
system.physmem.perBankRdBursts::6 1115 # Per bank write bursts
system.physmem.perBankRdBursts::7 1101 # Per bank write bursts
system.physmem.perBankRdBursts::8 1033 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::9 962 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::10 937 # Per bank write bursts
system.physmem.perBankRdBursts::11 899 # Per bank write bursts
system.physmem.perBankRdBursts::12 910 # Per bank write bursts
system.physmem.perBankRdBursts::13 886 # Per bank write bursts
system.physmem.perBankRdBursts::14 919 # Per bank write bursts
system.physmem.perBankRdBursts::15 912 # Per bank write bursts
system.physmem.perBankWrBursts::0 23 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::2 4 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 9 # Per bank write bursts
system.physmem.perBankWrBursts::5 29 # Per bank write bursts
system.physmem.perBankWrBursts::6 62 # Per bank write bursts
system.physmem.perBankWrBursts::7 30 # Per bank write bursts
system.physmem.perBankWrBursts::8 15 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankWrBursts::10 10 # Per bank write bursts
system.physmem.perBankWrBursts::11 1 # Per bank write bursts
system.physmem.perBankWrBursts::12 9 # Per bank write bursts
system.physmem.perBankWrBursts::13 27 # Per bank write bursts
system.physmem.perBankWrBursts::14 48 # Per bank write bursts
system.physmem.perBankWrBursts::15 21 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 57719226000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 15872 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writePktSize::6 309 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads
system.physmem.totQLat 179464908 # Total ticks spent queuing
system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing
system.physmem.readRowHits 14166 # Number of row buffer hits during reads
system.physmem.writeRowHits 92 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes
system.physmem.avgGap 3567098.82 # Average gap between requests
system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.607894 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states
system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.433104 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states
system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 28271166 # Number of BP lookups
system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups
system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 115438755 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed
system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued
system.cpu.iq.rate 0.878644 # Inst issue rate
system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.exec_nop 12667 # number of nop insts executed
system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed
system.cpu.iew.exec_branches 20629236 # Number of branches executed
system.cpu.iew.exec_stores 4918943 # Number of stores executed
system.cpu.iew.exec_rate 0.867532 # Inst execution rate
system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back
system.cpu.iew.wb_producers 59706662 # num instructions producing a value
system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 27220755 # Number of memory references committed
system.cpu.commit.loads 22475911 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 3888 # Number of memory barriers committed
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.branches 18732304 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 56148 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntAlu 63822386 70.09% 70.09% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.rob.rob_reads 217026090 # The number of ROB reads
system.cpu.rob.rob_writes 219584249 # The number of ROB writes
system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads
system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 108125012 # number of integer regfile reads
system.cpu.int_regfile_writes 58739124 # number of integer regfile writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fp_regfile_writes 99 # number of floating regfile writes
system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads
system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes
system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.replacements 5486247 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits
system.cpu.dcache.overall_hits::total 18263472 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses
system.cpu.dcache.overall_misses::total 9970594 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks
system.cpu.dcache.writebacks::total 5460017 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.replacements 447 # number of replacements
system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses
system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits
system.cpu.icache.overall_hits::total 32314402 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1144 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1144 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1144 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1144 # number of overall misses
system.cpu.icache.overall_misses::total 1144 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 55657984 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 55657984 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 55657984 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 55657984 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 55657984 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 55657984 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 32315546 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 32315546 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 32315546 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 32315546 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 32315546 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 32315546 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48652.083916 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48652.083916 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48652.083916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48652.083916 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 17056 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 76.484305 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 44276742 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44276742 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 44276742 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44276742 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 44276742 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued 4494242 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 5296949 # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit 693182 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage 14114027 # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements 432 # number of replacements
system.cpu.l2cache.tags.tagsinuse 12071.451375 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10694296 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15874 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 673.698879 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 11103.819168 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 569.155490 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 195.974498 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 202.502218 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.677723 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034738 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.011961 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.012360 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.736783 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15202 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 5261084 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 5261295 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 5460017 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 5460017 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 224780 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 224780 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 5485864 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 5486075 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 5485864 # number of overall hits
system.cpu.l2cache.overall_hits::total 5486075 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 695 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 895 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1590 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 895 # number of overall misses
system.cpu.l2cache.overall_misses::total 1590 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42529250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21068985 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 63598235 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30498 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 30498 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34497490 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 34497490 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 42529250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 55566475 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 98095725 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 42529250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 55566475 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 98095725 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 906 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 5261470 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5262376 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 5460017 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 5460017 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 225289 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 225289 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 906 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 5486759 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 5487665 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 906 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 5486759 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 5487665 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.767108 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000073 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000205 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002259 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.002259 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767108 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.000290 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767108 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.000290 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61193.165468 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54582.862694 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 58832.779833 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15249 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15249 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67775.029470 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67775.029470 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 61695.424528 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 61695.424528 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks
system.cpu.l2cache.writebacks::total 309 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 168 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 168 # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 214 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 694 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20230 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 20230 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 682 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 682 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20230 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 22341 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 15531 # Transaction distribution
system.membus.trans_dist::ReadResp 15531 # Transaction distribution
system.membus.trans_dist::Writeback 309 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
system.membus.trans_dist::ReadExReq 341 # Transaction distribution
system.membus.trans_dist::ReadExResp 341 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 16183 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 16183 # Request fanout histogram
system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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