2006-05-16 23:36:50 +02:00
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/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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2006-06-01 01:26:56 +02:00
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*
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* Authors: Steve Reinhardt
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2006-05-16 23:36:50 +02:00
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*/
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2006-10-08 19:53:24 +02:00
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#include "arch/locked_mem.hh"
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2006-11-29 23:11:10 +01:00
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#include "arch/mmaped_ipr.hh"
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2006-05-16 23:36:50 +02:00
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#include "arch/utility.hh"
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2007-02-12 19:06:30 +01:00
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#include "base/bigint.hh"
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2009-09-23 17:34:21 +02:00
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#include "config/the_isa.hh"
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2006-05-16 23:36:50 +02:00
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#include "cpu/exetrace.hh"
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#include "cpu/simple/atomic.hh"
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2006-10-20 08:38:45 +02:00
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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2007-07-24 06:51:38 +02:00
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#include "params/AtomicSimpleCPU.hh"
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2006-07-13 02:22:07 +02:00
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#include "sim/system.hh"
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2006-05-16 23:36:50 +02:00
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using namespace std;
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using namespace TheISA;
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AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
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2008-10-09 13:58:24 +02:00
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: Event(CPU_Tick_Pri), cpu(c)
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2006-05-16 23:36:50 +02:00
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{
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}
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void
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AtomicSimpleCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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2008-02-06 22:32:40 +01:00
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AtomicSimpleCPU::TickEvent::description() const
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2006-05-16 23:36:50 +02:00
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{
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2007-07-01 02:45:58 +02:00
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return "AtomicSimpleCPU tick";
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2006-05-16 23:36:50 +02:00
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}
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2006-07-07 21:15:11 +02:00
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Port *
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2009-06-05 08:21:12 +02:00
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AtomicSimpleCPU::getPort(const string &if_name, int idx)
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2006-07-07 21:15:11 +02:00
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{
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if (if_name == "dcache_port")
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return &dcachePort;
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else if (if_name == "icache_port")
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return &icachePort;
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2007-08-09 00:43:12 +02:00
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else if (if_name == "physmem_port") {
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hasPhysMemPort = true;
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return &physmemPort;
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}
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2006-07-07 21:15:11 +02:00
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else
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panic("No Such Port\n");
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}
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2006-05-16 23:36:50 +02:00
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void
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AtomicSimpleCPU::init()
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{
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BaseCPU::init();
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#if FULL_SYSTEM
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2009-05-26 18:23:13 +02:00
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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2006-06-06 23:32:21 +02:00
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ThreadContext *tc = threadContexts[i];
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2006-05-16 23:36:50 +02:00
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// initialize CPU, including PC
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2008-11-03 03:57:07 +01:00
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TheISA::initCPU(tc, tc->contextId());
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2006-05-16 23:36:50 +02:00
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}
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#endif
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2007-08-09 00:43:12 +02:00
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if (hasPhysMemPort) {
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bool snoop = false;
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AddrRangeList pmAddrList;
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physmemPort.getPeerAddressRanges(pmAddrList, snoop);
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physMemAddr = *pmAddrList.begin();
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}
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2008-11-03 03:57:07 +01:00
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// Atomic doesn't do MT right now, so contextId == threadId
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2008-11-03 03:56:57 +01:00
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ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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2006-05-16 23:36:50 +02:00
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}
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bool
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2006-10-20 09:10:12 +02:00
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AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
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2006-05-16 23:36:50 +02:00
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{
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2006-10-09 02:30:42 +02:00
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panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
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2006-05-16 23:36:50 +02:00
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return true;
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}
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Tick
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2006-10-20 09:10:12 +02:00
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AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
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2006-05-16 23:36:50 +02:00
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{
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2006-10-18 00:50:19 +02:00
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//Snooping a coherence request, just return
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2006-11-14 01:12:45 +01:00
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return 0;
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2006-05-16 23:36:50 +02:00
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}
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void
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2006-10-20 09:10:12 +02:00
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AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
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2006-05-16 23:36:50 +02:00
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{
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2006-10-09 02:30:42 +02:00
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//No internal storage to update, just return
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return;
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2006-05-16 23:36:50 +02:00
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}
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void
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AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
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{
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2006-11-14 00:51:16 +01:00
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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2006-05-18 04:08:44 +02:00
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return;
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2006-11-14 00:51:16 +01:00
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}
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2006-05-18 04:08:44 +02:00
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2006-05-16 23:36:50 +02:00
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panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
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}
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2006-05-31 00:57:42 +02:00
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void
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2006-05-16 23:36:50 +02:00
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AtomicSimpleCPU::CpuPort::recvRetry()
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{
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panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
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}
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2007-03-09 16:06:09 +01:00
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void
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AtomicSimpleCPU::DcachePort::setPeer(Port *port)
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{
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Port::setPeer(port);
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#if FULL_SYSTEM
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// Update the ThreadContext's memory ports (Functional/Virtual
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// Ports)
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2008-07-01 16:24:16 +02:00
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cpu->tcBase()->connectMemPorts(cpu->tcBase());
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2007-03-09 16:06:09 +01:00
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#endif
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}
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2006-05-16 23:36:50 +02:00
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2008-08-11 21:22:16 +02:00
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AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
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2009-04-19 13:50:07 +02:00
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: BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
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2008-06-18 19:15:21 +02:00
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simulate_data_stalls(p->simulate_data_stalls),
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simulate_inst_stalls(p->simulate_inst_stalls),
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2007-08-09 00:43:12 +02:00
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icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
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physmemPort(name() + "-iport", this), hasPhysMemPort(false)
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2006-05-16 23:36:50 +02:00
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{
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_status = Idle;
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2006-11-14 00:51:16 +01:00
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icachePort.snoopRangeSent = false;
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dcachePort.snoopRangeSent = false;
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2006-05-16 23:36:50 +02:00
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}
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AtomicSimpleCPU::~AtomicSimpleCPU()
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{
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2009-11-18 22:55:58 +01:00
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if (tickEvent.scheduled()) {
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deschedule(tickEvent);
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}
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2006-05-16 23:36:50 +02:00
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}
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void
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AtomicSimpleCPU::serialize(ostream &os)
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{
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2006-07-12 23:11:57 +02:00
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SimObject::State so_state = SimObject::getState();
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SERIALIZE_ENUM(so_state);
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2009-04-19 13:50:07 +02:00
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SERIALIZE_SCALAR(locked);
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2006-10-06 07:29:50 +02:00
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BaseSimpleCPU::serialize(os);
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2006-05-16 23:36:50 +02:00
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nameOut(os, csprintf("%s.tickEvent", name()));
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tickEvent.serialize(os);
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}
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void
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AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
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{
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2006-07-12 23:11:57 +02:00
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SimObject::State so_state;
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UNSERIALIZE_ENUM(so_state);
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2009-04-19 13:50:07 +02:00
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UNSERIALIZE_SCALAR(locked);
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2006-07-12 23:11:57 +02:00
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BaseSimpleCPU::unserialize(cp, section);
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2006-10-06 07:29:50 +02:00
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tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
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2006-07-12 23:11:57 +02:00
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}
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void
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AtomicSimpleCPU::resume()
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{
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2007-11-08 16:46:41 +01:00
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if (_status == Idle || _status == SwitchedOut)
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return;
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2007-08-05 00:56:48 +02:00
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DPRINTF(SimpleCPU, "Resume\n");
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2007-11-08 16:46:41 +01:00
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assert(system->getMemoryMode() == Enums::atomic);
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changeState(SimObject::Running);
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if (thread->status() == ThreadContext::Active) {
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2008-10-09 13:58:24 +02:00
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if (!tickEvent.scheduled())
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schedule(tickEvent, nextCycle());
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2006-07-12 23:11:57 +02:00
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}
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2006-05-16 23:36:50 +02:00
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}
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void
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2006-06-30 01:45:24 +02:00
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AtomicSimpleCPU::switchOut()
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2006-05-16 23:36:50 +02:00
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{
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2008-07-01 16:24:09 +02:00
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assert(_status == Running || _status == Idle);
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2006-06-30 01:45:24 +02:00
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_status = SwitchedOut;
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2006-05-16 23:36:50 +02:00
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2006-06-30 01:45:24 +02:00
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tickEvent.squash();
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2006-05-16 23:36:50 +02:00
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}
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void
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AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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2007-03-09 16:06:09 +01:00
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BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
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2006-05-16 23:36:50 +02:00
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assert(!tickEvent.scheduled());
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2006-06-06 23:32:21 +02:00
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// if any of this CPU's ThreadContexts are active, mark the CPU as
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2006-05-16 23:36:50 +02:00
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// running and schedule its tick event.
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2009-05-26 18:23:13 +02:00
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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2006-06-06 23:32:21 +02:00
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ThreadContext *tc = threadContexts[i];
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if (tc->status() == ThreadContext::Active && _status != Running) {
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2006-05-16 23:36:50 +02:00
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_status = Running;
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2008-10-09 13:58:24 +02:00
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schedule(tickEvent, nextCycle());
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2006-05-16 23:36:50 +02:00
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break;
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}
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}
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2006-11-09 17:33:44 +01:00
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if (_status != Running) {
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_status = Idle;
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}
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2007-10-18 19:15:08 +02:00
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assert(threadContexts.size() == 1);
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2008-11-03 03:56:57 +01:00
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ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
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data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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2006-05-16 23:36:50 +02:00
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}
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void
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AtomicSimpleCPU::activateContext(int thread_num, int delay)
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{
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2007-08-05 00:56:48 +02:00
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DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
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2006-05-16 23:36:50 +02:00
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assert(thread_num == 0);
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2006-06-07 21:29:53 +02:00
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assert(thread);
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2006-05-16 23:36:50 +02:00
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assert(_status == Idle);
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assert(!tickEvent.scheduled());
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notIdleFraction++;
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2007-09-28 19:22:14 +02:00
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numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
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2006-11-29 22:07:55 +01:00
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2006-10-27 12:51:28 +02:00
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//Make sure ticks are still on multiples of cycles
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2008-10-09 13:58:24 +02:00
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schedule(tickEvent, nextCycle(curTick + ticks(delay)));
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2006-05-16 23:36:50 +02:00
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_status = Running;
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}
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void
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AtomicSimpleCPU::suspendContext(int thread_num)
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{
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2007-08-05 00:56:48 +02:00
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DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
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2006-05-16 23:36:50 +02:00
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assert(thread_num == 0);
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2006-06-07 21:29:53 +02:00
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assert(thread);
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2006-05-16 23:36:50 +02:00
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2009-04-19 11:23:29 +02:00
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if (_status == Idle)
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return;
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2006-05-16 23:36:50 +02:00
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assert(_status == Running);
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2006-05-18 04:08:44 +02:00
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// tick event may not be scheduled if this gets called from inside
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// an instruction's execution, e.g. "quiesce"
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if (tickEvent.scheduled())
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2008-10-09 13:58:24 +02:00
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deschedule(tickEvent);
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2006-05-16 23:36:50 +02:00
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notIdleFraction--;
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_status = Idle;
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}
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template <class T>
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Fault
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AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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{
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2006-10-08 19:43:31 +02:00
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// use the CPU's statically allocated read request and packet objects
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2007-06-30 19:16:18 +02:00
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Request *req = &data_read_req;
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
if (traceData) {
|
|
|
|
traceData->setAddr(addr);
|
|
|
|
}
|
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//The block size of our peer.
|
2009-06-05 08:21:12 +02:00
|
|
|
unsigned blockSize = dcachePort.peerBlockSize();
|
2007-08-27 05:27:11 +02:00
|
|
|
//The size of the data we're trying to read.
|
|
|
|
int dataSize = sizeof(T);
|
|
|
|
|
|
|
|
uint8_t * dataPtr = (uint8_t *)&data;
|
|
|
|
|
|
|
|
//The address of the second part of this access if it needs to be split
|
|
|
|
//across a cache line boundary.
|
|
|
|
Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
|
|
|
|
|
|
|
|
if(secondAddr > addr)
|
|
|
|
dataSize = secondAddr - addr;
|
|
|
|
|
|
|
|
dcache_latency = 0;
|
2006-10-08 19:53:24 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
while(1) {
|
|
|
|
req->setVirt(0, addr, dataSize, flags, thread->readPC());
|
2007-07-29 03:00:05 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
// translate to physical address
|
2009-04-09 07:21:27 +02:00
|
|
|
Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
|
2007-08-27 05:27:11 +02:00
|
|
|
|
|
|
|
// Now do the access.
|
2009-08-23 23:15:15 +02:00
|
|
|
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
|
2007-08-27 05:27:11 +02:00
|
|
|
Packet pkt = Packet(req,
|
2009-04-20 06:44:15 +02:00
|
|
|
req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
|
2007-08-27 05:27:11 +02:00
|
|
|
Packet::Broadcast);
|
|
|
|
pkt.dataStatic(dataPtr);
|
|
|
|
|
|
|
|
if (req->isMmapedIpr())
|
|
|
|
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
|
|
|
|
else {
|
|
|
|
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
|
|
|
|
dcache_latency += physmemPort.sendAtomic(&pkt);
|
|
|
|
else
|
|
|
|
dcache_latency += dcachePort.sendAtomic(&pkt);
|
|
|
|
}
|
|
|
|
dcache_access = true;
|
2007-08-27 06:45:40 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
assert(!pkt.isError());
|
|
|
|
|
2009-04-20 06:44:15 +02:00
|
|
|
if (req->isLLSC()) {
|
2007-08-27 05:27:11 +02:00
|
|
|
TheISA::handleLockedRead(thread, req);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// This will need a new way to tell if it has a dcache attached.
|
|
|
|
if (req->isUncacheable())
|
|
|
|
recordEvent("Uncached Read");
|
|
|
|
|
|
|
|
//If there's a fault, return it
|
2009-11-11 06:10:18 +01:00
|
|
|
if (fault != NoFault) {
|
|
|
|
if (req->isPrefetch()) {
|
|
|
|
return NoFault;
|
|
|
|
} else {
|
|
|
|
return fault;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//If we don't need to access a second cache line, stop now.
|
|
|
|
if (secondAddr <= addr)
|
|
|
|
{
|
|
|
|
data = gtoh(data);
|
2008-06-12 06:35:50 +02:00
|
|
|
if (traceData) {
|
|
|
|
traceData->setData(data);
|
|
|
|
}
|
2009-04-19 13:50:07 +02:00
|
|
|
if (req->isLocked() && fault == NoFault) {
|
|
|
|
assert(!locked);
|
|
|
|
locked = true;
|
|
|
|
}
|
2007-08-27 05:27:11 +02:00
|
|
|
return fault;
|
2006-10-08 19:53:24 +02:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
/*
|
|
|
|
* Set up for accessing the second cache line.
|
|
|
|
*/
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//Move the pointer we're reading into to the correct location.
|
|
|
|
dataPtr += dataSize;
|
|
|
|
//Adjust the size to get the remaining bytes.
|
|
|
|
dataSize = addr + sizeof(T) - secondAddr;
|
|
|
|
//And access the right address.
|
|
|
|
addr = secondAddr;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
2007-03-03 04:34:51 +01:00
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
|
|
|
|
|
2007-02-12 19:06:30 +01:00
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
|
|
|
|
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(addr, *(uint64_t*)&data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(addr, *(uint32_t*)&data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
|
|
|
|
{
|
|
|
|
return read(addr, (uint32_t&)data, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
template <class T>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
2006-10-08 19:43:31 +02:00
|
|
|
// use the CPU's statically allocated write request and packet objects
|
2007-06-30 19:16:18 +02:00
|
|
|
Request *req = &data_write_req;
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
if (traceData) {
|
|
|
|
traceData->setAddr(addr);
|
|
|
|
}
|
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//The block size of our peer.
|
2009-06-05 08:21:12 +02:00
|
|
|
unsigned blockSize = dcachePort.peerBlockSize();
|
2007-08-27 05:27:11 +02:00
|
|
|
//The size of the data we're trying to read.
|
|
|
|
int dataSize = sizeof(T);
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
uint8_t * dataPtr = (uint8_t *)&data;
|
2007-07-01 05:35:42 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//The address of the second part of this access if it needs to be split
|
|
|
|
//across a cache line boundary.
|
|
|
|
Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
|
|
|
|
|
|
|
|
if(secondAddr > addr)
|
|
|
|
dataSize = secondAddr - addr;
|
|
|
|
|
|
|
|
dcache_latency = 0;
|
|
|
|
|
|
|
|
while(1) {
|
|
|
|
req->setVirt(0, addr, dataSize, flags, thread->readPC());
|
|
|
|
|
|
|
|
// translate to physical address
|
2009-04-09 07:21:27 +02:00
|
|
|
Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
|
2007-08-27 05:27:11 +02:00
|
|
|
|
|
|
|
// Now do the access.
|
|
|
|
if (fault == NoFault) {
|
|
|
|
MemCmd cmd = MemCmd::WriteReq; // default
|
|
|
|
bool do_access = true; // flag to suppress cache access
|
|
|
|
|
2009-04-20 06:44:15 +02:00
|
|
|
if (req->isLLSC()) {
|
2007-08-27 05:27:11 +02:00
|
|
|
cmd = MemCmd::StoreCondReq;
|
|
|
|
do_access = TheISA::handleLockedWrite(thread, req);
|
|
|
|
} else if (req->isSwap()) {
|
|
|
|
cmd = MemCmd::SwapReq;
|
|
|
|
if (req->isCondSwap()) {
|
|
|
|
assert(res);
|
|
|
|
req->setExtraData(*res);
|
|
|
|
}
|
2006-11-29 23:11:10 +01:00
|
|
|
}
|
2007-07-01 05:35:42 +02:00
|
|
|
|
2009-08-23 23:15:15 +02:00
|
|
|
if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
|
2007-08-27 05:27:11 +02:00
|
|
|
Packet pkt = Packet(req, cmd, Packet::Broadcast);
|
|
|
|
pkt.dataStatic(dataPtr);
|
|
|
|
|
|
|
|
if (req->isMmapedIpr()) {
|
|
|
|
dcache_latency +=
|
|
|
|
TheISA::handleIprWrite(thread->getTC(), &pkt);
|
|
|
|
} else {
|
|
|
|
//XXX This needs to be outside of the loop in order to
|
|
|
|
//work properly for cache line boundary crossing
|
|
|
|
//accesses in transendian simulations.
|
|
|
|
data = htog(data);
|
|
|
|
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
|
|
|
|
dcache_latency += physmemPort.sendAtomic(&pkt);
|
|
|
|
else
|
|
|
|
dcache_latency += dcachePort.sendAtomic(&pkt);
|
|
|
|
}
|
|
|
|
dcache_access = true;
|
|
|
|
assert(!pkt.isError());
|
|
|
|
|
|
|
|
if (req->isSwap()) {
|
|
|
|
assert(res);
|
|
|
|
*res = pkt.get<T>();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (res && !req->isSwap()) {
|
|
|
|
*res = req->getExtraData();
|
2007-07-01 05:35:42 +02:00
|
|
|
}
|
2006-10-08 19:53:24 +02:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
// This will need a new way to tell if it's hooked up to a cache or not.
|
|
|
|
if (req->isUncacheable())
|
|
|
|
recordEvent("Uncached Write");
|
|
|
|
|
|
|
|
//If there's a fault or we don't need to access a second cache line,
|
|
|
|
//stop now.
|
|
|
|
if (fault != NoFault || secondAddr <= addr)
|
|
|
|
{
|
|
|
|
// If the write needs to have a fault on the access, consider
|
|
|
|
// calling changeStatus() and changing it to "bad addr write"
|
|
|
|
// or something.
|
2008-06-12 06:35:50 +02:00
|
|
|
if (traceData) {
|
2009-03-12 07:05:24 +01:00
|
|
|
traceData->setData(gtoh(data));
|
2008-06-12 06:35:50 +02:00
|
|
|
}
|
2009-04-19 13:50:07 +02:00
|
|
|
if (req->isLocked() && fault == NoFault) {
|
|
|
|
assert(locked);
|
|
|
|
locked = false;
|
|
|
|
}
|
2009-11-11 06:10:18 +01:00
|
|
|
if (fault != NoFault && req->isPrefetch()) {
|
|
|
|
return NoFault;
|
|
|
|
} else {
|
|
|
|
return fault;
|
|
|
|
}
|
2006-05-19 04:54:19 +02:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
/*
|
|
|
|
* Set up for accessing the second cache line.
|
|
|
|
*/
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2007-08-27 05:27:11 +02:00
|
|
|
//Move the pointer we're reading into to the correct location.
|
|
|
|
dataPtr += dataSize;
|
|
|
|
//Adjust the size to get the remaining bytes.
|
|
|
|
dataSize = addr + sizeof(T) - secondAddr;
|
|
|
|
//And access the right address.
|
|
|
|
addr = secondAddr;
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
2007-03-11 23:12:33 +01:00
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(Twin32_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(Twin64_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(uint64_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(uint32_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(uint16_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
template
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(uint8_t data, Addr addr,
|
|
|
|
unsigned flags, uint64_t *res);
|
|
|
|
|
|
|
|
#endif //DOXYGEN_SHOULD_SKIP_THIS
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write(*(uint64_t*)&data, addr, flags, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write(*(uint32_t*)&data, addr, flags, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
template<>
|
|
|
|
Fault
|
|
|
|
AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
|
|
|
|
{
|
|
|
|
return write((uint32_t)data, addr, flags, res);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
AtomicSimpleCPU::tick()
|
|
|
|
{
|
2007-08-05 00:56:48 +02:00
|
|
|
DPRINTF(SimpleCPU, "Tick\n");
|
|
|
|
|
2008-06-18 19:15:21 +02:00
|
|
|
Tick latency = 0;
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2009-04-19 13:50:07 +02:00
|
|
|
for (int i = 0; i < width || locked; ++i) {
|
2006-05-16 23:36:50 +02:00
|
|
|
numCycles++;
|
|
|
|
|
2006-10-23 08:39:02 +02:00
|
|
|
if (!curStaticInst || !curStaticInst->isDelayedCommit())
|
|
|
|
checkForInterrupts();
|
2006-05-18 04:08:44 +02:00
|
|
|
|
2008-02-14 22:14:35 +01:00
|
|
|
checkPcEventQueue();
|
|
|
|
|
2008-10-13 04:32:06 +02:00
|
|
|
Fault fault = NoFault;
|
|
|
|
|
|
|
|
bool fromRom = isRomMicroPC(thread->readMicroPC());
|
2009-02-25 19:18:36 +01:00
|
|
|
if (!fromRom && !curMacroStaticInst) {
|
2009-02-25 19:16:15 +01:00
|
|
|
setupFetchRequest(&ifetch_req);
|
2009-04-09 07:21:27 +02:00
|
|
|
fault = thread->itb->translateAtomic(&ifetch_req, tc,
|
|
|
|
BaseTLB::Execute);
|
2009-02-25 19:16:15 +01:00
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
if (fault == NoFault) {
|
2007-03-15 03:47:42 +01:00
|
|
|
Tick icache_latency = 0;
|
|
|
|
bool icache_access = false;
|
|
|
|
dcache_access = false; // assume no dcache access
|
2006-05-31 04:30:42 +02:00
|
|
|
|
2009-02-25 19:18:36 +01:00
|
|
|
if (!fromRom && !curMacroStaticInst) {
|
2008-10-13 08:52:02 +02:00
|
|
|
// This is commented out because the predecoder would act like
|
|
|
|
// a tiny cache otherwise. It wouldn't be flushed when needed
|
|
|
|
// like the I cache. It should be flushed, and when that works
|
|
|
|
// this code should be uncommented.
|
2008-10-13 04:32:06 +02:00
|
|
|
//Fetch more instruction memory if necessary
|
|
|
|
//if(predecoder.needMoreBytes())
|
|
|
|
//{
|
|
|
|
icache_access = true;
|
|
|
|
Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
|
|
|
|
Packet::Broadcast);
|
|
|
|
ifetch_pkt.dataStatic(&inst);
|
|
|
|
|
|
|
|
if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
|
|
|
|
icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
|
|
|
|
else
|
|
|
|
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
|
2007-08-09 00:43:12 +02:00
|
|
|
|
2008-10-13 04:32:06 +02:00
|
|
|
assert(!ifetch_pkt.isError());
|
2007-08-09 00:43:12 +02:00
|
|
|
|
2008-10-13 04:32:06 +02:00
|
|
|
// ifetch_req is initialized to read the instruction directly
|
|
|
|
// into the CPU object's inst field.
|
|
|
|
//}
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
|
|
|
preExecute();
|
2006-12-04 06:54:40 +01:00
|
|
|
|
2007-08-27 05:29:09 +02:00
|
|
|
if (curStaticInst) {
|
2007-03-15 03:47:42 +01:00
|
|
|
fault = curStaticInst->execute(this, traceData);
|
2007-08-27 05:25:42 +02:00
|
|
|
|
|
|
|
// keep an instruction count
|
|
|
|
if (fault == NoFault)
|
|
|
|
countInst();
|
2007-08-27 05:29:09 +02:00
|
|
|
else if (traceData) {
|
|
|
|
// If there was a fault, we should trace this instruction.
|
|
|
|
delete traceData;
|
|
|
|
traceData = NULL;
|
|
|
|
}
|
2007-08-27 05:25:42 +02:00
|
|
|
|
2007-03-15 03:47:42 +01:00
|
|
|
postExecute();
|
|
|
|
}
|
2006-05-16 23:36:50 +02:00
|
|
|
|
2006-12-04 06:54:40 +01:00
|
|
|
// @todo remove me after debugging with legion done
|
2007-06-12 18:21:47 +02:00
|
|
|
if (curStaticInst && (!curStaticInst->isMicroop() ||
|
|
|
|
curStaticInst->isFirstMicroop()))
|
2006-12-04 06:54:40 +01:00
|
|
|
instCnt++;
|
|
|
|
|
2008-06-18 19:15:21 +02:00
|
|
|
Tick stall_ticks = 0;
|
|
|
|
if (simulate_inst_stalls && icache_access)
|
|
|
|
stall_ticks += icache_latency;
|
|
|
|
|
|
|
|
if (simulate_data_stalls && dcache_access)
|
|
|
|
stall_ticks += dcache_latency;
|
|
|
|
|
|
|
|
if (stall_ticks) {
|
|
|
|
Tick stall_cycles = stall_ticks / ticks(1);
|
|
|
|
Tick aligned_stall_ticks = ticks(stall_cycles);
|
|
|
|
|
|
|
|
if (aligned_stall_ticks < stall_ticks)
|
|
|
|
aligned_stall_ticks += 1;
|
|
|
|
|
|
|
|
latency += aligned_stall_ticks;
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
2007-05-18 19:42:50 +02:00
|
|
|
if(fault != NoFault || !stayAtPC)
|
2007-03-15 03:47:42 +01:00
|
|
|
advancePC(fault);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
2008-06-18 19:15:21 +02:00
|
|
|
// instruction takes at least one cycle
|
|
|
|
if (latency < ticks(1))
|
|
|
|
latency = ticks(1);
|
|
|
|
|
2006-05-18 04:08:44 +02:00
|
|
|
if (_status != Idle)
|
2008-10-09 13:58:24 +02:00
|
|
|
schedule(tickEvent, curTick + latency);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-01-02 22:46:22 +01:00
|
|
|
void
|
|
|
|
AtomicSimpleCPU::printAddr(Addr a)
|
|
|
|
{
|
|
|
|
dcachePort.printAddr(a);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2006-05-16 23:36:50 +02:00
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
//
|
|
|
|
// AtomicSimpleCPU Simulation Object
|
|
|
|
//
|
2007-07-24 06:51:38 +02:00
|
|
|
AtomicSimpleCPU *
|
|
|
|
AtomicSimpleCPUParams::create()
|
2006-05-16 23:36:50 +02:00
|
|
|
{
|
2008-08-11 21:22:16 +02:00
|
|
|
numThreads = 1;
|
|
|
|
#if !FULL_SYSTEM
|
2007-07-24 06:51:38 +02:00
|
|
|
if (workload.size() != 1)
|
|
|
|
panic("only one workload allowed");
|
2006-05-16 23:36:50 +02:00
|
|
|
#endif
|
2008-08-11 21:22:16 +02:00
|
|
|
return new AtomicSimpleCPU(this);
|
2006-05-16 23:36:50 +02:00
|
|
|
}
|