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gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt

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Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
sim_seconds 1.920419 # Number of seconds simulated
sim_ticks 1920418772000 # Number of ticks simulated
final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
host_inst_rate 1235696 # Simulator instruction rate (inst/s)
host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42298287542 # Simulator tick rate (ticks/s)
host_mem_usage 370580 # Number of bytes of host memory used
host_seconds 45.40 # Real time elapsed on the host
sim_insts 56102800 # Number of instructions simulated
sim_ops 56102800 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory
system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory
system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 401711 # Number of read requests accepted
system.physmem.writeReqs 157234 # Number of write requests accepted
system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue
system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25160 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::1 25539 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::2 25602 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::3 25523 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::4 24974 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::5 24969 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::6 24210 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::7 24487 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::8 25140 # Per bank write bursts
system.physmem.perBankRdBursts::9 24800 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::10 25360 # Per bank write bursts
system.physmem.perBankRdBursts::11 24834 # Per bank write bursts
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.perBankRdBursts::12 24395 # Per bank write bursts
system.physmem.perBankRdBursts::13 25368 # Per bank write bursts
system.physmem.perBankRdBursts::14 25772 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::15 25477 # Per bank write bursts
system.physmem.perBankWrBursts::0 10048 # Per bank write bursts
system.physmem.perBankWrBursts::1 9910 # Per bank write bursts
system.physmem.perBankWrBursts::2 10442 # Per bank write bursts
system.physmem.perBankWrBursts::3 9959 # Per bank write bursts
system.physmem.perBankWrBursts::4 9552 # Per bank write bursts
system.physmem.perBankWrBursts::5 9342 # Per bank write bursts
system.physmem.perBankWrBursts::6 8789 # Per bank write bursts
system.physmem.perBankWrBursts::7 8561 # Per bank write bursts
system.physmem.perBankWrBursts::8 9905 # Per bank write bursts
system.physmem.perBankWrBursts::9 8742 # Per bank write bursts
system.physmem.perBankWrBursts::10 9526 # Per bank write bursts
system.physmem.perBankWrBursts::11 9262 # Per bank write bursts
system.physmem.perBankWrBursts::12 9811 # Per bank write bursts
system.physmem.perBankWrBursts::13 10568 # Per bank write bursts
system.physmem.perBankWrBursts::14 10305 # Per bank write bursts
system.physmem.perBankWrBursts::15 10316 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.totGap 1920406851000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.readPktSize::6 401711 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.writePktSize::6 157234 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads
system.physmem.totQLat 2115529750 # Total ticks spent queuing
system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers
system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtil 0.14 # Data bus utilization in percentage
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing
system.physmem.readRowHits 359951 # Number of row buffer hits during reads
system.physmem.writeRowHits 130246 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes
system.physmem.avgGap 3435770.69 # Average gap between requests
system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.686102 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states
system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.730762 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states
system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_hits 9052701 # DTB read hits
system.cpu.dtb.read_misses 10312 # DTB read misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.read_acv 210 # DTB read access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.read_accesses 728817 # DTB read accesses
system.cpu.dtb.write_hits 6349364 # DTB write hits
system.cpu.dtb.write_misses 1140 # DTB write misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.write_acv 157 # DTB write access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.write_accesses 291929 # DTB write accesses
system.cpu.dtb.data_hits 15402065 # DTB hits
system.cpu.dtb.data_misses 11452 # DTB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.dtb.data_acv 367 # DTB access violations
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.data_accesses 1020746 # DTB accesses
system.cpu.itb.fetch_hits 4973977 # ITB hits
system.cpu.itb.fetch_misses 4997 # ITB misses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.fetch_acv 184 # ITB acv
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.fetch_accesses 4978974 # ITB accesses
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numCycles 3840837544 # number of cpu cycles simulated
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.committedInsts 56102800 # Number of instructions committed
system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses
system.cpu.num_func_calls 1481300 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls
system.cpu.num_int_insts 51978055 # number of integer instructions
system.cpu.num_fp_insts 324393 # number of float instructions
system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read
system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written
system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written
system.cpu.num_mem_refs 15454652 # number of memory refs
system.cpu.num_load_insts 9089529 # Number of load instructions
system.cpu.num_store_insts 6365123 # Number of store instructions
system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles
system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles
system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.934485 # Percentage of idle cycles
system.cpu.Branches 8412940 # Number of branches fetched
system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction
system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction
system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction
system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction
system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.op_class::total 56114619 # Class of executed instruction
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.callpal::total 192900 # number of callpals executed
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches
system.cpu.kern.mode_switch::user 1743 # number of protection mode switches
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1913
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.kern.mode_good::user 1743
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.mode_good::idle 170
system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches
system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
system.cpu.dcache.tags.replacements 1389979 # number of replacements
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits
system.cpu.dcache.overall_hits::total 13648338 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses
system.cpu.dcache.overall_misses::total 1373292 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks
system.cpu.dcache.writebacks::total 834368 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304189 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304189 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17217 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17217 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1373292 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1373292 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1373292 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1373292 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26736955500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245884370 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.091421 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33682.626163 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33682.626163 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.replacements 927664 # number of replacements
system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.tag_accesses 57042955 # Number of tag accesses
system.cpu.icache.tags.data_accesses 57042955 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 55186285 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 55186285 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 55186285 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 55186285 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 55186285 # number of overall hits
system.cpu.icache.overall_hits::total 55186285 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 928335 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 928335 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 928335 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 928335 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928335 # number of overall misses
system.cpu.icache.overall_misses::total 928335 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909899750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11048066250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048066250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11048066250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016544 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.016544 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.016544 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.947664 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.947664 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency
stats: Update stats for final tick and memory bandwidth patches
2012-01-25 18:19:50 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 336225 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65295.018505 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2445535 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 401387 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 6.092711 # Average number of references to valid blocks.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 55550.770505 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.438466 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.809535 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.847637 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072761 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996323 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4873 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3256 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.tag_accesses 25931322 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 25931322 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 915025 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 814362 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1729387 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 834368 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 834368 # number of Writeback hits
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 187334 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 187334 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 915025 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1001696 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1916721 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 915025 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1001696 # number of overall hits
system.cpu.l2cache.overall_hits::total 1916721 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 271958 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 285248 # number of ReadReq misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 116838 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 116838 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 388796 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 402086 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 388796 # number of overall misses
system.cpu.l2cache.overall_misses::total 402086 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 969461250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17700747500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 18670208750 # number of ReadReq miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067922881 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8067922881 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 969461250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 25768670381 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 26738131631 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 969461250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 25768670381 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 26738131631 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 928315 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1086320 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2014635 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 834368 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 834368 # number of Writeback accesses(hits+misses)
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 928315 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1390492 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2318807 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 928315 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1390492 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2318807 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250348 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.141588 # miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384118 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384118 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.279610 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.173402 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.279610 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.173402 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72946.670429 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65086.327668 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 65452.549185 # average ReadReq miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69052.216582 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69052.216582 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 66498.539196 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 66498.539196 # average overall miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.writebacks::writebacks 74170 # number of writebacks
system.cpu.l2cache.writebacks::total 74170 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271958 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 285248 # number of ReadReq MSHR misses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116838 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 116838 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 388796 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 402086 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388796 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 402086 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802917750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14300848500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103766250 # number of ReadReq MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency
Stats: Update stats for new default L1-to-L2 bus clock and width This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoops 41901 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
system.iobus.trans_dist::WriteReq 51202 # Transaction distribution
system.iobus.trans_dist::WriteResp 9650 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 41685 # number of replacements
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 375525 # Number of tag accesses
system.iocache.tags.data_accesses 375525 # Number of data accesses
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses
system.iocache.demand_misses::total 173 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 173 # number of overall misses
system.iocache.overall_misses::total 173 # number of overall misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles
system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses
system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41512 # number of writebacks
system.iocache.writebacks::total 41512 # number of writebacks
system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadReq 292351 # Transaction distribution
system.membus.trans_dist::ReadResp 292351 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::WriteReq 9650 # Transaction distribution
system.membus.trans_dist::WriteResp 9650 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::Writeback 115682 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.trans_dist::ReadExReq 116719 # Transaction distribution
system.membus.trans_dist::ReadExResp 116719 # Transaction distribution
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoops 431 # Total snoops (count)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::samples 559506 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::total 559506 # Request fanout histogram
system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
Update ref stats. tests/test1/ref/alpha/atomic/stdout: tests/test1/ref/alpha/detailed/stderr: tests/test1/ref/alpha/detailed/stdout: tests/test1/ref/alpha/timing/stdout: Updated output. --HG-- extra : convert_revision : 3189564725ac4d2b3d63e6a71151a52326f8d416
2006-07-27 23:47:43 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink