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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt

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tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
---------- Begin Simulation Statistics ----------
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
sim_seconds 2.627904 # Number of seconds simulated
sim_ticks 2627903712000 # Number of ticks simulated
final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
host_inst_rate 497056 # Simulator instruction rate (inst/s)
host_op_rate 593637 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 21691918305 # Simulator tick rate (ticks/s)
host_mem_usage 460332 # Number of bytes of host memory used
host_seconds 121.15 # Real time elapsed on the host
sim_insts 60216663 # Number of instructions simulated
sim_ops 71917112 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory
system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory
system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s)
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15690649 # Number of read requests accepted
system.physmem.writeReqs 811422 # Number of write requests accepted
system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue
system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::0 980414 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::1 980044 # Per bank write bursts
system.physmem.perBankRdBursts::2 979984 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::3 980262 # Per bank write bursts
system.physmem.perBankRdBursts::4 986671 # Per bank write bursts
system.physmem.perBankRdBursts::5 980424 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::6 980555 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::7 980428 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::8 980781 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::9 980432 # Per bank write bursts
system.physmem.perBankRdBursts::10 979731 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankRdBursts::11 979566 # Per bank write bursts
system.physmem.perBankRdBursts::12 980337 # Per bank write bursts
system.physmem.perBankRdBursts::13 980248 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankRdBursts::14 980396 # Per bank write bursts
system.physmem.perBankRdBursts::15 980367 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankWrBursts::0 6669 # Per bank write bursts
system.physmem.perBankWrBursts::1 6337 # Per bank write bursts
system.physmem.perBankWrBursts::2 6309 # Per bank write bursts
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.perBankWrBursts::3 6427 # Per bank write bursts
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.perBankWrBursts::4 6393 # Per bank write bursts
system.physmem.perBankWrBursts::5 6675 # Per bank write bursts
system.physmem.perBankWrBursts::6 6845 # Per bank write bursts
system.physmem.perBankWrBursts::7 6769 # Per bank write bursts
system.physmem.perBankWrBursts::8 7058 # Per bank write bursts
system.physmem.perBankWrBursts::9 6682 # Per bank write bursts
system.physmem.perBankWrBursts::10 6146 # Per bank write bursts
system.physmem.perBankWrBursts::11 6016 # Per bank write bursts
system.physmem.perBankWrBursts::12 6658 # Per bank write bursts
system.physmem.perBankWrBursts::13 6472 # Per bank write bursts
system.physmem.perBankWrBursts::14 6707 # Per bank write bursts
system.physmem.perBankWrBursts::15 6699 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.totGap 2627899414000 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.readPktSize::2 6644 # Read request sizes (log2)
system.physmem.readPktSize::3 15532042 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.readPktSize::6 151963 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.writePktSize::6 57404 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1139478 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 982369 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 987635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1091943 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 997696 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1062131 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2775683 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2686264 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3513182 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 110777 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 100216 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 94857 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 91541 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19322 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18831 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18688 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::0 354 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::2 349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 345 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::7 329 # What write queue length does an incoming req see
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.wrQLenPdf::11 319 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 316 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 315 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 314 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3902 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3891 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5880 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5876 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5856 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5838 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5824 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5803 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 5782 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 5762 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 5738 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5721 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5712 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 5676 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 5665 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 5653 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 5639 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 971.829985 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 906.043406 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 203.863923 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 22728 2.18% 2.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 22848 2.20% 4.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 9187 0.88% 5.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2378 0.23% 5.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2112 0.20% 5.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1712 0.16% 5.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 9383 0.90% 6.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 867 0.08% 6.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 969000 93.15% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6002 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2614.234255 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 48623.103038 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-65535 5977 99.58% 99.58% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::131072-196607 9 0.15% 99.73% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.78% # Reads before turning the bus around for writes
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.rdPerTurnAround::total 6002 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6002 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.471176 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.313667 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 2.128575 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::2 1 0.02% 0.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::3 5 0.08% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4 9 0.15% 0.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::5 6 0.10% 0.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::6 1 0.02% 0.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::7 2 0.03% 0.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8 2 0.03% 0.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::9 6 0.10% 0.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::10 3 0.05% 0.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::11 2 0.03% 0.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12 2 0.03% 0.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::13 2 0.03% 0.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::14 2 0.03% 0.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::15 12 0.20% 0.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 2065 34.41% 35.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 28 0.47% 35.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 3575 59.56% 95.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 74 1.23% 96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 26 0.43% 97.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 13 0.22% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 8 0.13% 97.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 17 0.28% 97.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 20 0.33% 98.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 23 0.38% 98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 19 0.32% 98.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27 14 0.23% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 21 0.35% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 6 0.10% 99.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 12 0.20% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 10 0.17% 99.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6002 # Writes before turning the bus around for reads
system.physmem.totQLat 402684411250 # Total ticks spent queuing
system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 78453200000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.busUtil 3.01 # Data bus utilization in percentage
system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing
system.physmem.readRowHits 14667378 # Number of row buffer hits during reads
system.physmem.writeRowHits 87909 # Number of row buffer hits during writes
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes
system.physmem.avgGap 159246.64 # Average gap between requests
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states
system.physmem.memoryStateTime::REF 87751300000 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 16743265 # Transaction distribution
system.membus.trans_dist::ReadResp 16743265 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.membus.trans_dist::WriteReq 763389 # Transaction distribution
system.membus.trans_dist::WriteResp 763389 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.trans_dist::Writeback 57404 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 131496 # Transaction distribution
system.membus.trans_dist::ReadExResp 131496 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 213883 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 213883 # Request fanout histogram
system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.replacements 61855 # number of replacements
system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use
system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6516 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 56686 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17278829 # Number of tag accesses
system.l2c.tags.data_accesses 17278829 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 9065 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3142 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 447117 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 182266 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 10696 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 4002 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 397485 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 188475 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1242248 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 596597 # number of Writeback hits
system.l2c.Writeback_hits::total 596597 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadExReq_hits::cpu0.data 57734 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 56826 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 114560 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 9065 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3142 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 447117 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 240000 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 10696 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 4002 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 397485 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 245301 # number of demand (read+write) hits
system.l2c.demand_hits::total 1356808 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 9065 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3142 # number of overall hits
system.l2c.overall_hits::cpu0.inst 447117 # number of overall hits
system.l2c.overall_hits::cpu0.data 240000 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 10696 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 4002 # number of overall hits
system.l2c.overall_hits::cpu1.inst 397485 # number of overall hits
system.l2c.overall_hits::cpu1.data 245301 # number of overall hits
system.l2c.overall_hits::total 1356808 # number of overall hits
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_misses::cpu0.inst 4368 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 5525 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_misses::cpu1.inst 6248 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 4323 # number of ReadReq misses
system.l2c.ReadReq_misses::total 20467 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1358 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 1517 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 66435 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 66702 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133137 # number of ReadExReq misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_misses::cpu0.inst 4368 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 71960 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_misses::cpu1.inst 6248 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 71025 # number of demand (read+write) misses
system.l2c.demand_misses::total 153604 # number of demand (read+write) misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_misses::cpu0.inst 4368 # number of overall misses
system.l2c.overall_misses::cpu0.data 71960 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_misses::cpu1.inst 6248 # number of overall misses
system.l2c.overall_misses::cpu1.data 71025 # number of overall misses
system.l2c.overall_misses::total 153604 # number of overall misses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 305909750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 407234000 # number of ReadReq miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_miss_latency::cpu1.inst 435495000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 324083500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1472961000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 210491 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 255989 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 466480 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 4624449779 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4644924080 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9269373859 # number of ReadExReq miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_miss_latency::cpu0.inst 305909750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 5031683779 # number of demand (read+write) miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_miss_latency::cpu1.inst 435495000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 4969007580 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 10742334859 # number of demand (read+write) miss cycles
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_miss_latency::cpu0.inst 305909750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 5031683779 # number of overall miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_miss_latency::cpu1.inst 435495000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 4969007580 # number of overall miss cycles
system.l2c.overall_miss_latency::total 10742334859 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 9065 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3144 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 451485 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 187791 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 10697 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 4002 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 403733 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 192798 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1262715 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 596597 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 596597 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1371 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 1530 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 124169 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 123528 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 247697 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 9065 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3144 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 451485 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 311960 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 10697 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 4002 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 403733 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 316326 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1510412 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 9065 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3144 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 451485 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 311960 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 10697 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 4002 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 403733 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 316326 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1510412 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000636 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.009675 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.029421 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.015476 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.022422 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016209 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990518 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991503 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.535037 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.539975 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.537499 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000636 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.009675 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.230671 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.015476 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.224531 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.101697 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000636 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.009675 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.230671 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.015476 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.224531 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.101697 # miss rate for overall accesses
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70034.283425 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 73707.511312 # average ReadReq miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69701.504481 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74967.268101 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 71967.606391 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 155.000736 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 168.746869 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 162.253913 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69608.636698 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69636.953615 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 69622.823550 # average ReadExReq miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 69935.254674 # average overall miss latency
stats: updates due to changes to ticksToCycles()
2013-11-27 00:05:25 +01:00
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 69935.254674 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.writebacks::writebacks 57404 # number of writebacks
system.l2c.writebacks::total 57404 # number of writebacks
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 4368 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 5525 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 6248 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 4323 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 20467 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 1358 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 1517 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 66435 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 66702 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 133137 # number of ReadExReq MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 4368 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 71960 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 6248 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 71025 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 153604 # number of demand (read+write) MSHR misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_misses::cpu0.inst 4368 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 71960 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 6248 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 71025 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 153604 # number of overall MSHR misses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250603750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 338351500 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356302000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 270143000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1215601500 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13581358 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15174017 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 28755375 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3774125721 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3790687920 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 7564813641 # number of ReadExReq MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_miss_latency::cpu0.inst 250603750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 4112477221 # number of demand (read+write) MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_mshr_miss_latency::cpu1.inst 356302000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 4060830920 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 8780415141 # number of demand (read+write) MSHR miss cycles
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_miss_latency::cpu0.inst 250603750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 4112477221 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_miss_latency::cpu1.inst 356302000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 4060830920 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 8780415141 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349507750 # number of ReadReq MSHR uncacheable cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83883763250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82798029500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 167031300500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8325924664 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8377233499 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 16703158163 # number of WriteReq MSHR uncacheable cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349507750 # number of overall MSHR uncacheable cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92209687914 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91175262999 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 183734458663 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.029421 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022422 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.016209 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990518 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991503 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.535037 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.537499 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.101697 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.101697 # mshr miss rate for overall accesses
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61240.090498 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62489.706223 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 59393.242781 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.647989 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.869565 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56809.298126 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56830.198795 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 56819.769418 # average ReadExReq mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.trans_dist::ReadReq 2471648 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 18167 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution
system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.trans_dist::WriteReq 8184 # Transaction distribution
system.iobus.trans_dist::WriteResp 8184 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes)
arm: Bump stats after FS config script update This patch updates the stats to reflect the change in kernel options needed for armv8 (but used for all FS regressions).
2014-02-19 13:59:46 +01:00
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks)
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.read_hits 6554416 # DTB read hits
system.cpu0.dtb.read_misses 6570 # DTB read misses
system.cpu0.dtb.write_hits 5649486 # DTB write hits
system.cpu0.dtb.write_misses 1771 # DTB write misses
system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 6560986 # DTB read accesses
system.cpu0.dtb.write_accesses 5651257 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dtb.hits 12203902 # DTB hits
system.cpu0.dtb.misses 8341 # DTB misses
system.cpu0.dtb.accesses 12212243 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.itb.inst_hits 30237068 # ITB inst hits
system.cpu0.itb.inst_misses 3286 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses
system.cpu0.itb.hits 30237068 # DTB hits
system.cpu0.itb.misses 3286 # DTB misses
system.cpu0.itb.accesses 30240354 # DTB accesses
system.cpu0.numCycles 2626678485 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.committedInsts 29654606 # Number of instructions committed
system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses
system.cpu0.num_func_calls 1084226 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls
system.cpu0.num_int_insts 31825632 # number of integer instructions
system.cpu0.num_fp_insts 5298 # number of float instructions
system.cpu0.num_int_register_reads 57689563 # number of times the integer registers were read
system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written
system.cpu0.num_mem_refs 12632580 # number of memory refs
system.cpu0.num_load_insts 6723962 # Number of load instructions
system.cpu0.num_store_insts 5908618 # Number of store instructions
system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles
system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles
system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles
system.cpu0.Branches 5094853 # Number of branches fetched
system.cpu0.op_class::No_OpClass 11433 0.03% 0.03% # Class of executed instruction
system.cpu0.op_class::IntAlu 23427860 64.87% 64.90% # Class of executed instruction
system.cpu0.op_class::IntMult 44876 0.12% 65.02% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 988 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.02% # Class of executed instruction
system.cpu0.op_class::MemRead 6723962 18.62% 83.64% # Class of executed instruction
system.cpu0.op_class::MemWrite 5908618 16.36% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.op_class::total 36117737 # Class of executed instruction
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.tags.replacements 856352 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 358.897350 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.296827 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.700971 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.997799 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.tags.tag_accesses 62367702 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 62367702 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 29784788 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 30869186 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 60653974 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 29784788 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 30869186 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 60653974 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 29784788 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 30869186 # number of overall hits
system.cpu0.icache.overall_hits::total 60653974 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 452280 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 404584 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 856864 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 452280 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 404584 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 856864 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 452280 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 404584 # number of overall misses
system.cpu0.icache.overall_misses::total 856864 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6154944247 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5645212999 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 11800157246 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 6154944247 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 5645212999 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 11800157246 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 6154944247 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 5645212999 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 11800157246 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 30237068 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 31273770 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 61510838 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 30237068 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 31273770 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 61510838 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 30237068 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 31273770 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 61510838 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014958 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012937 # miss rate for ReadReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014958 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012937 # miss rate for demand accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014958 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012937 # miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13608.703120 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.129632 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13771.330393 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13771.330393 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13771.330393 # average overall miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 452280 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 404584 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 856864 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 452280 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 404584 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 856864 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 452280 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 404584 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 856864 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5248743753 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4833652001 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10082395754 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5248743753 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4833652001 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10082395754 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5248743753 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4833652001 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10082395754 # number of overall MSHR miss cycles
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 440846250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 440846250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for ReadReq accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for demand accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for overall accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11766.623121 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.replacements 627774 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.876288 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 21798278 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 628286 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 34.694833 # Average number of references to valid blocks.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 151.360555 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 360.515733 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.295626 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.704132 # Average percentage of cache occupancy
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.tags.tag_accesses 90462374 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 90462374 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 5593916 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 5661901 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11255817 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5011257 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 4959929 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9971186 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 42993 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 41213 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 84206 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120215 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 116148 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 236363 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126346 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 121459 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247805 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 10605173 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 10621830 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 21227003 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 10648166 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 10663043 # number of overall hits
system.cpu0.dcache.overall_hits::total 21311209 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 143610 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 152503 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 296113 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 128053 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 127367 # number of WriteReq misses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.dcache.WriteReq_misses::total 255420 # number of WriteReq misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51303 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 48866 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 100169 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6128 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5315 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11443 # number of LoadLockedReq misses
system.cpu0.dcache.demand_misses::cpu0.data 271663 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 279870 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 551533 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 322966 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 328736 # number of overall misses
system.cpu0.dcache.overall_misses::total 651702 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2007762250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2072626499 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 4080388749 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5753453329 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5756409687 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 11509863016 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81968750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77716000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 159684750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 7761215579 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 7829036186 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 15590251765 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 7761215579 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 7829036186 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 15590251765 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5737526 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 5814404 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 11551930 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5139310 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 5087296 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10226606 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 94296 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 90079 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 184375 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126343 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 121463 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 247806 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126346 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 121459 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247805 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 10876836 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 10901700 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21778536 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 10971132 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 10991779 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21962911 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025030 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026228 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.025633 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024916 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.025036 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.024976 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.544063 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.542479 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543289 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048503 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043758 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046177 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024976 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025672 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.025325 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029438 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029907 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.029673 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13980.657684 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.726078 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13779.836579 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44930.250201 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45195.456335 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45062.497126 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.101501 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14622.013170 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13954.797693 # average LoadLockedReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28569.277299 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27973.831372 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 28267.124116 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24031.060790 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23815.572940 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23922.362928 # average overall miss latency
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu0.dcache.writebacks::writebacks 596597 # number of writebacks
system.cpu0.dcache.writebacks::total 596597 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 293 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2513 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2309 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 4822 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 2743 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 2602 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 5345 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 2743 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 2602 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 5345 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 143380 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 152210 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 295590 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125540 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125058 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 250598 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 38283 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 35273 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 73556 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6128 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5315 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11443 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 268920 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 277268 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 546188 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 307203 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 312541 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 619744 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1717602000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1764563500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3482165500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5365627921 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5380262063 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10745889984 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 643406250 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 581822500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1225228750 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69708250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67035000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136743250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7083229921 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144825563 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 14228055484 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7726636171 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7726648063 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 15453284234 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91635621250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90440418250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182076039500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13169946836 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13069221001 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239167837 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104805568086 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dtb.read_hits 6613806 # DTB read hits
system.cpu1.dtb.read_misses 7420 # DTB read misses
system.cpu1.dtb.write_hits 5584575 # DTB write hits
system.cpu1.dtb.write_misses 1868 # DTB write misses
system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 6621226 # DTB read accesses
system.cpu1.dtb.write_accesses 5586443 # DTB write accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.dtb.hits 12198381 # DTB hits
system.cpu1.dtb.misses 9288 # DTB misses
system.cpu1.dtb.accesses 12207669 # DTB accesses
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.itb.inst_hits 31273770 # ITB inst hits
system.cpu1.itb.inst_misses 4023 # ITB inst misses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses
system.cpu1.itb.hits 31273770 # DTB hits
system.cpu1.itb.misses 4023 # DTB misses
system.cpu1.itb.accesses 31277793 # DTB accesses
system.cpu1.numCycles 2629128939 # number of cpu cycles simulated
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.committedInsts 30562057 # Number of instructions committed
system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses
system.cpu1.num_func_calls 1056400 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls
system.cpu1.num_int_insts 32452923 # number of integer instructions
system.cpu1.num_fp_insts 4971 # number of float instructions
system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read
system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written
system.cpu1.num_mem_refs 12626030 # number of memory refs
system.cpu1.num_load_insts 6797131 # Number of load instructions
system.cpu1.num_store_insts 5828899 # Number of store instructions
system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles
system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles
system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles
system.cpu1.Branches 5215542 # Number of branches fetched
system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction
system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction
system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction
system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu1.op_class::total 36855310 # Class of executed instruction
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles
tests: Add CPU switching tests This changeset adds a set of tests that stress the CPU switching code. It adds the following test configurations: * tsunami-switcheroo-full -- Alpha system (atomic, timing, O3) * realview-switcheroo-atomic -- ARM system (atomic<->atomic) * realview-switcheroo-timing -- ARM system (timing<->timing) * realview-switcheroo-o3 -- ARM system (O3<->O3) * realview-switcheroo-full -- ARM system (atomic, timing, O3) Reference data is provided for the 10.linux-boot test case. All of the tests trigger a CPU switch once per millisecond during the boot process. The in-order CPU model was not included in any of the tests as it does not support CPU handover.
2013-01-07 19:05:52 +01:00
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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