gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini

394 lines
7.3 KiB
INI
Raw Normal View History

2010-07-27 07:03:44 +02:00
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
2011-02-08 04:23:13 +01:00
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
2010-07-27 07:03:44 +02:00
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
2014-01-24 22:29:34 +01:00
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
2011-02-08 04:23:13 +01:00
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
2012-03-09 21:33:07 +01:00
system_port=system.membus.slave[0]
2010-07-27 07:03:44 +02:00
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
2010-07-27 07:03:44 +02:00
[system.cpu]
type=TimingSimpleCPU
2014-01-24 22:29:34 +01:00
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
branchPred=Null
2010-07-27 07:03:44 +02:00
checker=Null
clk_domain=system.cpu_clk_domain
2010-07-27 07:03:44 +02:00
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
2010-07-27 07:03:44 +02:00
do_statistics_insts=true
2014-01-24 22:29:34 +01:00
dstage2_mmu=system.cpu.dstage2_mmu
2010-07-27 07:03:44 +02:00
dtb=system.cpu.dtb
eventq_index=0
2010-07-27 07:03:44 +02:00
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
2014-01-24 22:29:34 +01:00
istage2_mmu=system.cpu.istage2_mmu
2010-07-27 07:03:44 +02:00
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
2010-07-27 07:03:44 +02:00
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
2010-07-27 07:03:44 +02:00
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
2010-07-27 07:03:44 +02:00
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
2010-07-27 07:03:44 +02:00
forward_snoops=true
hit_latency=2
is_read_only=false
2010-07-27 07:03:44 +02:00
max_miss_count=0
mshrs=4
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
2010-07-27 07:03:44 +02:00
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
2010-07-27 07:03:44 +02:00
write_buffers=8
cpu_side=system.cpu.dcache_port
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[1]
2010-07-27 07:03:44 +02:00
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
2014-01-24 22:29:34 +01:00
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
2014-01-24 22:29:34 +01:00
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
2010-07-27 07:03:44 +02:00
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
2014-01-24 22:29:34 +01:00
is_stage2=false
2010-07-27 07:03:44 +02:00
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
2014-01-24 22:29:34 +01:00
is_stage2=false
num_squash_per_cycle=2
sys=system
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[3]
2010-07-27 07:03:44 +02:00
[system.cpu.icache]
type=Cache
children=tags
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
2010-07-27 07:03:44 +02:00
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
2010-07-27 07:03:44 +02:00
forward_snoops=true
hit_latency=2
is_read_only=true
2010-07-27 07:03:44 +02:00
max_miss_count=0
mshrs=4
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
2010-07-27 07:03:44 +02:00
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
2010-07-27 07:03:44 +02:00
write_buffers=8
cpu_side=system.cpu.icache_port
2012-03-09 21:33:07 +01:00
mem_side=system.cpu.toL2Bus.slave[0]
2010-07-27 07:03:44 +02:00
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
2014-01-24 22:29:34 +01:00
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
2014-01-24 22:29:34 +01:00
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
2014-01-24 22:29:34 +01:00
id_mmfr3=34611729
id_pfr0=49
2014-01-24 22:29:34 +01:00
id_pfr1=4113
midr=1091551472
pmu=Null
2014-01-24 22:29:34 +01:00
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
2014-01-24 22:29:34 +01:00
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
2010-07-27 07:03:44 +02:00
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
2014-01-24 22:29:34 +01:00
is_stage2=false
2010-07-27 07:03:44 +02:00
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
2014-01-24 22:29:34 +01:00
is_stage2=false
num_squash_per_cycle=2
sys=system
2012-03-09 21:33:07 +01:00
port=system.cpu.toL2Bus.slave[2]
2010-07-27 07:03:44 +02:00
[system.cpu.l2cache]
type=Cache
children=tags
2012-03-09 21:33:07 +01:00
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
2010-07-27 07:03:44 +02:00
forward_snoops=true
hit_latency=20
is_read_only=false
2010-07-27 07:03:44 +02:00
max_miss_count=0
mshrs=20
2010-07-27 07:03:44 +02:00
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
2010-07-27 07:03:44 +02:00
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
2010-07-27 07:03:44 +02:00
write_buffers=8
2012-03-09 21:33:07 +01:00
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
2010-07-27 07:03:44 +02:00
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
2010-07-27 07:03:44 +02:00
[system.cpu.toL2Bus]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
2012-03-09 21:33:07 +01:00
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
2010-07-27 07:03:44 +02:00
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
2010-07-27 07:03:44 +02:00
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
drivers=
2010-07-27 07:03:44 +02:00
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
2010-07-27 07:03:44 +02:00
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
2010-07-27 07:03:44 +02:00
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=114600000000
system=system
uid=100
useArchPT=false
2010-07-27 07:03:44 +02:00
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
2010-07-27 07:03:44 +02:00
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.physmem.port
2012-03-09 21:33:07 +01:00
slave=system.system_port system.cpu.l2cache.mem_side
2010-07-27 07:03:44 +02:00
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
eventq_index=0
in_addr_map=true
2010-07-27 07:03:44 +02:00
latency=30000
latency_var=0
null=false
range=0:134217727
2012-03-09 21:33:07 +01:00
port=system.membus.master[0]
2010-07-27 07:03:44 +02:00
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000