gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini

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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
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[system]
type=System
children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
load_addr_mask=1099511627775
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load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
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work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
type=SrcClockDomain
clock=1000
eventq_index=0
voltage_domain=system.voltage_domain
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[system.cpu]
type=TimingSimpleCPU
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children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
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checker=Null
clk_domain=system.cpu_clk_domain
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cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
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do_statistics_insts=true
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dstage2_mmu=system.cpu.dstage2_mmu
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dtb=system.cpu.dtb
eventq_index=0
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function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
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istage2_mmu=system.cpu.istage2_mmu
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itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
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progress_interval=0
simpoint_start_insts=
switched_out=false
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system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
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forward_snoops=true
hit_latency=2
is_top_level=true
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max_miss_count=0
mshrs=4
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prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
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size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
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two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
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[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
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[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
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is_stage2=false
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size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
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is_stage2=false
num_squash_per_cycle=2
sys=system
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port=system.cpu.toL2Bus.slave[3]
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[system.cpu.icache]
type=BaseCache
children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
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forward_snoops=true
hit_latency=2
is_top_level=true
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max_miss_count=0
mshrs=4
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prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
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size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
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two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
eventq_index=0
fpsid=1090793632
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id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_aa64pfr0_el1=17
id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
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id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
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id_mmfr3=34611729
id_pfr0=49
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id_pfr1=4113
midr=1091551472
system=system
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
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[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
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is_stage2=false
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size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
eventq_index=0
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is_stage2=false
num_squash_per_cycle=2
sys=system
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port=system.cpu.toL2Bus.slave[2]
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[system.cpu.l2cache]
type=BaseCache
children=tags
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addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
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forward_snoops=true
hit_latency=20
is_top_level=false
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max_miss_count=0
mshrs=20
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prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
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size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
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two_queue=false
write_buffers=8
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cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
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[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
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[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
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header_cycles=1
system=system
use_default_range=false
width=32
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master=system.cpu.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
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[system.cpu.tracer]
type=ExeTracer
eventq_index=0
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[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
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egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/dist/cpu2000/binaries/arm/linux/parser
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gid=100
input=/dist/cpu2000/data/parser/mdred/input/parser.in
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max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=114600000000
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
eventq_index=0
voltage_domain=system.voltage_domain
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[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
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header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
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slave=system.system_port system.cpu.l2cache.mem_side
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[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
eventq_index=0
in_addr_map=true
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latency=30000
latency_var=0
null=false
range=0:134217727
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port=system.membus.master[0]
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[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000