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gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

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ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- Begin Simulation Statistics ----------
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
sim_seconds 0.085019 # Number of seconds simulated
sim_ticks 85018904000 # Number of ticks simulated
final_tick 85018904000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
host_inst_rate 135768 # Simulator instruction rate (inst/s)
host_op_rate 143122 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 66991355 # Simulator tick rate (ticks/s)
host_mem_usage 315704 # Number of bytes of host memory used
host_seconds 1269.10 # Real time elapsed on the host
stats: arm: updates
2015-04-30 21:17:43 +02:00
sim_insts 172303022 # Number of instructions simulated
sim_ops 181635954 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 71296 # Number of bytes read from this memory
system.physmem.bytes_read::total 246144 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 1114 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3846 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1493503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 563075 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher 838590 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2895168 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1493503 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1493503 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1493503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 563075 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher 838590 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2895168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 3846 # Number of read requests accepted
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeReqs 0 # Number of write requests accepted
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readBursts 3846 # Number of DRAM read bursts, including those serviced by the write queue
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesReadDRAM 246144 # Total number of bytes read from DRAM
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesReadSys 246144 # Total read bytes from the system interface side
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::0 309 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::1 220 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::2 142 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::3 309 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::4 300 # Per bank write bursts
system.physmem.perBankRdBursts::5 302 # Per bank write bursts
system.physmem.perBankRdBursts::6 262 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::7 237 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::8 252 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::9 219 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::10 291 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::11 194 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.perBankRdBursts::12 193 # Per bank write bursts
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.perBankRdBursts::13 211 # Per bank write bursts
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.perBankRdBursts::14 211 # Per bank write bursts
system.physmem.perBankRdBursts::15 194 # Per bank write bursts
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.totGap 85018760500 # Total gap between requests
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readPktSize::6 3846 # Read request sizes (log2)
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::0 2523 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 883 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller.
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.bytesPerActivate::samples 777 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 316.211068 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 199.877402 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 303.919917 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 237 30.50% 30.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 193 24.84% 55.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 84 10.81% 66.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 88 11.33% 77.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 35 4.50% 81.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 40 5.15% 87.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 20 2.57% 89.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 13 1.67% 91.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 67 8.62% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 777 # Bytes accessed per row activation
system.physmem.totQLat 39111678 # Total ticks spent queuing
system.physmem.totMemAccLat 111224178 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19230000 # Total ticks spent in databus transfers
system.physmem.avgQLat 10169.44 # Average queueing delay per DRAM burst
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgMemAccLat 28919.44 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgRdQLen 2.71 # Average read queue length when enqueuing
stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller.
2013-11-01 16:56:34 +01:00
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readRowHits 3067 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readRowHitRate 79.75 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.avgGap 22105761.96 # Average gap between requests
system.physmem.pageHitRate 79.75 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2744280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1497375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 16231800 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2336092560 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 48961790250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 56871322905 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.930183 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 81450773508 # Time in different power states
system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_0.memoryStateTime::ACT 728623992 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.actEnergy 3129840 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 13712400 # Energy for read commands per rank (pJ)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2289194100 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 49002929250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 56863639980 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.839816 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 81519548908 # Time in different power states
system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem_1.memoryStateTime::ACT 659848592 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.lookups 85912123 # Number of BP lookups
system.cpu.branchPred.condPredicted 68393040 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 6015536 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 40101118 # Number of BTB lookups
system.cpu.branchPred.BTBHits 39014565 # Number of BTB hits
regressions: update stats due to branch predictor changes The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.branchPred.BTBHitPct 97.290467 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 3703089 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
stats: update stats for ARMv8 changes
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.numCycles 170037809 # number of cpu cycles simulated
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.icacheStallCycles 5613511 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 349250633 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85912123 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 42717654 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 158261511 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 12044973 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 1577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.IcacheWaitRetryStallCycles 2368 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 78950648 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 18008 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 169901476 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.150563 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.047122 # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::0 17358895 10.22% 10.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 30204196 17.78% 27.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 31835534 18.74% 46.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 90502851 53.27% 100.00% # Number of instructions fetched each cycle (Total)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.fetch.rateDist::total 169901476 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.505253 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.053959 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 17563828 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 17110473 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 122657456 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 6722156 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 5847563 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 11134699 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 190129 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 306600036 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 27639970 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 5847563 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 37745979 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 8468798 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 579877 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 108923634 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 8335625 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 278650711 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 13412582 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 3051453 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 842711 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 2185712 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 35165 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 483080894 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1196921588 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 297573906 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.rename.UndoneMaps 190103965 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13336347 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 34142095 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 14476543 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2549376 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 214902718 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 219925398 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 169901476 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.264867 # Number of insts issued each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::0 52832101 31.10% 31.10% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 36093158 21.24% 52.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 65784259 38.72% 91.06% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 13574357 7.99% 99.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 1570220 0.92% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 47195 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.issued_per_cycle::total 169901476 # Number of insts issued each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::IntAlu 35605011 66.11% 66.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 1068 0.00% 66.40% # attempts to use FU when none available
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 1037 0.00% 66.47% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.fu_full::MemRead 14078469 26.14% 92.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3945889 7.33% 100.00% # attempts to use FU when none available
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::IntAlu 167344164 77.87% 77.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::SimdFloatAdd 33018 0.02% 78.31% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatCmp 165202 0.08% 78.39% # Type of FU issued
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.50% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::MemRead 32006921 14.89% 93.78% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 13373534 6.22% 100.00% # Type of FU issued
tests: update stats for name changes
2011-04-20 03:45:23 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iq.FU_type_0::total 214902718 # Type of FU issued
system.cpu.iq.rate 1.263853 # Inst issue rate
system.cpu.iq.fu_busy_cnt 53854775 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 654798543 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 204597394 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 3953764 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 266623027 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2134466 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 1601141 # Number of loads that had data forwarded from stores
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 6245951 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 7537 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1831909 # Number of stores squashed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 804 # Number of times an access to memory failed due to the cache being blocked
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewSquashCycles 5847563 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 5681873 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 37049 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.iewDispLoadInsts 34142095 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 14476543 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 29963 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 207521850 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 30720954 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 7380868 # Number of squashed instructions skipped in execute
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.exec_nop 15987 # number of nop insts executed
system.cpu.iew.exec_refs 43860782 # number of memory reference insts executed
system.cpu.iew.exec_branches 44934590 # Number of branches executed
system.cpu.iew.exec_stores 13139828 # Number of stores executed
system.cpu.iew.exec_rate 1.220445 # Inst execution rate
system.cpu.iew.wb_sent 206738830 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 206403837 # cumulative count of insts written-back
system.cpu.iew.wb_producers 129472700 # num instructions producing a value
system.cpu.iew.wb_consumers 221699640 # num instructions consuming a value
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.iew.wb_rate 1.213870 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.584000 # average fanout of values written-back
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.commitSquashedInsts 69532932 # The number of squashed insts skipped by commit
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 158460459 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.146345 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.646701 # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::0 73681032 46.50% 46.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 41276330 26.05% 72.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 22553900 14.23% 86.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 9626912 6.08% 92.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2147757 1.36% 96.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1281176 0.81% 97.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 3356651 2.12% 100.00% # Number of insts commited each cycle
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.committed_per_cycle::total 158460459 # Number of insts commited each cycle
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.committedInsts 172317410 # Number of instructions committed
system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.refs 40540778 # Number of memory references committed
system.cpu.commit.loads 27896144 # Number of loads committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.membars 22408 # Number of memory barriers committed
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.branches 40300312 # Number of branches committed
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
Stats: Update stats for minor O3 changes below.
2011-05-23 17:59:13 +02:00
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 27896144 15.36% 93.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Class of committed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.commit.bw_lim_events 3356651 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 406281881 # The number of ROB reads
system.cpu.rob.rob_writes 513821502 # The number of ROB writes
system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 136333 # Total number of cycles that the CPU has spent unscheduled due to idling
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.committedInsts 172303022 # Number of Instructions Simulated
system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.cpi 0.986853 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.986853 # CPI: Total CPI of All Threads
system.cpu.ipc 1.013322 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.013322 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 218956398 # number of integer regfile reads
system.cpu.int_regfile_writes 114512064 # number of integer regfile writes
system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads
system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes
system.cpu.cc_regfile_reads 709567727 # number of cc regfile reads
system.cpu.cc_regfile_writes 229536120 # number of cc regfile writes
system.cpu.misc_regfile_reads 59314176 # number of misc regfile reads
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.replacements 72863 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.419653 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 41115439 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 73375 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 560.346698 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 504093500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.419653 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.998867 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.998867 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.tags.tag_accesses 82529747 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 82529747 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28729201 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28729201 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12341321 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12341321 # number of WriteReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_hits::cpu.data 41070522 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 41070522 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 41070883 # number of overall hits
system.cpu.dcache.overall_hits::total 41070883 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 89405 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 22966 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 22966 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 112371 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 112371 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 112488 # number of overall misses
system.cpu.dcache.overall_misses::total 112488 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 853901000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 853901000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 240852499 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 240852499 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1094753499 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1094753499 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1094753499 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1094753499 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28818606 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28818606 # number of ReadReq accesses(hits+misses)
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 478 # number of SoftPFReq accesses(hits+misses)
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses)
stats: update stats for previous six changes
2013-01-08 14:54:16 +01:00
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.demand_accesses::cpu.data 41182893 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 41182893 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 41183371 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 41183371 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9550.931156 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 9550.931156 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 9742.313399 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 9742.313399 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 9732.180313 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 9732.180313 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 10552 # number of cycles access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 12.198844 # average number of cycles each access was blocked
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks
system.cpu.dcache.writebacks::total 64850 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24706 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 24706 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14404 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 14404 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 39110 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 39110 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 39110 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 39110 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64699 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 64699 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 73261 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 73261 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 73375 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 73375 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558347000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 558347000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85131499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85131499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 643478499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 643478499 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 644448499 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 644448499 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.238494 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.238494 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8629.917000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8629.917000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9942.945457 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9942.945457 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8783.370402 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 8783.370402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8782.943768 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 8782.943768 # average overall mshr miss latency
stats: update stats for previous changes.
2013-01-07 19:05:54 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.replacements 54433 # number of replacements
system.cpu.icache.tags.tagsinuse 510.604366 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 78892637 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1435.847429 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 84263927500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.604366 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997274 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.tags.tag_accesses 157956201 # Number of tag accesses
system.cpu.icache.tags.data_accesses 157956201 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 78892637 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 78892637 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 78892637 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 78892637 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 78892637 # number of overall hits
system.cpu.icache.overall_hits::total 78892637 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 57991 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 57991 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 57991 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 57991 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 57991 # number of overall misses
system.cpu.icache.overall_misses::total 57991 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 602655456 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 602655456 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 602655456 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 602655456 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 602655456 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 602655456 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 78950628 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 78950628 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 78950628 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 78950628 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 78950628 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 78950628 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10392.223897 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10392.223897 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 58612 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.blocked::no_mshrs 2849 # number of cycles access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 20.572833 # average number of cycles each access was blocked
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3046 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 3046 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 3046 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 3046 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 3046 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 3046 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54945 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 54945 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 54945 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 54945 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 54945 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 54945 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 535420965 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 535420965 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 535420965 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 535420965 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 535420965 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 535420965 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9744.671308 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9744.671308 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9744.671308 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 9744.671308 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9744.671308 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 9744.671308 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.prefetcher.num_hwpf_issued 9365 # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified 9365 # number of prefetch candidates identified
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.prefetcher.pfSpanPage 1339 # number of prefetches not generated due to page crossing
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.replacements 0 # number of replacements
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.tagsinuse 2660.276616 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 230314 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3583 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 64.279654 # Average number of references to valid blocks.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 701.934591 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.049531 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 421.061183 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.231311 # Average occupied blocks per requestor
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.tags.occ_percent::writebacks 0.042843 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.025700 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009841 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.162370 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3322 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 754 # Occupied blocks per task id
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202759 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3933865 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3933865 # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks 64850 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 64850 # number of Writeback hits
stats: arm: updates
2015-04-30 21:17:43 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 8397 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 8397 # number of ReadExReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52956 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 52956 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 64220 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 64220 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 52956 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 72617 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 125573 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 52956 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 72617 # number of overall hits
system.cpu.l2cache.overall_hits::total 125573 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 237 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 237 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1989 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1989 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 521 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 521 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1989 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2747 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1989 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses
system.cpu.l2cache.overall_misses::total 2747 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18014000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 18014000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 135911500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 135911500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37126500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 37126500 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 135911500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 55140500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 191052000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 135911500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 55140500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 191052000 # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks 64850 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 64850 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54945 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 54945 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64741 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 64741 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 54945 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 73375 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 128320 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 54945 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 73375 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 128320 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027450 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.027450 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.036200 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.036200 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.008047 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.008047 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036200 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.010330 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.021407 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036200 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.010330 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.021407 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76008.438819 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76008.438819 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68331.573655 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68331.573655 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 71260.076775 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 71260.076775 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68331.573655 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72744.722955 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69549.326538 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68331.573655 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72744.722955 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69549.326538 # average overall miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1818 # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total 1818 # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1984 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1984 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 513 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 513 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1984 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2732 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1984 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1818 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 4550 # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70301588 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16173000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16173000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 123686500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 123686500 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33594500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33594500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 123686500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49767500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 173454000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 123686500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49767500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 243755588 # number of overall MSHR miss cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027218 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027218 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007924 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.021291 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for overall accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.overall_mshr_miss_rate::total 0.035458 # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374 # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703 # average overall mshr miss latency
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.trans_dist::ReadResp 119686 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 2160 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 64741 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155973 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217450 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 373423 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 12362880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2160 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 257776 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 1.008379 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.091155 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::1 255616 99.16% 99.16% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 2160 0.84% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.snoop_fanout::total 257776 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 192658000 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 82430973 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 110066991 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::ReadResp 3611 # Transaction distribution
system.membus.trans_dist::ReadExReq 235 # Transaction distribution
system.membus.trans_dist::ReadExResp 235 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3611 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7692 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7692 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 246144 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoops 0 # Total snoops (count)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::samples 3846 # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::0 3846 100.00% 100.00% # Request fanout histogram
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.snoop_fanout::total 3846 # Request fanout histogram
system.membus.reqLayer0.occupancy 5081597 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.respLayer1.occupancy 20277583 # Layer occupancy (ticks)
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
ARM/O3: Add regressions for ARM w/ O3 CPU.
2011-01-18 23:30:06 +01:00
---------- End Simulation Statistics ----------
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