gem5/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini

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[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
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time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
readfile=
symbolfile=
thermal_components=
thermal_model=Null
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work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[1]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu0]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu0.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu0.port
mem_side=system.toL2Bus.slave[0]
[system.cpu0.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu1]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu1.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu1.port
mem_side=system.toL2Bus.slave[1]
[system.cpu1.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu2]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu2.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu2.port
mem_side=system.toL2Bus.slave[2]
[system.cpu2.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu3]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu3.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu3.port
mem_side=system.toL2Bus.slave[3]
[system.cpu3.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu4]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu4.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu4.port
mem_side=system.toL2Bus.slave[4]
[system.cpu4.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu5]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu5.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu5.port
mem_side=system.toL2Bus.slave[5]
[system.cpu5.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu6]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu6.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu6.port
mem_side=system.toL2Bus.slave[6]
[system.cpu6.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu7]
type=MemTest
children=l1c
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
interval=1
max_loads=100000
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
percent_functional=50
percent_reads=65
percent_uncacheable=10
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power_model=Null
progress_check=5000000
progress_interval=10000
size=65536
suppress_func_warnings=false
system=system
port=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
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is_read_only=false
max_miss_count=0
mshrs=4
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=32768
system=system
tags=system.cpu7.l1c.tags
tgts_per_mshr=20
write_buffers=8
writeback_clean=false
cpu_side=system.cpu7.port
mem_side=system.toL2Bus.slave[7]
[system.cpu7.l1c.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.l2c]
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type=Cache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
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default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
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is_read_only=false
max_miss_count=0
mshrs=20
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=65536
system=system
tags=system.l2c.tags
tgts_per_mshr=12
write_buffers=8
writeback_clean=false
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[0]
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=65536
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
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default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
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power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=16
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master=system.physmem.port
slave=system.l2c.mem_side system.system_port
[system.physmem]
type=SimpleMemory
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bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
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default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
range=0:134217727
port=system.membus.master[0]
[system.toL2Bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
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default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
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p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
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power_model=Null
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2c.cpu_side
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000