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gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt

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ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- Begin Simulation Statistics ----------
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
sim_seconds 0.000088 # Number of seconds simulated
sim_ticks 87948 # Number of ticks simulated
final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86 Regressions: Update stats due to fence instruction
2012-01-10 16:59:01 +01:00
sim_freq 1000000000 # Frequency of simulated ticks
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
host_inst_rate 39587 # Simulator instruction rate (inst/s)
host_op_rate 71707 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 646904 # Simulator tick rate (ticks/s)
host_mem_usage 417864 # Number of bytes of host memory used
host_seconds 0.14 # Real time elapsed on the host
stats: Update stats for syscall emulation Linux kernel changes.
2012-08-15 16:38:05 +02:00
sim_insts 5381 # Number of instructions simulated
regressions: x86: stats updates due to new x87 insts
2013-03-11 23:45:09 +01:00
sim_ops 9748 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory
system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.bw_read::ruby.dir_cntrl0 1002046664 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total 1002046664 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 999135853 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 999135853 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::ruby.dir_cntrl0 2001182517 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total 2001182517 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readReqs 1377 # Number of read requests accepted
system.mem_ctrls.writeReqs 1373 # Number of write requests accepted
system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.bytesReadDRAM 40320 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 47808 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 39936 # Total number of bytes written to DRAM
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 722 # Number of DRAM write bursts merged with an existing one
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankRdBursts::0 59 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankRdBursts::3 9 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 52 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 55 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 37 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 119 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 121 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankRdBursts::13 21 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankRdBursts::15 30 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 51 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankWrBursts::3 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 50 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 36 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 25 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 120 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10 125 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 23 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.totGap 87868 # Total gap between requests
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2)
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.rdQLenPdf::0 630 # What read queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.bytesPerActivate::samples 271 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean 293.313653 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean 193.377642 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev 283.497497 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 72 26.57% 26.57% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 83 30.63% 57.20% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 37 13.65% 70.85% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511 23 8.49% 79.34% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639 21 7.75% 87.08% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767 5 1.85% 88.93% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895 7 2.58% 91.51% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023 3 1.11% 92.62% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 20 7.38% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 271 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 16.289474 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 16.048466 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev 3.463383 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::12-13 1 2.63% 2.63% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::14-15 15 39.47% 42.11% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-17 16 42.11% 84.21% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 4 10.53% 94.74% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::20-21 1 2.63% 97.37% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 2.63% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16.421053 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.397539 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev 0.919212 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 31 81.58% 81.58% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 5 13.16% 94.74% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads
system.mem_ctrls.totQLat 9303 # Total ticks spent queuing
system.mem_ctrls.totMemAccLat 21273 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 3150 # Total ticks spent in databus transfers
system.mem_ctrls.avgQLat 14.77 # Average queueing delay per DRAM burst
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.avgMemAccLat 33.77 # Average memory access latency per DRAM burst
system.mem_ctrls.avgRdBW 458.45 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 454.09 # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys 1002.05 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 999.14 # Average system write bandwidth in MiByte/s
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.busUtil 7.13 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 3.58 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls.avgWrQLen 25.04 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 420 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 556 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 66.67 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 85.41 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 31.95 # Average gap between requests
system.mem_ctrls.pageHitRate 76.19 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 657720 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 365400 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 3407040 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_0.actBackEnergy 51093432 # Energy for active background per rank (pJ)
system.mem_ctrls_0.preBackEnergy 6724800 # Energy for precharge background per rank (pJ)
system.mem_ctrls_0.totalEnergy 70465656 # Total energy per rank (pJ)
system.mem_ctrls_0.averagePower 820.264661 # Core power per rank (mW)
system.mem_ctrls_0.memoryStateTime::IDLE 10886 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls_0.memoryStateTime::ACT 72174 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls_1.actEnergy 1368360 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 760200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 4268160 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 3680640 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
system.mem_ctrls_1.actBackEnergy 54919728 # Energy for active background per rank (pJ)
system.mem_ctrls_1.preBackEnergy 3368400 # Energy for precharge background per rank (pJ)
system.mem_ctrls_1.totalEnergy 73959648 # Total energy per rank (pJ)
system.mem_ctrls_1.averagePower 860.936931 # Core power per rank (mW)
system.mem_ctrls_1.memoryStateTime::IDLE 5575 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.apic_clk_domain.clock 16 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.cpu.numCycles 87948 # number of cpu cycles simulated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5381 # Number of instructions committed
system.cpu.committedOps 9748 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 209 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls
system.cpu.num_int_insts 9654 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
system.cpu.num_int_register_reads 18335 # number of times the integer registers were read
system.cpu.num_int_register_writes 7527 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read
system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written
system.cpu.num_mem_refs 1988 # number of memory refs
system.cpu.num_load_insts 1053 # Number of load instructions
system.cpu.num_store_insts 935 # Number of store instructions
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.cpu.num_idle_cycles 0.999989 # Number of idle cycles
system.cpu.num_busy_cycles 87947.000011 # Number of busy cycles
system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000011 # Percentage of idle cycles
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu.Branches 1208 # Number of branches fetched
system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction
system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction
system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction
system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction
system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction
system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.ruby.clk_domain.clock 1 # Clock period in ticks
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 2750 # delay histogram for all message
system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 2750 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.outstanding_req_hist::samples 8852
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.outstanding_req_hist::mean 1
system.ruby.outstanding_req_hist::gmean 1
stats: updates due to previous mmap and exit_group patches.
2014-10-20 23:48:19 +02:00
system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist::total 8852
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.latency_hist::bucket_size 64
system.ruby.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.latency_hist::samples 8852
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.latency_hist::mean 8.935382
system.ruby.latency_hist::gmean 1.815175
system.ruby.latency_hist::stdev 22.675647
system.ruby.latency_hist | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.latency_hist::total 8852
system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
system.ruby.hit_latency_hist::samples 7475
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.hit_latency_hist::mean 1
system.ruby.hit_latency_hist::gmean 1
system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7475 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.hit_latency_hist::total 7475
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.miss_latency_hist::bucket_size 64
system.ruby.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.miss_latency_hist::samples 1377
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.miss_latency_hist::mean 52.012346
system.ruby.miss_latency_hist::gmean 46.179478
system.ruby.miss_latency_hist::stdev 33.292581
system.ruby.miss_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.miss_latency_hist::total 1377
system.ruby.Directory.incomplete_times 1376
stats: updates statistics for ruby regressions
2013-05-21 18:32:57 +02:00
system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers0.percent_links_utilized 7.817119
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.msg_count.Control::2 1377
system.ruby.network.routers0.msg_count.Data::2 1373
system.ruby.network.routers0.msg_count.Response_Data::4 1377
system.ruby.network.routers0.msg_count.Writeback_Control::3 1373
system.ruby.network.routers0.msg_bytes.Control::2 11016
system.ruby.network.routers0.msg_bytes.Data::2 98856
system.ruby.network.routers0.msg_bytes.Response_Data::4 99144
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers1.percent_links_utilized 7.817119
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.msg_count.Control::2 1377
system.ruby.network.routers1.msg_count.Data::2 1373
system.ruby.network.routers1.msg_count.Response_Data::4 1377
system.ruby.network.routers1.msg_count.Writeback_Control::3 1373
system.ruby.network.routers1.msg_bytes.Control::2 11016
system.ruby.network.routers1.msg_bytes.Data::2 98856
system.ruby.network.routers1.msg_bytes.Response_Data::4 99144
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers2.percent_links_utilized 7.817119
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.msg_count.Control::2 1377
system.ruby.network.routers2.msg_count.Data::2 1373
system.ruby.network.routers2.msg_count.Response_Data::4 1377
system.ruby.network.routers2.msg_count.Writeback_Control::3 1373
system.ruby.network.routers2.msg_bytes.Control::2 11016
system.ruby.network.routers2.msg_bytes.Data::2 98856
system.ruby.network.routers2.msg_bytes.Response_Data::4 99144
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984
tests: update reference outputs Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
2013-09-28 21:25:17 +02:00
system.ruby.network.msg_count.Control 4131
system.ruby.network.msg_count.Data 4119
system.ruby.network.msg_count.Response_Data 4131
system.ruby.network.msg_count.Writeback_Control 4119
system.ruby.network.msg_byte.Control 33048
system.ruby.network.msg_byte.Data 296568
system.ruby.network.msg_byte.Response_Data 297432
system.ruby.network.msg_byte.Writeback_Control 32952
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers0.throttle0.link_utilization 7.826215
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers0.throttle1.link_utilization 7.808023
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers0.throttle1.msg_count.Control::2 1377
system.ruby.network.routers0.throttle1.msg_count.Data::2 1373
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers1.throttle0.link_utilization 7.808023
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.throttle0.msg_count.Control::2 1377
system.ruby.network.routers1.throttle0.msg_count.Data::2 1373
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers1.throttle1.link_utilization 7.826215
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers2.throttle0.link_utilization 7.826215
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.network.routers2.throttle1.link_utilization 7.808023
stats: ruby: updates due to recent changes.
2013-09-06 23:21:36 +02:00
system.ruby.network.routers2.throttle1.msg_count.Control::2 1377
system.ruby.network.routers2.throttle1.msg_count.Data::2 1373
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.latency_hist::bucket_size 32
system.ruby.LD.latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.latency_hist::samples 1045
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.latency_hist::mean 22.607656
system.ruby.LD.latency_hist::gmean 5.952637
system.ruby.LD.latency_hist::stdev 28.358291
system.ruby.LD.latency_hist | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.latency_hist::total 1045
system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
system.ruby.LD.hit_latency_hist::samples 546
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.hit_latency_hist::mean 1
system.ruby.LD.hit_latency_hist::gmean 1
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 546 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.hit_latency_hist::total 546
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.miss_latency_hist::bucket_size 32
system.ruby.LD.miss_latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.miss_latency_hist::samples 499
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.miss_latency_hist::mean 46.250501
system.ruby.LD.miss_latency_hist::gmean 41.916728
system.ruby.LD.miss_latency_hist::stdev 24.776985
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.miss_latency_hist::total 499
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.ST.latency_hist::bucket_size 64
system.ruby.ST.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.latency_hist::samples 935
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.ST.latency_hist::mean 15.124064
system.ruby.ST.latency_hist::gmean 2.829099
system.ruby.ST.latency_hist::stdev 31.003309
system.ruby.ST.latency_hist | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.latency_hist::total 935
system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
system.ruby.ST.hit_latency_hist::samples 681
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.ST.hit_latency_hist::mean 1
system.ruby.ST.hit_latency_hist::gmean 1
system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 681 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.hit_latency_hist::total 681
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.ST.miss_latency_hist::bucket_size 64
system.ruby.ST.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.miss_latency_hist::samples 254
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.ST.miss_latency_hist::mean 52.992126
system.ruby.ST.miss_latency_hist::gmean 45.979346
system.ruby.ST.miss_latency_hist::stdev 39.646660
system.ruby.ST.miss_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.miss_latency_hist::total 254
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.latency_hist::bucket_size 64
system.ruby.IFETCH.latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.latency_hist::samples 6864
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.IFETCH.latency_hist::mean 6.015589
system.ruby.IFETCH.latency_hist::gmean 1.426336
system.ruby.IFETCH.latency_hist::stdev 19.173758
system.ruby.IFETCH.latency_hist | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.latency_hist::total 6864
system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
system.ruby.IFETCH.hit_latency_hist::samples 6241
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.IFETCH.hit_latency_hist::mean 1
system.ruby.IFETCH.hit_latency_hist::gmean 1
system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 6241 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.hit_latency_hist::total 6241
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.miss_latency_hist::bucket_size 64
system.ruby.IFETCH.miss_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.miss_latency_hist::samples 623
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.IFETCH.miss_latency_hist::mean 56.260032
system.ruby.IFETCH.miss_latency_hist::gmean 50.022291
system.ruby.IFETCH.miss_latency_hist::stdev 35.712767
system.ruby.IFETCH.miss_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.miss_latency_hist::total 623
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.RMW_Read.latency_hist::bucket_size 4
system.ruby.RMW_Read.latency_hist::max_bucket 39
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.latency_hist::samples 8
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.RMW_Read.latency_hist::mean 4.875000
system.ruby.RMW_Read.latency_hist::gmean 1.542211
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.RMW_Read.latency_hist::stdev 10.960155
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.latency_hist | 7 87.50% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 0 0.00% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00%
system.ruby.RMW_Read.latency_hist::total 8
system.ruby.RMW_Read.hit_latency_hist::bucket_size 1
system.ruby.RMW_Read.hit_latency_hist::max_bucket 9
system.ruby.RMW_Read.hit_latency_hist::samples 7
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.RMW_Read.hit_latency_hist::mean 1
system.ruby.RMW_Read.hit_latency_hist::gmean 1
system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.hit_latency_hist::total 7
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.RMW_Read.miss_latency_hist::bucket_size 4
system.ruby.RMW_Read.miss_latency_hist::max_bucket 39
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.miss_latency_hist::samples 1
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.RMW_Read.miss_latency_hist::mean 32
system.ruby.RMW_Read.miss_latency_hist::gmean 32
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.miss_latency_hist::stdev nan
system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.RMW_Read.miss_latency_hist::total 1
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_mach_latency_hist::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_mach_latency_hist::samples 1377
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.Directory.miss_mach_latency_hist::mean 52.012346
system.ruby.Directory.miss_mach_latency_hist::gmean 46.179478
system.ruby.Directory.miss_mach_latency_hist::stdev 33.292581
system.ruby.Directory.miss_mach_latency_hist | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_mach_latency_hist::total 1377
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev nan
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 1
system.ruby.Directory.miss_latency_hist.initial_to_forward::stdev nan
system.ruby.Directory.miss_latency_hist.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 1
system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev nan
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 1
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 499
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 46.250501
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 41.916728
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 24.776985
system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 499
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 254
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 52.992126
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 45.979346
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 39.646660
system.ruby.ST.Directory.miss_type_mach_latency_hist | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 254
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 56.260032
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 50.022291
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.712767
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623
stats: updates due to changes to ruby
2014-11-06 12:42:21 +01:00
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::max_bucket 39
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::samples 1
stats: Bump for MessageBuffer, cache latency changes
2015-08-14 08:19:34 +02:00
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::mean 32
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 32
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.ruby.Directory_Controller.GETX 1377 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00%
system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00%
stats: updates due to changes to ruby
2014-01-10 23:19:58 +01:00
system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 943 0.00% 0.00%
system.ruby.L1Cache_Controller.Data 1377 0.00% 0.00%
system.ruby.L1Cache_Controller.Replacement 1373 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 1373 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Load 499 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 623 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 255 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 546 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Ifetch 6241 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 688 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00%
ruby: Initial references for ruby regressions
2009-05-11 19:38:46 +02:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink