2013-03-01 19:20:30 +01:00
---------- Begin Simulation Statistics ----------
2015-09-25 13:27:03 +02:00
sim_seconds 2.824718 # Number of seconds simulated
sim_ticks 2824717821500 # Number of ticks simulated
final_tick 2824717821500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2013-03-01 19:20:30 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-09-25 13:27:03 +02:00
host_inst_rate 249146 # Simulator instruction rate (inst/s)
host_op_rate 302232 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5724351305 # Simulator tick rate (ticks/s)
host_mem_usage 631692 # Number of bytes of host memory used
host_seconds 493.46 # Real time elapsed on the host
sim_insts 122942928 # Number of instructions simulated
sim_ops 149138280 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::cpu0.inst 536420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 4179876 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 121792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 910464 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 318592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1655680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.dtb.walker 4032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 408768 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 3010752 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_read::total 11149640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 536420 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 121792 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 318592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 408768 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1385572 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8394624 # Number of bytes written to this memory
2015-07-30 11:16:36 +02:00
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
2015-09-25 13:27:03 +02:00
system.physmem.bytes_written::total 8412148 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::cpu0.inst 16835 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 65830 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1903 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 14226 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 4978 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 25870 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.dtb.walker 63 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 6387 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 47043 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_reads::total 183186 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131166 # Number of write requests responded to by this memory
2015-07-30 11:16:36 +02:00
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
2015-09-25 13:27:03 +02:00
system.physmem.num_writes::total 135547 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::cpu0.inst 189902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1479750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 43117 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 322320 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 702 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 112787 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 586140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.dtb.walker 1427 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 144711 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 1065859 # Total read bandwidth from this memory (bytes/s)
2015-07-30 11:16:36 +02:00
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::total 3947169 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 189902 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 43117 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 112787 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 144711 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 490517 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2971845 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2978049 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2971845 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:18:29 +01:00
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::cpu0.inst 189902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1485954 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 43117 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 322320 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 702 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 112787 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 586140 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.dtb.walker 1427 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 144711 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 1065859 # Total bandwidth to/from this memory (bytes/s)
2015-07-30 11:16:36 +02:00
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::total 6925218 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 100502 # Number of read requests accepted
system.physmem.writeReqs 68912 # Number of write requests accepted
system.physmem.readBursts 100502 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 68912 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 6426176 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue
system.physmem.bytesWritten 4409728 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 6432128 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4410368 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue
2015-07-30 11:16:36 +02:00
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
2015-09-25 13:27:03 +02:00
system.physmem.neitherReadNorWriteReqs 17980 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 6920 # Per bank write bursts
system.physmem.perBankRdBursts::1 6286 # Per bank write bursts
system.physmem.perBankRdBursts::2 6764 # Per bank write bursts
system.physmem.perBankRdBursts::3 6403 # Per bank write bursts
system.physmem.perBankRdBursts::4 6105 # Per bank write bursts
system.physmem.perBankRdBursts::5 5950 # Per bank write bursts
system.physmem.perBankRdBursts::6 6704 # Per bank write bursts
system.physmem.perBankRdBursts::7 6701 # Per bank write bursts
system.physmem.perBankRdBursts::8 6487 # Per bank write bursts
system.physmem.perBankRdBursts::9 6589 # Per bank write bursts
system.physmem.perBankRdBursts::10 6182 # Per bank write bursts
system.physmem.perBankRdBursts::11 5526 # Per bank write bursts
system.physmem.perBankRdBursts::12 5641 # Per bank write bursts
system.physmem.perBankRdBursts::13 6650 # Per bank write bursts
system.physmem.perBankRdBursts::14 6151 # Per bank write bursts
system.physmem.perBankRdBursts::15 5350 # Per bank write bursts
system.physmem.perBankWrBursts::0 4550 # Per bank write bursts
system.physmem.perBankWrBursts::1 4246 # Per bank write bursts
system.physmem.perBankWrBursts::2 4783 # Per bank write bursts
system.physmem.perBankWrBursts::3 4329 # Per bank write bursts
system.physmem.perBankWrBursts::4 4133 # Per bank write bursts
system.physmem.perBankWrBursts::5 4124 # Per bank write bursts
system.physmem.perBankWrBursts::6 4743 # Per bank write bursts
system.physmem.perBankWrBursts::7 4271 # Per bank write bursts
system.physmem.perBankWrBursts::8 4451 # Per bank write bursts
system.physmem.perBankWrBursts::9 4796 # Per bank write bursts
system.physmem.perBankWrBursts::10 4218 # Per bank write bursts
system.physmem.perBankWrBursts::11 3947 # Per bank write bursts
system.physmem.perBankWrBursts::12 3851 # Per bank write bursts
system.physmem.perBankWrBursts::13 4779 # Per bank write bursts
system.physmem.perBankWrBursts::14 4130 # Per bank write bursts
system.physmem.perBankWrBursts::15 3551 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-09-25 13:27:03 +02:00
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2823151552500 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-07-30 11:16:36 +02:00
system.physmem.readPktSize::2 0 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 0 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::6 100502 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2015-07-30 11:16:36 +02:00
system.physmem.writePktSize::2 0 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.writePktSize::6 68912 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 76732 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 21067 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2057 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 552 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
2015-07-30 11:16:36 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
2013-11-01 16:56:34 +01:00
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
2013-03-01 19:20:30 +01:00
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::0 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 69 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 67 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 66 # What write queue length does an incoming req see
2015-07-30 11:16:36 +02:00
system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::5 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1227 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1461 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3065 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 3816 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4087 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4893 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 4186 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4173 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4364 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 3907 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 3740 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 3651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 136 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 75 # What write queue length does an incoming req see
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::38 48 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::39 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 35 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 32 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 63 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 38 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 27 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 22 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 39319 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 275.584628 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 163.263333 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 308.433492 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 16168 41.12% 41.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9688 24.64% 65.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 3830 9.74% 75.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2076 5.28% 80.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1590 4.04% 84.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 981 2.49% 87.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 594 1.51% 88.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 552 1.40% 90.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3840 9.77% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 39319 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 3599 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.894137 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 471.050714 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 3597 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 3599 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 3599 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.144762 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.954400 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 10.164866 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 6 0.17% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 1 0.03% 0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 5 0.14% 0.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 3182 88.41% 88.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 82 2.28% 91.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 48 1.33% 92.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 63 1.75% 94.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 10 0.28% 94.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 54 1.50% 95.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 28 0.78% 96.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 5 0.14% 96.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 9 0.25% 97.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 17 0.47% 97.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 4 0.11% 97.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 3 0.08% 97.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 52 1.44% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.14% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 2 0.06% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 13 0.36% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 1 0.03% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 2 0.06% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 3 0.08% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3599 # Writes before turning the bus around for reads
system.physmem.totQLat 1312823000 # Total ticks spent queuing
system.physmem.totMemAccLat 3195491750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 502045000 # Total ticks spent in databus transfers
system.physmem.avgQLat 13074.75 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgMemAccLat 31824.75 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2014-10-30 05:18:29 +01:00
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
2015-03-02 11:04:20 +01:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2014-10-30 05:18:29 +01:00
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
2015-09-25 13:27:03 +02:00
system.physmem.avgWrQLen 20.91 # Average write queue length when enqueuing
system.physmem.readRowHits 80981 # Number of row buffer hits during reads
system.physmem.writeRowHits 49010 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.65 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 71.12 # Row buffer hit rate for writes
system.physmem.avgGap 16664216.37 # Average gap between requests
system.physmem.pageHitRate 76.77 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 156287880 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 85152375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 404274000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 227959920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 73215548100 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1622782125750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1876644765225 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.446746 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2640312790250 # Time in different power states
system.physmem_0.memoryStateTime::REF 91908700000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_0.memoryStateTime::ACT 20242228250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.actEnergy 140963760 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 76741500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 378892800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 218525040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 179773417200 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 72451612440 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1618075692000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1871115844740 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.608024 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2641479820250 # Time in different power states
system.physmem_1.memoryStateTime::REF 91908700000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-09-25 13:27:03 +02:00
system.physmem_1.memoryStateTime::ACT 19062807500 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-11-03 17:14:42 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
2013-03-01 19:20:30 +01:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walks 4993 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 4993 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples 4993 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0 4993 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 4993 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 1.255415 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -14647046374 -25.54% -25.54% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 71993140750 125.54% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 57346094376 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 2743 66.90% 66.90% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.10% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 4100 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4993 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4993 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4100 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4100 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 9093 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.read_hits 12030030 # DTB read hits
system.cpu0.dtb.read_misses 4190 # DTB read misses
system.cpu0.dtb.write_hits 9398007 # DTB write hits
system.cpu0.dtb.write_misses 803 # DTB write misses
system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.flush_entries 2915 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.prefetch_faults 721 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.perms_faults 173 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 12034220 # DTB read accesses
system.cpu0.dtb.write_accesses 9398810 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
2015-09-25 13:27:03 +02:00
system.cpu0.dtb.hits 21428037 # DTB hits
system.cpu0.dtb.misses 4993 # DTB misses
system.cpu0.dtb.accesses 21433030 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walks 2307 # Table walker walks requested
system.cpu0.itb.walker.walksShort 2307 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples 2307 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0 2307 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 2307 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples 57346094376 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 1.255417 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -14647174874 -25.54% -25.54% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 71993269250 125.54% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 57346094376 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 1275 74.08% 74.08% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 446 25.92% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 1721 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2307 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2307 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1721 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1721 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 4028 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 57257258 # ITB inst hits
system.cpu0.itb.inst_misses 2307 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 352 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu0.itb.flush_entries 1727 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
2015-09-25 13:27:03 +02:00
system.cpu0.itb.inst_accesses 57259565 # ITB inst accesses
system.cpu0.itb.hits 57257258 # DTB hits
system.cpu0.itb.misses 2307 # DTB misses
system.cpu0.itb.accesses 57259565 # DTB accesses
system.cpu0.numCycles 69320920 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu0.committedInsts 55846469 # Number of instructions committed
system.cpu0.committedOps 67799019 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 59476753 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4636 # Number of float alu accesses
system.cpu0.num_func_calls 5739649 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 7404981 # number of instructions that are conditional controls
system.cpu0.num_int_insts 59476753 # number of integer instructions
system.cpu0.num_fp_insts 4636 # number of float instructions
system.cpu0.num_int_register_reads 109855675 # number of times the integer registers were read
system.cpu0.num_int_register_writes 41239490 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3530 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 206363052 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 25211275 # number of times the CC registers were written
system.cpu0.num_mem_refs 21994746 # number of memory refs
system.cpu0.num_load_insts 12174830 # Number of load instructions
system.cpu0.num_store_insts 9819916 # Number of store instructions
system.cpu0.num_idle_cycles 65448484.972740 # Number of idle cycles
system.cpu0.num_busy_cycles 3872435.027260 # Number of busy cycles
system.cpu0.not_idle_fraction 0.055862 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.944138 # Percentage of idle cycles
system.cpu0.Branches 13529823 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2175 0.00% 0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu 46835768 67.99% 67.99% # Class of executed instruction
system.cpu0.op_class::IntMult 49875 0.07% 68.07% # Class of executed instruction
2015-09-15 15:14:09 +02:00
system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu0.op_class::SimdFloatMisc 3855 0.01% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::MemRead 12174830 17.67% 85.74% # Class of executed instruction
system.cpu0.op_class::MemWrite 9819916 14.26% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu0.op_class::total 68886419 # Class of executed instruction
2013-03-01 19:20:30 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 833472 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.996601 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 46054787 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 833984 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 55.222627 # Average number of references to valid blocks.
2014-11-03 17:14:42 +01:00
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.685791 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.479753 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.026378 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.804679 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.936886 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022421 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011770 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028915 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
2014-01-24 22:29:33 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.tags.tag_accesses 193142781 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 193142781 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 11422254 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 3666502 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4281798 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu3.data 6456449 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 25827003 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 9049094 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 2626435 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3309918 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu3.data 3942780 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 18928227 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 169795 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 55205 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74478 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86629 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 386107 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 210372 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75336 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 77039 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 87626 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 450373 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 211678 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 77328 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 79652 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu3.data 91425 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 460083 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 20471348 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 6292937 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7591716 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu3.data 10399229 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 44755230 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 20641143 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 6348142 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7666194 # number of overall hits
system.cpu0.dcache.overall_hits::cpu3.data 10485858 # number of overall hits
system.cpu0.dcache.overall_hits::total 45141337 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 163446 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 56575 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 94619 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu3.data 204651 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 519291 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 128471 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 30419 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 95949 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu3.data 1094862 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1349701 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50858 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17638 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 31597 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu3.data 38338 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 138431 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3927 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2640 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3575 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 7812 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 17954 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 23 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 23 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 291917 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 86994 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 190568 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu3.data 1299513 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1868992 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 342775 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 104632 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 222165 # number of overall misses
system.cpu0.dcache.overall_misses::cpu3.data 1337851 # number of overall misses
system.cpu0.dcache.overall_misses::total 2007423 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 1024208500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1411816500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3682555500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 6118580500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1841305000 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 6494222497 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 77954846454 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 86290373951 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 35655500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49776000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 112749000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 198180500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 799000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 799000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 2865513500 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 7906038997 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu3.data 81637401954 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 92408954451 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 2865513500 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 7906038997 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu3.data 81637401954 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 92408954451 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 11585700 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 3723077 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4376417 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu3.data 6661100 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 26346294 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 9177565 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 2656854 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3405867 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu3.data 5037642 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 20277928 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 220653 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 72843 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 106075 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 124967 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 524538 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 214299 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77976 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 80614 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 95438 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 468327 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 211678 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 77328 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 79652 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 91448 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 460106 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 20763265 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 6379931 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7782284 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu3.data 11698742 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 46624222 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 20983918 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 6452774 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7888359 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu3.data 11823709 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 47148760 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014108 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.015196 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.021620 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.030723 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.019710 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013998 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011449 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.028172 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.217336 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.066560 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.230489 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.242137 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.297874 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.306785 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.263910 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018325 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.033857 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.044347 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.081854 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038336 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000252 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000050 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.014059 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013636 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024487 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu3.data 0.111081 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.040086 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016335 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016215 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.028164 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu3.data 0.113150 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.042576 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18103.552806 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14921.067650 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17994.319598 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 11782.566037 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 60531.411289 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 67684.108193 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 71200.613825 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 63932.955485 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13505.871212 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13923.356643 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14432.795699 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11038.236605 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 34739.130435 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 34739.130435 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 32939.208451 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41486.708141 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 62821.535417 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 49443.204921 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27386.588233 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 35586.338969 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 61021.296059 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 46033.623432 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 512704 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 36990 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 12419 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 546 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.283839 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 67.747253 # average number of cycles each access was blocked
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu0.dcache.writebacks::writebacks 692075 # number of writebacks
system.cpu0.dcache.writebacks::total 692075 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 65 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 15172 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 93547 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 108784 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 43736 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1006705 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1050441 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1618 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2327 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5382 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9327 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 65 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 58908 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu3.data 1100252 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1159225 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 65 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 58908 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu3.data 1100252 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1159225 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 56510 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 79447 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 111104 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 247061 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 30419 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52213 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 88157 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 170789 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 17367 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 21997 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 28240 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 67604 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1022 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1248 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2430 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4700 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 23 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 23 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 86929 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 131660 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu3.data 199261 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 417850 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 104296 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 153657 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu3.data 227501 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 485454 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3591 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5668 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8430 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17689 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2928 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4375 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6667 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13970 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6519 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 10043 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 15097 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31659 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 966240500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1154098000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1729828000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3850166500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810886000 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3506727500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6410528421 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11728141921 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 228034000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 306929500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 499195000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1034158500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 15604000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 21310500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39501500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76416000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 776000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 776000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2777126500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4660825500 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8140356421 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 15578308421 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3005160500 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 4967755000 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8639551421 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 16612466921 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 597998000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1071505000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1718751500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3388254500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 486771500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 812532000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1333957452 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2633260952 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1084769500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1884037000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3052708952 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6021515452 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015178 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018153 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016680 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009377 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011449 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015330 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017500 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008422 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238417 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.207372 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.225980 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.128883 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013107 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015481 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.025462 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010036 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000252 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000050 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013625 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016918 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017033 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.008962 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016163 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019479 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019241 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.010296 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17098.575473 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14526.640402 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15569.448445 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15583.869975 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59531.411289 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67161.961580 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72717.179816 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68670.358870 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13130.304601 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13953.243624 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17676.876771 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15297.297497 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15268.101761 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17075.721154 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16255.761317 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16258.723404 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 33739.130435 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33739.130435 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31947.065996 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35400.467112 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40852.732953 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37282.059162 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28813.765629 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32330.157429 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37975.883275 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34220.475928 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166526.872737 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 189044.636556 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203885.112693 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191545.847702 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166247.096995 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185721.600000 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200083.613619 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188493.983679 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 166401.211842 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 187597.032759 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 202206.329204 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190199.167756 # average overall mshr uncacheable latency
2013-03-01 19:20:30 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.replacements 1975887 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.441259 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 94009429 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1976399 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 47.566017 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12738207000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 433.789749 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 10.948279 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.353975 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu3.inst 39.349255 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.847246 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.021383 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053426 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu3.inst 0.076854 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998909 # Average percentage of cache occupancy
2015-07-30 11:16:36 +02:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
2015-07-30 11:16:36 +02:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.cpu0.icache.tags.tag_accesses 98005721 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 98005721 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 56526239 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 17926561 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 10330491 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu3.inst 9226138 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 94009429 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 56526239 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 17926561 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 10330491 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu3.inst 9226138 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 94009429 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 56526239 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 17926561 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 10330491 # number of overall hits
system.cpu0.icache.overall_hits::cpu3.inst 9226138 # number of overall hits
system.cpu0.icache.overall_hits::total 94009429 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 732740 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 203961 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 495572 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu3.inst 587581 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 2019854 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 732740 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 203961 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 495572 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu3.inst 587581 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 2019854 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 732740 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 203961 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 495572 # number of overall misses
system.cpu0.icache.overall_misses::cpu3.inst 587581 # number of overall misses
system.cpu0.icache.overall_misses::total 2019854 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2885533500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 7058023000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 8404858487 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 18348414987 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2885533500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 7058023000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu3.inst 8404858487 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 18348414987 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2885533500 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 7058023000 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu3.inst 8404858487 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 18348414987 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57258979 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 18130522 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 10826063 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu3.inst 9813719 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 96029283 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 57258979 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 18130522 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 10826063 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu3.inst 9813719 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 96029283 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 57258979 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 18130522 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 10826063 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu3.inst 9813719 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 96029283 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012797 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011250 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045776 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.059873 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.021034 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012797 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011250 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045776 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu3.inst 0.059873 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.021034 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012797 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011250 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045776 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059873 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.021034 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14147.476723 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14242.174699 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 14304.169956 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9084.030324 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14147.476723 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14242.174699 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 14304.169956 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9084.030324 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14147.476723 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14242.174699 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 14304.169956 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9084.030324 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 7750 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu0.icache.blocked::no_mshrs 322 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-09-25 13:27:03 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.068323 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 43415 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 43415 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu3.inst 43415 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 43415 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu3.inst 43415 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 43415 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 203961 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 495572 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544166 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1243699 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 203961 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 495572 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu3.inst 544166 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1243699 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 203961 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 495572 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu3.inst 544166 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1243699 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2681572500 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6562452000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7336863488 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 16580887988 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2681572500 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6562452000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7336863488 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 16580887988 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2681572500 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6562452000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7336863488 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 16580887988 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012951 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.012951 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011250 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045776 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055450 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.012951 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13331.913902 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13147.476723 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13242.176717 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13482.767185 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13331.913902 # average overall mshr miss latency
2014-11-12 15:05:25 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walks 1988 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 1988 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 507 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1481 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walkWaitTime::samples 1988 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0 1988 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 1988 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 1694 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 13442.148760 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 11640.659125 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 7340.460279 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-16383 1298 76.62% 76.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 23.32% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 1694 # Table walker service (enqueue to completion) latency
2015-07-31 18:04:59 +02:00
system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkPageSizes::4K 1189 70.19% 70.19% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 505 29.81% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 1694 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1988 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1988 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1694 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1694 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 3682 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.read_hits 3877487 # DTB read hits
system.cpu1.dtb.read_misses 1782 # DTB read misses
system.cpu1.dtb.write_hits 2737174 # DTB write hits
system.cpu1.dtb.write_misses 206 # DTB write misses
system.cpu1.dtb.flush_tlb 151 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.flush_entries 1170 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.prefetch_faults 242 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 3879269 # DTB read accesses
system.cpu1.dtb.write_accesses 2737380 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
2015-09-25 13:27:03 +02:00
system.cpu1.dtb.hits 6614661 # DTB hits
system.cpu1.dtb.misses 1988 # DTB misses
system.cpu1.dtb.accesses 6616649 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walks 1030 # Table walker walks requested
system.cpu1.itb.walker.walksShort 1030 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 846 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walkWaitTime::samples 1030 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0 1030 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1030 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 746 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 12997.319035 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 11244.232149 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 6525.015841 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-6143 210 28.15% 28.15% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.13% 28.28% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::10240-12287 183 24.53% 52.82% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-14335 68 9.12% 61.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::14336-16383 130 17.43% 79.36% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::22528-24575 152 20.38% 99.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-26623 2 0.27% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 746 # Table walker service (enqueue to completion) latency
2015-07-31 18:04:59 +02:00
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkPageSizes::4K 562 75.34% 75.34% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 184 24.66% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 746 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1030 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1030 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 746 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 746 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 1776 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 18130522 # ITB inst hits
system.cpu1.itb.inst_misses 1030 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu1.itb.flush_tlb 151 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 141 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu1.itb.flush_entries 779 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
2015-09-25 13:27:03 +02:00
system.cpu1.itb.inst_accesses 18131552 # ITB inst accesses
system.cpu1.itb.hits 18130522 # DTB hits
system.cpu1.itb.misses 1030 # DTB misses
system.cpu1.itb.accesses 18131552 # DTB accesses
system.cpu1.numCycles 144010279 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu1.committedInsts 17464166 # Number of instructions committed
system.cpu1.committedOps 20951836 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 18623353 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1244 # Number of float alu accesses
system.cpu1.num_func_calls 2002453 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 2238605 # number of instructions that are conditional controls
system.cpu1.num_int_insts 18623353 # number of integer instructions
system.cpu1.num_fp_insts 1244 # number of float instructions
system.cpu1.num_int_register_reads 34462753 # number of times the integer registers were read
system.cpu1.num_int_register_writes 13064497 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 984 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 260 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 76266638 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 7592351 # number of times the CC registers were written
system.cpu1.num_mem_refs 6809095 # number of memory refs
system.cpu1.num_load_insts 3920028 # Number of load instructions
system.cpu1.num_store_insts 2889067 # Number of store instructions
system.cpu1.num_idle_cycles 136641410.332873 # Number of idle cycles
system.cpu1.num_busy_cycles 7368868.667127 # Number of busy cycles
system.cpu1.not_idle_fraction 0.051169 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.948831 # Percentage of idle cycles
system.cpu1.Branches 4354761 # Number of branches fetched
system.cpu1.op_class::No_OpClass 27 0.00% 0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu 14731476 68.33% 68.33% # Class of executed instruction
system.cpu1.op_class::IntMult 16530 0.08% 68.41% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 936 0.00% 68.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.42% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.42% # Class of executed instruction
system.cpu1.op_class::MemRead 3920028 18.18% 86.60% # Class of executed instruction
system.cpu1.op_class::MemWrite 2889067 13.40% 100.00% # Class of executed instruction
2014-05-10 00:58:50 +02:00
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
2015-09-25 13:27:03 +02:00
system.cpu1.op_class::total 21558064 # Class of executed instruction
2013-03-01 19:20:30 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
2015-09-25 13:27:03 +02:00
system.cpu2.branchPred.lookups 5764695 # Number of BP lookups
system.cpu2.branchPred.condPredicted 2966106 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 506808 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3301109 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2388086 # Number of BTB hits
2013-03-01 19:20:30 +01:00
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-25 13:27:03 +02:00
system.cpu2.branchPred.BTBHitPct 72.341931 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 1613052 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 330539 # Number of incorrect RAS predictions.
2014-12-23 15:31:20 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.walker.walks 12898 # Table walker walks requested
system.cpu2.dtb.walker.walksShort 12898 # Table walker walks initiated with short descriptors
system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8122 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4776 # Level at which table walker walks with short descriptors terminate
system.cpu2.dtb.walker.walkWaitTime::samples 12898 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::0 12898 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkWaitTime::total 12898 # Table walker wait (enqueue to first request) latency
system.cpu2.dtb.walker.walkCompletionTime::samples 2175 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::mean 12233.103448 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::gmean 10576.406558 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::stdev 6350.387588 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::2048-4095 16 0.74% 0.74% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::4096-6143 627 28.83% 29.56% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::6144-8191 3 0.14% 29.70% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::10240-12287 777 35.72% 65.43% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::12288-14335 187 8.60% 74.02% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::14336-16383 174 8.00% 82.02% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::22528-24575 386 17.75% 99.77% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::24576-26623 5 0.23% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::total 2175 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution
system.cpu2.dtb.walker.walkPageSizes::4K 1361 62.57% 62.57% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::1M 814 37.43% 100.00% # Table walker page sizes translated
system.cpu2.dtb.walker.walkPageSizes::total 2175 # Table walker page sizes translated
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12898 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12898 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2175 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2175 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin::total 15073 # Table walker requests started/completed, data/inst
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.read_hits 4607133 # DTB read hits
system.cpu2.dtb.read_misses 11539 # DTB read misses
system.cpu2.dtb.write_hits 3514721 # DTB write hits
system.cpu2.dtb.write_misses 1359 # DTB write misses
system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.flush_entries 1512 # Number of entries that have been flushed from TLB
2015-09-15 15:14:09 +02:00
system.cpu2.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.perms_faults 112 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 4618672 # DTB read accesses
system.cpu2.dtb.write_accesses 3516080 # DTB write accesses
2013-03-01 19:20:30 +01:00
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
2015-09-25 13:27:03 +02:00
system.cpu2.dtb.hits 8121854 # DTB hits
system.cpu2.dtb.misses 12898 # DTB misses
system.cpu2.dtb.accesses 8134752 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu2.itb.walker.walks 1355 # Table walker walks requested
system.cpu2.itb.walker.walksShort 1355 # Table walker walks initiated with short descriptors
system.cpu2.itb.walker.walksShortTerminationLevel::Level1 252 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1103 # Level at which table walker walks with short descriptors terminate
system.cpu2.itb.walker.walkWaitTime::samples 1355 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::0 1355 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkWaitTime::total 1355 # Table walker wait (enqueue to first request) latency
system.cpu2.itb.walker.walkCompletionTime::samples 885 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::mean 12701.694915 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::gmean 10970.308006 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::stdev 6476.484391 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::4096-6143 261 29.49% 29.49% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::10240-12287 244 27.57% 57.06% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::12288-14335 68 7.68% 64.75% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::14336-16383 134 15.14% 79.89% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::22528-24575 177 20.00% 99.89% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.11% 100.00% # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walkCompletionTime::total 885 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution
system.cpu2.itb.walker.walkPageSizes::4K 640 72.32% 72.32% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::1M 245 27.68% 100.00% # Table walker page sizes translated
system.cpu2.itb.walker.walkPageSizes::total 885 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1355 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1355 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 885 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::total 885 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin::total 2240 # Table walker requests started/completed, data/inst
system.cpu2.itb.inst_hits 10827992 # ITB inst hits
system.cpu2.itb.inst_misses 1355 # ITB inst misses
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
2014-10-30 05:18:29 +01:00
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu2.itb.flush_entries 895 # Number of entries that have been flushed from TLB
2013-03-01 19:20:30 +01:00
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu2.itb.perms_faults 1816 # Number of TLB faults due to permissions restrictions
2013-03-01 19:20:30 +01:00
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
2015-09-25 13:27:03 +02:00
system.cpu2.itb.inst_accesses 10829347 # ITB inst accesses
system.cpu2.itb.hits 10827992 # DTB hits
system.cpu2.itb.misses 1355 # DTB misses
system.cpu2.itb.accesses 10829347 # DTB accesses
system.cpu2.numCycles 1394813628 # number of cpu cycles simulated
2013-03-01 19:20:30 +01:00
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu2.committedInsts 20299204 # Number of instructions committed
system.cpu2.committedOps 24561296 # Number of ops (including micro ops) committed
system.cpu2.discardedOps 1454329 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 560 # Number of times Execute suspended instruction fetching
system.cpu2.quiesceCycles 4254632682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.cpi 68.712725 # CPI: cycles per instruction
system.cpu2.ipc 0.014553 # IPC: instructions per cycle
2015-07-30 11:16:36 +02:00
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
2015-09-25 13:27:03 +02:00
system.cpu2.tickCycles 42192180 # Number of cycles that the object actually ticked
system.cpu2.idleCycles 1352621448 # Total number of cycles that the object has spent stopped
system.cpu3.branchPred.lookups 13267477 # Number of BP lookups
system.cpu3.branchPred.condPredicted 7218148 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 306932 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 7331192 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 6244117 # Number of BTB hits
2015-07-30 11:16:36 +02:00
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-09-25 13:27:03 +02:00
system.cpu3.branchPred.BTBHitPct 85.171920 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 3106613 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 16022 # Number of incorrect RAS predictions.
2015-07-30 11:16:36 +02:00
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.walker.walks 32594 # Table walker walks requested
system.cpu3.dtb.walker.walksShort 32594 # Table walker walks initiated with short descriptors
system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11131 # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7720 # Level at which table walker walks with short descriptors terminate
system.cpu3.dtb.walker.walksSquashedBefore 13743 # Table walks squashed before starting
system.cpu3.dtb.walker.walkWaitTime::samples 18851 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::mean 550.607395 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::stdev 4115.669871 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::0-16383 18669 99.03% 99.03% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::16384-32767 132 0.70% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::32768-49151 28 0.15% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::49152-65535 10 0.05% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::65536-81919 5 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::98304-114687 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::114688-131071 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::total 18851 # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkCompletionTime::samples 6073 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::mean 12561.337066 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::gmean 10324.019552 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::stdev 7892.573788 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::0-16383 4743 78.10% 78.10% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1245 20.50% 98.60% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::32768-49151 80 1.32% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.93% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.95% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walkCompletionTime::total 6073 # Table walker service (enqueue to completion) latency
system.cpu3.dtb.walker.walksPending::samples -8078927064 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::mean 0.145347 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::stdev 0.140537 # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::0-1 -8125083564 100.57% 100.57% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::2-3 32811500 -0.41% 100.17% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::4-5 7062500 -0.09% 100.08% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::6-7 2662500 -0.03% 100.04% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::8-9 1263000 -0.02% 100.03% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::10-11 812000 -0.01% 100.02% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::12-13 353000 -0.00% 100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::14-15 734000 -0.01% 100.01% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::16-17 142000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::18-19 166000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::20-21 33500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::22-23 14500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::24-25 66000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::26-27 5000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::30-31 27500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.dtb.walker.walksPending::total -8078927064 # Table walker pending requests distribution
system.cpu3.dtb.walker.walkPageSizes::4K 1773 69.37% 69.37% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::1M 783 30.63% 100.00% # Table walker page sizes translated
system.cpu3.dtb.walker.walkPageSizes::total 2556 # Table walker page sizes translated
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 32594 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 32594 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2556 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2556 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin::total 35150 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.read_hits 7207975 # DTB read hits
system.cpu3.dtb.read_misses 28184 # DTB read misses
system.cpu3.dtb.write_hits 5370312 # DTB write hits
system.cpu3.dtb.write_misses 4410 # DTB write misses
system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.flush_entries 1876 # Number of entries that have been flushed from TLB
system.cpu3.dtb.align_faults 480 # Number of TLB faults due to alignment restrictions
system.cpu3.dtb.prefetch_faults 811 # Number of TLB faults due to prefetch
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.perms_faults 348 # Number of TLB faults due to permissions restrictions
system.cpu3.dtb.read_accesses 7236159 # DTB read accesses
system.cpu3.dtb.write_accesses 5374722 # DTB write accesses
2015-07-30 11:16:36 +02:00
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
2015-09-25 13:27:03 +02:00
system.cpu3.dtb.hits 12578287 # DTB hits
system.cpu3.dtb.misses 32594 # DTB misses
system.cpu3.dtb.accesses 12610881 # DTB accesses
2015-07-30 11:16:36 +02:00
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu3.itb.walker.walks 4409 # Table walker walks requested
system.cpu3.itb.walker.walksShort 4409 # Table walker walks initiated with short descriptors
system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1513 # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2804 # Level at which table walker walks with short descriptors terminate
system.cpu3.itb.walker.walksSquashedBefore 92 # Table walks squashed before starting
system.cpu3.itb.walker.walkWaitTime::samples 4317 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::mean 1474.635163 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::stdev 6438.514221 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::0-8191 4058 94.00% 94.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.59% 96.59% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::16384-24575 78 1.81% 98.40% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::24576-32767 36 0.83% 99.24% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.28% 99.51% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.14% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::49152-57343 4 0.09% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.09% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::81920-90111 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::total 4317 # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkCompletionTime::samples 1329 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::mean 13040.632054 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::gmean 10790.250081 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::stdev 7776.712895 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.81% 1.81% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 30.32% 32.13% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::8192-12287 359 27.01% 59.14% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::12288-16383 209 15.73% 74.87% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::16384-20479 19 1.43% 76.30% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::20480-24575 282 21.22% 97.52% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::24576-28671 11 0.83% 98.34% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::28672-32767 1 0.08% 98.42% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::36864-40959 9 0.68% 99.17% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::40960-45055 7 0.53% 99.70% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.23% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::total 1329 # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walksPending::samples -8082078064 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::mean 1.066049 # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::0 536728704 -6.64% -6.64% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::1 -8620989268 106.67% 100.03% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::2 1669000 -0.02% 100.01% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::3 344000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::4 120000 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::5 49500 -0.00% 100.00% # Table walker pending requests distribution
system.cpu3.itb.walker.walksPending::total -8082078064 # Table walker pending requests distribution
system.cpu3.itb.walker.walkPageSizes::4K 894 72.27% 72.27% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::1M 343 27.73% 100.00% # Table walker page sizes translated
system.cpu3.itb.walker.walkPageSizes::total 1237 # Table walker page sizes translated
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4409 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4409 # Table walker requests started/completed, data/inst
2015-07-30 11:16:36 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1237 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1237 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin::total 5646 # Table walker requests started/completed, data/inst
system.cpu3.itb.inst_hits 9814748 # ITB inst hits
system.cpu3.itb.inst_misses 4409 # ITB inst misses
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA
2015-07-30 11:16:36 +02:00
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu3.itb.flush_entries 1248 # Number of entries that have been flushed from TLB
2015-07-30 11:16:36 +02:00
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-09-25 13:27:03 +02:00
system.cpu3.itb.perms_faults 724 # Number of TLB faults due to permissions restrictions
2015-07-30 11:16:36 +02:00
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
2015-09-25 13:27:03 +02:00
system.cpu3.itb.inst_accesses 9819157 # ITB inst accesses
system.cpu3.itb.hits 9814748 # DTB hits
system.cpu3.itb.misses 4409 # DTB misses
system.cpu3.itb.accesses 9819157 # DTB accesses
system.cpu3.numCycles 57366661 # number of cpu cycles simulated
2015-07-30 11:16:36 +02:00
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-09-25 13:27:03 +02:00
system.cpu3.fetch.icacheStallCycles 20761268 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 52178877 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 13267477 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 9350730 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 33698249 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 1591212 # Number of cycles fetch has spent squashing
system.cpu3.fetch.TlbCycles 69410 # Number of cycles fetch has spent waiting for tlb
system.cpu3.fetch.MiscStallCycles 1107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.PendingDrainCycles 256 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu3.fetch.PendingTrapStallCycles 135306 # Number of stall cycles due to pending traps
system.cpu3.fetch.PendingQuiesceStallCycles 74302 # Number of stall cycles due to pending quiesce instructions
system.cpu3.fetch.IcacheWaitRetryStallCycles 555 # Number of stall cycles due to full MSHR
system.cpu3.fetch.CacheLines 9813722 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 210476 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.ItlbSquashes 2135 # Number of outstanding ITLB misses that were squashed
system.cpu3.fetch.rateDist::samples 55536037 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.135538 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.278414 # Number of instructions fetched each cycle (Total)
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu3.fetch.rateDist::0 41384973 74.52% 74.52% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 1837710 3.31% 77.83% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 1169547 2.11% 79.93% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3702482 6.67% 86.60% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 911101 1.64% 88.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 554699 1.00% 89.24% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 2918405 5.25% 94.50% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 606250 1.09% 95.59% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 2450870 4.41% 100.00% # Number of instructions fetched each cycle (Total)
2015-07-30 11:16:36 +02:00
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
2015-09-25 13:27:03 +02:00
system.cpu3.fetch.rateDist::total 55536037 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.231275 # Number of branch fetches per cycle
system.cpu3.fetch.rate 0.909568 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 14514304 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 31619877 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 7786036 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 908366 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 707244 # Number of cycles decode is squashing
system.cpu3.decode.BranchResolved 976635 # Number of times decode resolved a branch
system.cpu3.decode.BranchMispred 89470 # Number of times decode detected a branch misprediction
system.cpu3.decode.DecodedInsts 44785495 # Number of instructions handled by decode
system.cpu3.decode.SquashedInsts 293014 # Number of squashed instructions handled by decode
system.cpu3.rename.SquashCycles 707244 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 15002070 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 3712166 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 21623767 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 8198323 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 6292235 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 42920389 # Number of instructions processed by rename
system.cpu3.rename.ROBFullEvents 988 # Number of times rename has blocked due to ROB full
system.cpu3.rename.IQFullEvents 999285 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LQFullEvents 100726 # Number of times rename has blocked due to LQ full
system.cpu3.rename.SQFullEvents 4827959 # Number of times rename has blocked due to SQ full
system.cpu3.rename.RenamedOperands 44612381 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 197148279 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 47945794 # Number of integer rename lookups
system.cpu3.rename.fp_rename_lookups 3725 # Number of floating rename lookups
system.cpu3.rename.CommittedMaps 37230904 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 7381477 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 716136 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 666620 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 5136604 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 7692057 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 5940620 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 1092936 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 1536247 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 41290259 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 501894 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 39299013 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 52056 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 5966024 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 13660779 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 53087 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 55536037 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 0.707631 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.411142 # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-09-25 13:27:03 +02:00
system.cpu3.iq.issued_per_cycle::0 39933168 71.90% 71.90% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 5154759 9.28% 81.19% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 3998218 7.20% 88.39% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 3241689 5.84% 94.22% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 1260306 2.27% 96.49% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 769738 1.39% 97.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 826217 1.49% 99.37% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 240001 0.43% 99.80% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 111941 0.20% 100.00% # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
2015-09-25 13:27:03 +02:00
system.cpu3.iq.issued_per_cycle::total 55536037 # Number of insts issued each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu3.iq.fu_full::IntAlu 56634 9.59% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.59% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 279182 47.28% 56.87% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 254722 43.13% 100.00% # attempts to use FU when none available
2015-07-30 11:16:36 +02:00
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu3.iq.FU_type_0::No_OpClass 79 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 26205156 66.68% 66.68% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 29936 0.08% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 2339 0.01% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.76% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 7421328 18.88% 85.65% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 5640175 14.35% 100.00% # Type of FU issued
2015-07-30 11:16:36 +02:00
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu3.iq.FU_type_0::total 39299013 # Type of FU issued
system.cpu3.iq.rate 0.685050 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 590538 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.015027 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 134768668 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 47782568 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 38141743 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 7989 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 4328 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 3477 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 39885201 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 4271 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 170012 # Number of loads that had data forwarded from stores
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-09-25 13:27:03 +02:00
system.cpu3.iew.lsq.thread0.squashedLoads 1165546 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 1325 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 29357 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 600603 # Number of stores squashed
2015-07-30 11:16:36 +02:00
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-09-25 13:27:03 +02:00
system.cpu3.iew.lsq.thread0.rescheduledLoads 108801 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 44606 # Number of times an access to memory failed due to the cache being blocked
2015-07-30 11:16:36 +02:00
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-09-25 13:27:03 +02:00
system.cpu3.iew.iewSquashCycles 707244 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 3069413 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 520763 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 41839488 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 76423 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 7692057 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 5940620 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 259410 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 22603 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 492210 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 29357 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 139025 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 123161 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 262186 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 38971879 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 7290710 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 294612 # Number of squashed instructions skipped in execute
2015-07-30 11:16:36 +02:00
system.cpu3.iew.exec_swp 0 # number of swp insts executed
2015-09-25 13:27:03 +02:00
system.cpu3.iew.exec_nop 47335 # number of nop insts executed
system.cpu3.iew.exec_refs 12872001 # number of memory reference insts executed
system.cpu3.iew.exec_branches 7242885 # Number of branches executed
system.cpu3.iew.exec_stores 5581291 # Number of stores executed
system.cpu3.iew.exec_rate 0.679347 # Inst execution rate
system.cpu3.iew.wb_sent 38686705 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 38145220 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 19984457 # num instructions producing a value
system.cpu3.iew.wb_consumers 34832102 # num instructions consuming a value
2015-07-30 11:16:36 +02:00
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2015-09-25 13:27:03 +02:00
system.cpu3.iew.wb_rate 0.664937 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.573737 # average fanout of values written-back
2015-07-30 11:16:36 +02:00
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2015-09-25 13:27:03 +02:00
system.cpu3.commit.commitSquashedInsts 5981270 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 448807 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 218548 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 54250638 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 0.660854 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 1.552983 # Number of insts commited each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-09-25 13:27:03 +02:00
system.cpu3.commit.committed_per_cycle::0 40430906 74.53% 74.53% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 6113695 11.27% 85.80% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 3127574 5.77% 91.56% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 1326177 2.44% 94.01% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 716812 1.32% 95.33% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 505346 0.93% 96.26% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 950559 1.75% 98.01% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 229517 0.42% 98.43% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 850052 1.57% 100.00% # Number of insts commited each cycle
2015-07-30 11:16:36 +02:00
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-09-25 13:27:03 +02:00
system.cpu3.commit.committed_per_cycle::total 54250638 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 29358701 # Number of instructions committed
system.cpu3.commit.committedOps 35851741 # Number of ops (including micro ops) committed
2015-07-30 11:16:36 +02:00
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
2015-09-25 13:27:03 +02:00
system.cpu3.commit.refs 11866528 # Number of memory references committed
system.cpu3.commit.loads 6526511 # Number of loads committed
system.cpu3.commit.membars 173804 # Number of memory barriers committed
system.cpu3.commit.branches 6837387 # Number of branches committed
system.cpu3.commit.fp_insts 3456 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 31324780 # Number of committed integer instructions.
system.cpu3.commit.function_calls 1241793 # Number of function calls committed.
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu3.commit.op_class_0::IntAlu 23953965 66.81% 66.81% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 28909 0.08% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.89% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 2339 0.01% 66.90% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.90% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.90% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.90% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 6526511 18.20% 85.11% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 5340017 14.89% 100.00% # Class of committed instruction
2015-07-30 11:16:36 +02:00
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu3.commit.op_class_0::total 35851741 # Class of committed instruction
system.cpu3.commit.bw_lim_events 850052 # number cycles where commit BW limit reached
system.cpu3.rob.rob_reads 89574127 # The number of ROB reads
system.cpu3.rob.rob_writes 84953819 # The number of ROB writes
system.cpu3.timesIdled 222816 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1830624 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 5161214707 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 29333089 # Number of Instructions Simulated
system.cpu3.committedOps 35826129 # Number of Ops (including micro ops) Simulated
system.cpu3.cpi 1.955698 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 1.955698 # CPI: Total CPI of All Threads
system.cpu3.ipc 0.511326 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 0.511326 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 42472744 # number of integer regfile reads
system.cpu3.int_regfile_writes 24152717 # number of integer regfile writes
system.cpu3.fp_regfile_reads 14290 # number of floating regfile reads
system.cpu3.fp_regfile_writes 12064 # number of floating regfile writes
system.cpu3.cc_regfile_reads 137731283 # number of cc regfile reads
system.cpu3.cc_regfile_writes 14845540 # number of cc regfile writes
system.cpu3.misc_regfile_reads 75477983 # number of misc regfile reads
system.cpu3.misc_regfile_writes 336291 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
system.iobus.trans_dist::WriteResp 59010 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 22360000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-07-30 11:16:36 +02:00
system.iobus.reqLayer16.occupancy 32000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer23.occupancy 3278000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer24.occupancy 84000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer25.occupancy 19060000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer26.occupancy 90000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.reqLayer27.occupancy 78461015 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer0.occupancy 48730000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.iocache.tags.replacements 36409 # number of replacements
system.iocache.tags.tagsinuse 1.005075 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 249186259009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005075 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062817 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062817 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-09-25 13:27:03 +02:00
system.iocache.tags.tag_accesses 328227 # Number of tag accesses
system.iocache.tags.data_accesses 328227 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 17563919 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 17563919 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 1966288096 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 1966288096 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 17563919 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 17563919 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 17563919 # number of overall miss cycles
system.iocache.overall_miss_latency::total 17563919 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-09-25 13:27:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-09-25 13:27:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 70537.827309 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 70537.827309 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54324.854151 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 54324.854151 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 70537.827309 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 70537.827309 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 70537.827309 # average overall miss latency
2015-07-03 16:15:03 +02:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-07-03 16:15:03 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2013-03-01 19:20:30 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2013-03-01 19:20:30 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-09-25 13:27:03 +02:00
system.iocache.writebacks::writebacks 36160 # number of writebacks
system.iocache.writebacks::total 36160 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 10163919 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 10163919 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1206938096 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 1206938096 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 10163919 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 10163919 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 10163919 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 10163919 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68675.128378 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68675.128378 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79471.791401 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79471.791401 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68675.128378 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68675.128378 # average overall mshr miss latency
2013-03-01 19:20:30 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.l2c.tags.replacements 103711 # number of replacements
system.l2c.tags.tagsinuse 65095.024716 # Cycle average of tags in use
system.l2c.tags.total_refs 5145934 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 168963 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 30.455981 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 80077044000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 48951.707616 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.971864 # Average occupied blocks per requestor
2014-11-12 15:05:25 +01:00
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_blocks::cpu0.inst 4249.334624 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2262.984305 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967017 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 905.000363 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 870.835112 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.993332 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 2120.702185 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 746.628994 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.dtb.walker 47.189745 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 3231.570243 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 1686.139222 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.746944 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
2015-09-25 13:27:03 +02:00
system.l2c.tags.occ_percent::cpu0.inst 0.064840 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.034530 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.013809 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.013288 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000320 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.032359 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.011393 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000720 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.049310 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.025728 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.993271 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 64 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2120 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55295 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 45476650 # Number of tag accesses
system.l2c.tags.data_accesses 45476650 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 4171 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 2069 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 1847 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 966 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 13780 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 1202 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.dtb.walker 20190 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.itb.walker 4342 # number of ReadReq hits
system.l2c.ReadReq_hits::total 48567 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 692075 # number of Writeback hits
system.l2c.Writeback_hits::total 692075 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3.data 39 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 63 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 16 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 67281 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 18043 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 27363 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3.data 44025 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 156712 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 724916 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 202055 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 490576 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu3.inst 537675 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 1955222 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 212249 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 72337 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu2.data 100704 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu3.data 137491 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 522781 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 4171 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 2069 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 724916 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 279530 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 1847 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 966 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 202055 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 90380 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 13780 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 1202 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 490576 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 128067 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.dtb.walker 20190 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.itb.walker 4342 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 537675 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 181516 # number of demand (read+write) hits
system.l2c.demand_hits::total 2683282 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 4171 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 2069 # number of overall hits
system.l2c.overall_hits::cpu0.inst 724916 # number of overall hits
system.l2c.overall_hits::cpu0.data 279530 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 1847 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 966 # number of overall hits
system.l2c.overall_hits::cpu1.inst 202055 # number of overall hits
system.l2c.overall_hits::cpu1.data 90380 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 13780 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 1202 # number of overall hits
system.l2c.overall_hits::cpu2.inst 490576 # number of overall hits
system.l2c.overall_hits::cpu2.data 128067 # number of overall hits
system.l2c.overall_hits::cpu3.dtb.walker 20190 # number of overall hits
system.l2c.overall_hits::cpu3.itb.walker 4342 # number of overall hits
system.l2c.overall_hits::cpu3.inst 537675 # number of overall hits
system.l2c.overall_hits::cpu3.data 181516 # number of overall hits
system.l2c.overall_hits::total 2683282 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses
2014-11-12 15:05:25 +01:00
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.dtb.walker 63 # number of ReadReq misses
system.l2c.ReadReq_misses::total 99 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1105 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 396 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 537 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 746 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2784 # number of UpgradeReq misses
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_misses::cpu3.data 7 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses
2015-09-25 13:27:03 +02:00
system.l2c.ReadExReq_misses::cpu0.data 60075 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 11977 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 24303 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 43355 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 139710 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 7818 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 1903 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu2.inst 4985 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu3.inst 6392 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 21098 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 5982 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 2562 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu2.data 1987 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu3.data 4275 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 14806 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses
2014-11-12 15:05:25 +01:00
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2015-09-25 13:27:03 +02:00
system.l2c.demand_misses::cpu0.inst 7818 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 66057 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1903 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 14539 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 4985 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 26290 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.dtb.walker 63 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 6392 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 47630 # number of demand (read+write) misses
system.l2c.demand_misses::total 175713 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses
2014-11-12 15:05:25 +01:00
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
2015-09-25 13:27:03 +02:00
system.l2c.overall_misses::cpu0.inst 7818 # number of overall misses
system.l2c.overall_misses::cpu0.data 66057 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1903 # number of overall misses
system.l2c.overall_misses::cpu1.data 14539 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses
system.l2c.overall_misses::cpu2.inst 4985 # number of overall misses
system.l2c.overall_misses::cpu2.data 26290 # number of overall misses
system.l2c.overall_misses::cpu3.dtb.walker 63 # number of overall misses
system.l2c.overall_misses::cpu3.inst 6392 # number of overall misses
system.l2c.overall_misses::cpu3.data 47630 # number of overall misses
system.l2c.overall_misses::total 175713 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 4492500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 8441000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 13066000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 161500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 484000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3.data 645000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1290500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 402500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 402500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 1543781500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 3095614000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 5747667500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10387063000 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 249498000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu2.inst 658893500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu3.inst 855999500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 1764391000 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 336746000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu2.data 262865000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu3.data 588294000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 1187905000 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 249498000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 1880527500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 4492500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 658893500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 3358479000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.dtb.walker 8441000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 855999500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 6335961500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 13352425000 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 249498000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 1880527500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 4492500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 658893500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 3358479000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.dtb.walker 8441000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 855999500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 6335961500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 13352425000 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4174 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 2070 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 1848 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 966 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 13811 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 1202 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.dtb.walker 20253 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.itb.walker 4342 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 48666 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 692075 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 692075 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1115 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 399 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 548 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 785 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2847 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data 23 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 23 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 127356 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 30020 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 51666 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 87380 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 296422 # number of ReadExReq accesses(hits+misses)
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system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992481 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.979927 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 0.950318 # miss rate for UpgradeReq accesses
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2014-11-12 15:05:25 +01:00
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2015-09-25 13:27:03 +02:00
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2015-07-30 11:16:36 +02:00
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2015-09-25 13:27:03 +02:00
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2015-09-15 15:14:09 +02:00
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2015-09-25 13:27:03 +02:00
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2015-07-30 11:16:36 +02:00
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2015-09-25 13:27:03 +02:00
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2015-09-15 15:14:09 +02:00
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2015-09-25 13:27:03 +02:00
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2015-07-30 11:16:36 +02:00
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2015-09-25 13:27:03 +02:00
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2015-09-15 15:14:09 +02:00
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2015-09-25 13:27:03 +02:00
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2015-09-15 15:14:09 +02:00
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2015-09-25 13:27:03 +02:00
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system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 230468000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 608913000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 791511500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 1630892500 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 311126000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 240626500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 541295500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 1093048000 # number of ReadSharedReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 230468000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1735137500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4182500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 608913000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 3093210500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 7811000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 791511500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 5855413000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 12326769500 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 230468000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1735137500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4182500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 608913000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 3093210500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 7811000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 791511500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 5855413000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 12326769500 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 553110500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1000651500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1613374500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 3167136500 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 453099500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 762218000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1257223000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 2472540500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1006210000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1762869500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2870597500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 5639677000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000541 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002245 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003111 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992481 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.979927 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.950318 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.589744 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.304348 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.304348 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.398967 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.470387 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.496166 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.268654 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006716 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.034206 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019155 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.029880 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016304 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000541 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.138574 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002245 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.170190 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003111 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.207689 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.035595 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000541 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009330 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.138574 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002245 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010053 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.170190 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003111 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011739 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.207689 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.035595 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 127536.842105 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70780.303030 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 70757.914339 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 70764.075067 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70765.932102 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 70928.571429 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70928.571429 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118895.508057 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117375.797227 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122572.194672 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 120433.389841 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122882.195600 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121438.719750 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 122331.723437 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127784.584514 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124705.989732 # average ReadSharedReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119343.661875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117746.878569 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 123036.141287 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 121127.374296 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121107.724645 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119343.661875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 134919.354839 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122222.601365 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117746.878569 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 123984.126984 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123925.395334 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 123036.141287 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 121127.374296 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154026.872737 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 176544.019054 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 191384.875445 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 179045.536774 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154747.096995 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 174221.257143 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188574.021299 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 176989.298497 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 154350.360485 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175532.161705 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 190143.571571 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 178138.191352 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2015-07-30 11:16:36 +02:00
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadResp 76298 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::Writeback 131166 # Transaction distribution
system.membus.trans_dist::CleanEvict 8718 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::UpgradeResp 4555 # Transaction distribution
system.membus.trans_dist::ReadExReq 137947 # Transaction distribution
system.membus.trans_dist::ReadExResp 137947 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 36184 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 488332 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 595784 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108913 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108913 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 704697 # Packet count per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
2015-07-30 11:16:36 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17254780 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 17417905 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19738609 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 305 # Total snoops (count)
system.membus.snoop_fanout::samples 422679 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::1 422679 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.membus.snoop_fanout::total 422679 # Request fanout histogram
system.membus.reqLayer0.occupancy 54961500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.reqLayer2.occupancy 673000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.reqLayer5.occupancy 481696064 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.respLayer2.occupancy 584907455 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.membus.respLayer3.occupancy 27319765 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-09-15 15:14:09 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.tot_requests 5650262 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 2839838 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 45471 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 619 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 619 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 112063 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2626235 # Transaction distribution
2015-07-30 11:16:36 +02:00
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.toL2Bus.trans_dist::Writeback 760987 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2076983 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 2848 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 23 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 2870 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296422 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296422 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1976439 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 537735 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5908570 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617393 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26301 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100850 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 8653114 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126520888 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97861689 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42712 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 178096 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 224603385 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 193657 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 5938870 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.020066 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.140226 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::0 5819701 97.99% 97.99% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 119169 2.01% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 5938870 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2186534999 # Layer occupancy (ticks)
2015-07-03 16:15:03 +02:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer0.occupancy 1866037017 # Layer occupancy (ticks)
2015-07-30 11:16:36 +02:00
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer1.occupancy 758288292 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer2.occupancy 11457495 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-09-25 13:27:03 +02:00
system.toL2Bus.respLayer3.occupancy 47843740 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-30 11:16:36 +02:00
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
2013-03-01 19:20:30 +01:00
---------- End Simulation Statistics ----------
