2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2016-08-12 15:12:59 +02:00
sim_seconds 51.558015 # Number of seconds simulated
sim_ticks 51558014828000 # Number of ticks simulated
final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2016-08-12 15:12:59 +02:00
host_inst_rate 133865 # Simulator instruction rate (inst/s)
host_op_rate 157345 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6235119796 # Simulator tick rate (ticks/s)
host_mem_usage 696436 # Number of bytes of host memory used
host_seconds 8268.97 # Real time elapsed on the host
sim_insts 1106923026 # Number of instructions simulated
sim_ops 1301083589 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory
system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2016-08-12 15:12:59 +02:00
system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2016-08-12 15:12:59 +02:00
system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1904301 # Number of read requests accepted
system.physmem.writeReqs 2205028 # Number of write requests accepted
system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue
system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
2016-08-12 15:12:59 +02:00
system.physmem.perBankRdBursts::0 114327 # Per bank write bursts
system.physmem.perBankRdBursts::1 123692 # Per bank write bursts
system.physmem.perBankRdBursts::2 118245 # Per bank write bursts
system.physmem.perBankRdBursts::3 117057 # Per bank write bursts
system.physmem.perBankRdBursts::4 115229 # Per bank write bursts
system.physmem.perBankRdBursts::5 125268 # Per bank write bursts
system.physmem.perBankRdBursts::6 115683 # Per bank write bursts
system.physmem.perBankRdBursts::7 119593 # Per bank write bursts
system.physmem.perBankRdBursts::8 115543 # Per bank write bursts
system.physmem.perBankRdBursts::9 144676 # Per bank write bursts
system.physmem.perBankRdBursts::10 112600 # Per bank write bursts
system.physmem.perBankRdBursts::11 120122 # Per bank write bursts
system.physmem.perBankRdBursts::12 113965 # Per bank write bursts
system.physmem.perBankRdBursts::13 118266 # Per bank write bursts
system.physmem.perBankRdBursts::14 113146 # Per bank write bursts
system.physmem.perBankRdBursts::15 116309 # Per bank write bursts
system.physmem.perBankWrBursts::0 135142 # Per bank write bursts
system.physmem.perBankWrBursts::1 141643 # Per bank write bursts
system.physmem.perBankWrBursts::2 136917 # Per bank write bursts
system.physmem.perBankWrBursts::3 137997 # Per bank write bursts
system.physmem.perBankWrBursts::4 135684 # Per bank write bursts
system.physmem.perBankWrBursts::5 143871 # Per bank write bursts
system.physmem.perBankWrBursts::6 135153 # Per bank write bursts
system.physmem.perBankWrBursts::7 138864 # Per bank write bursts
system.physmem.perBankWrBursts::8 135935 # Per bank write bursts
system.physmem.perBankWrBursts::9 142790 # Per bank write bursts
system.physmem.perBankWrBursts::10 134947 # Per bank write bursts
system.physmem.perBankWrBursts::11 140191 # Per bank write bursts
system.physmem.perBankWrBursts::12 134987 # Per bank write bursts
system.physmem.perBankWrBursts::13 137976 # Per bank write bursts
system.physmem.perBankWrBursts::14 134592 # Per bank write bursts
system.physmem.perBankWrBursts::15 136075 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2016-08-12 15:12:59 +02:00
system.physmem.numWrRetry 125 # Number of times write queue was full causing retry
system.physmem.totGap 51558013451500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.readPktSize::6 1883016 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2016-08-12 15:12:59 +02:00
system.physmem.writePktSize::6 2202455 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
2016-02-24 10:16:59 +01:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2016-08-12 15:12:59 +02:00
system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes
2016-02-24 10:16:59 +01:00
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
2016-08-12 15:12:59 +02:00
system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads
system.physmem.totQLat 42075497859 # Total ticks spent queuing
system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers
system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2016-08-12 15:12:59 +02:00
system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2016-08-12 15:12:59 +02:00
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing
system.physmem.readRowHits 1533744 # Number of row buffer hits during reads
system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes
system.physmem.avgGap 12546577.18 # Average gap between requests
system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.831109 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states
system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.833118 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states
system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2016-08-12 15:12:59 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
2016-08-12 15:12:59 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.lookups 290131106 # Number of BP lookups
system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups
system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2016-08-12 15:12:59 +02:00
system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches.
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 1423094 # Table walker walks requested
system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-07-21 18:19:18 +02:00
system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.read_hits 217549636 # DTB read hits
system.cpu.dtb.read_misses 1002675 # DTB read misses
system.cpu.dtb.write_hits 192429615 # DTB write hits
system.cpu.dtb.write_misses 420419 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu.dtb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 218552311 # DTB read accesses
system.cpu.dtb.write_accesses 192850034 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2016-08-12 15:12:59 +02:00
system.cpu.dtb.hits 409979251 # DTB hits
system.cpu.dtb.misses 1423094 # DTB misses
system.cpu.dtb.accesses 411402345 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 177767 # Table walker walks requested
system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2016-08-12 15:12:59 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 462600046 # ITB inst hits
system.cpu.itb.inst_misses 177767 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2016-08-12 15:12:59 +02:00
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2016-08-12 15:12:59 +02:00
system.cpu.itb.flush_tlb_mva_asid 63275 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1203 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2016-08-12 15:12:59 +02:00
system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2016-08-12 15:12:59 +02:00
system.cpu.itb.inst_accesses 462777813 # ITB inst accesses
system.cpu.itb.hits 462600046 # DTB hits
system.cpu.itb.misses 177767 # DTB misses
system.cpu.itb.accesses 462777813 # DTB accesses
system.cpu.numPwrStateTransitions 34262 # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state
2016-07-21 18:19:18 +02:00
system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
2016-06-06 18:16:44 +02:00
system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state
2016-08-12 15:12:59 +02:00
system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 2131080190 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2016-08-12 15:12:59 +02:00
system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed
system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2016-08-12 15:12:59 +02:00
system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2016-08-12 15:12:59 +02:00
system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2016-08-12 15:12:59 +02:00
system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued
system.cpu.iq.rate 0.638398 # Inst issue rate
system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2016-08-12 15:12:59 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2016-08-12 15:12:59 +02:00
system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2016-08-12 15:12:59 +02:00
system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2016-08-12 15:12:59 +02:00
system.cpu.iew.exec_nop 285536 # number of nop insts executed
system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed
system.cpu.iew.exec_branches 255680172 # Number of branches executed
system.cpu.iew.exec_stores 192439435 # Number of stores executed
system.cpu.iew.exec_rate 0.631996 # Inst execution rate
system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back
system.cpu.iew.wb_producers 574929948 # num instructions producing a value
system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value
system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2016-08-12 15:12:59 +02:00
system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1106923026 # Number of instructions committed
system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2016-08-12 15:12:59 +02:00
system.cpu.commit.refs 394099255 # Number of memory references committed
system.cpu.commit.loads 205210646 # Number of loads committed
system.cpu.commit.membars 9122435 # Number of memory barriers committed
system.cpu.commit.branches 247396089 # Number of branches committed
system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions.
system.cpu.commit.function_calls 30973786 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2016-08-12 15:12:59 +02:00
system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction
system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 3398675710 # The number of ROB reads
system.cpu.rob.rob_writes 2741957858 # The number of ROB writes
system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 1106923026 # Number of Instructions Simulated
system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads
system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads
system.cpu.int_regfile_writes 942915680 # number of integer regfile writes
system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads
system.cpu.fp_regfile_writes 762380 # number of floating regfile writes
system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads
system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes
system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads
system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 13662519 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits
system.cpu.dcache.overall_hits::total 351088116 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses
system.cpu.dcache.overall_misses::total 34748544 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks
system.cpu.dcache.writebacks::total 10319802 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses
2016-02-24 10:16:59 +01:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
2016-08-12 15:12:59 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 16891256 # number of replacements
system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses
system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits
system.cpu.icache.overall_hits::total 444441322 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses
system.cpu.icache.overall_misses::total 17679342 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks
system.cpu.icache.writebacks::total 16891256 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 2372905 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1576504 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 10319802 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10319802 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 16888637 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 16888637 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 38922 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 38922 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1712070 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1712070 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16794801 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 16794801 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8925946 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 8925946 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 673558 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 673558 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 1274032 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 302472 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 16794801 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 10638016 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 29009321 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 1274032 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 302472 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 16794801 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 10638016 # number of overall hits
system.cpu.l2cache.overall_hits::total 29009321 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10437 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8742 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 19179 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4078 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 4078 # number of UpgradeReq misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 1333352 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1333352 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 96984 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 96984 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 428025 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 428025 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 590099 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 590099 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 10437 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8742 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 96984 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1761377 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1877540 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 10437 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 8742 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 96984 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1761377 # number of overall misses
system.cpu.l2cache.overall_misses::total 1877540 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 936727000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 780169000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1716896000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73235500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 73235500 # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123861773500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 123861773500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8301693500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 8301693500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38723437000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 38723437000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 483000 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 483000 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 936727000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 780169000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 8301693500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 162585210500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 172603800000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 936727000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 780169000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 8301693500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 162585210500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 172603800000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1284469 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 311214 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1595683 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10319802 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10319802 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 16888637 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 16888637 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43000 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43000 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3045422 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 3045422 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16891785 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 16891785 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9353971 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 9353971 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263657 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1263657 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1284469 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 311214 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 16891785 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 12399393 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 30886861 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1284469 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 311214 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 16891785 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 12399393 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 30886861 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008126 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028090 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.012019 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.094837 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.094837 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.444444 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.444444 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437822 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.437822 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005741 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005741 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045759 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045759 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.466977 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.466977 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008126 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028090 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005741 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.142053 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060788 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008126 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028090 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005741 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.142053 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060788 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726 # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.818507 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.818507 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.writebacks::writebacks 2095825 # number of writebacks
system.cpu.l2cache.writebacks::total 2095825 # number of writebacks
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits
2016-02-24 10:16:59 +01:00
system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10437 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8742 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 19179 # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4078 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4078 # number of UpgradeReq MSHR misses
2016-07-21 18:19:18 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1333352 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1333352 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 96984 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 96984 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 428004 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 428004 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590099 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 590099 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8742 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 96984 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1761356 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1877519 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8742 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 96984 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1761356 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1877519 # number of overall MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 832356501 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 692749000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1525105501 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77850000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77850000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7331831049 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7331831049 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34442081593 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34442081593 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12207320002 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12207320002 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 832356501 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 692749000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7331831049 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 692749000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2016-08-12 15:12:59 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2999840 # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40300 # Transaction distribution
system.iobus.trans_dist::ReadResp 40300 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2016-07-21 18:19:18 +02:00
system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115465 # number of replacements
system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2016-08-12 15:12:59 +02:00
system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2016-08-12 15:12:59 +02:00
system.iocache.tags.tag_accesses 1039668 # Number of tag accesses
system.iocache.tags.data_accesses 1039668 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses
system.iocache.demand_misses::total 115519 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2016-08-12 15:12:59 +02:00
system.iocache.overall_misses::realview.ide 115479 # number of overall misses
system.iocache.overall_misses::total 115519 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2016-08-12 15:12:59 +02:00
system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2016-08-12 15:12:59 +02:00
system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2016-08-12 15:12:59 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2016-08-12 15:12:59 +02:00
system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2016-08-12 15:12:59 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2016-08-12 15:12:59 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency
system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 54986 # Transaction distribution
system.membus.trans_dist::ReadResp 608005 # Transaction distribution
system.membus.trans_dist::WriteReq 33703 # Transaction distribution
system.membus.trans_dist::WriteResp 33703 # Transaction distribution
system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution
system.membus.trans_dist::CleanEvict 284620 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution
2016-07-21 18:19:18 +02:00
system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
2016-08-12 15:12:59 +02:00
system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution
system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution
system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes)
2016-08-12 15:12:59 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2809 # Total snoops (count)
system.membus.snoopTraffic 179264 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2675908 # Request fanout histogram
system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram
system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2016-08-12 15:12:59 +02:00
system.membus.snoop_fanout::total 2675908 # Request fanout histogram
system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2016-04-09 18:13:40 +02:00
system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2016-08-12 15:12:59 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2016-08-12 15:12:59 +02:00
system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2016-08-12 15:12:59 +02:00
system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2016-08-12 15:12:59 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2016-08-12 15:12:59 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2016-08-12 15:12:59 +02:00
system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
