2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
2015-10-10 23:45:41 +02:00
sim_seconds 51.331518 # Number of seconds simulated
sim_ticks 51331518104000 # Number of ticks simulated
final_tick 51331518104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-10-10 23:45:41 +02:00
host_inst_rate 87398 # Simulator instruction rate (inst/s)
host_op_rate 102692 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5304439586 # Simulator tick rate (ticks/s)
host_mem_usage 679424 # Number of bytes of host memory used
host_seconds 9677.09 # Real time elapsed on the host
sim_insts 845761974 # Number of instructions simulated
sim_ops 993759083 # Number of ops (including micro ops) simulated
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-10-10 23:45:41 +02:00
system.physmem.bytes_read::cpu.dtb.walker 205120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 196736 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 5673888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 72271240 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 441728 # Number of bytes read from this memory
system.physmem.bytes_read::total 78788712 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 5673888 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 5673888 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 67330112 # Number of bytes written to this memory
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
2015-10-10 23:45:41 +02:00
system.physmem.bytes_written::total 67350692 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 3205 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 3074 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 104607 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1129251 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6902 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1247039 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1052033 # Number of write requests responded to by this memory
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
2015-10-10 23:45:41 +02:00
system.physmem.num_writes::total 1054606 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 3996 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 3833 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 110534 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1407931 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8605 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1534899 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 110534 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 110534 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1311672 # Write bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.physmem.bw_write::total 1312073 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1311672 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 3996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 3833 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 110534 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1408332 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2846972 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1247039 # Number of read requests accepted
system.physmem.writeReqs 1054606 # Number of write requests accepted
system.physmem.readBursts 1247039 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1054606 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 79759552 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 50944 # Total number of bytes read from write queue
system.physmem.bytesWritten 67349568 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 78788712 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 67350692 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 796 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 141264 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 74145 # Per bank write bursts
system.physmem.perBankRdBursts::1 81438 # Per bank write bursts
system.physmem.perBankRdBursts::2 79571 # Per bank write bursts
system.physmem.perBankRdBursts::3 74681 # Per bank write bursts
system.physmem.perBankRdBursts::4 75850 # Per bank write bursts
system.physmem.perBankRdBursts::5 80076 # Per bank write bursts
system.physmem.perBankRdBursts::6 74234 # Per bank write bursts
system.physmem.perBankRdBursts::7 74770 # Per bank write bursts
system.physmem.perBankRdBursts::8 71012 # Per bank write bursts
system.physmem.perBankRdBursts::9 102127 # Per bank write bursts
system.physmem.perBankRdBursts::10 78424 # Per bank write bursts
system.physmem.perBankRdBursts::11 78933 # Per bank write bursts
system.physmem.perBankRdBursts::12 75355 # Per bank write bursts
system.physmem.perBankRdBursts::13 78384 # Per bank write bursts
system.physmem.perBankRdBursts::14 73014 # Per bank write bursts
system.physmem.perBankRdBursts::15 74229 # Per bank write bursts
system.physmem.perBankWrBursts::0 61794 # Per bank write bursts
system.physmem.perBankWrBursts::1 67391 # Per bank write bursts
system.physmem.perBankWrBursts::2 68136 # Per bank write bursts
system.physmem.perBankWrBursts::3 64875 # Per bank write bursts
system.physmem.perBankWrBursts::4 65862 # Per bank write bursts
system.physmem.perBankWrBursts::5 67755 # Per bank write bursts
system.physmem.perBankWrBursts::6 63835 # Per bank write bursts
system.physmem.perBankWrBursts::7 65687 # Per bank write bursts
system.physmem.perBankWrBursts::8 61691 # Per bank write bursts
system.physmem.perBankWrBursts::9 69909 # Per bank write bursts
system.physmem.perBankWrBursts::10 65651 # Per bank write bursts
system.physmem.perBankWrBursts::11 67939 # Per bank write bursts
system.physmem.perBankWrBursts::12 65356 # Per bank write bursts
system.physmem.perBankWrBursts::13 67578 # Per bank write bursts
system.physmem.perBankWrBursts::14 64108 # Per bank write bursts
system.physmem.perBankWrBursts::15 64770 # Per bank write bursts
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-10-10 23:45:41 +02:00
system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
system.physmem.totGap 51331516800500 # Total gap between requests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-10-10 23:45:41 +02:00
system.physmem.readPktSize::6 1225754 # Read request sizes (log2)
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-10-10 23:45:41 +02:00
system.physmem.writePktSize::6 1052033 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 635607 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 328525 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 149631 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 126665 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 692 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 573 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1305 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 347 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 405 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 130 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 119 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 74 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
2015-10-10 23:45:41 +02:00
system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-10-10 23:45:41 +02:00
system.physmem.wrQLenPdf::15 11652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 13577 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 31214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44410 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 55222 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 63148 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 64318 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 64499 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 66981 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 65872 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 66221 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 71514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 66478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 79594 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 84129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 64906 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 68384 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 61420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 863 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 610 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 501 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 251 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 347 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::52 194 # What write queue length does an incoming req see
2015-10-10 23:45:41 +02:00
system.physmem.wrQLenPdf::53 189 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 476504 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 308.725081 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 177.620621 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 336.470597 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 186131 39.06% 39.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 111955 23.50% 62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 45179 9.48% 72.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 23084 4.84% 76.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 18337 3.85% 80.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11525 2.42% 83.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10900 2.29% 85.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 8098 1.70% 87.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 61295 12.86% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 476504 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 59915 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.799683 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 269.572248 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 59912 99.99% 99.99% # Reads before turning the bus around for writes
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
2015-10-10 23:45:41 +02:00
system.physmem.rdPerTurnAround::total 59915 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 59915 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.563832 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.981523 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 7.290123 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 57069 95.25% 95.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 858 1.43% 96.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 58 0.10% 96.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 312 0.52% 97.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 36 0.06% 97.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 354 0.59% 97.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 211 0.35% 98.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 25 0.04% 98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 62 0.10% 98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 123 0.21% 98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 28 0.05% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 35 0.06% 98.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 500 0.83% 99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 29 0.05% 99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 31 0.05% 99.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 125 0.21% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 7 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 19 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 3 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 6 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 59915 # Writes before turning the bus around for reads
system.physmem.totQLat 31917471814 # Total ticks spent queuing
system.physmem.totMemAccLat 55284528064 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 6231215000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25610.95 # Average queueing delay per DRAM burst
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-10-10 23:45:41 +02:00
system.physmem.avgMemAccLat 44360.95 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-09-25 13:27:03 +02:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
2015-10-10 23:45:41 +02:00
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.76 # Average write queue length when enqueuing
system.physmem.readRowHits 1024444 # Number of row buffer hits during reads
system.physmem.writeRowHits 797630 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
system.physmem.avgGap 22302099.93 # Average gap between requests
system.physmem.pageHitRate 79.27 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 1809644760 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 987405375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4795167000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 3404170800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1235982378375 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29714714061000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34314417854910 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.486362 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49432942986454 # Time in different power states
system.physmem_0.memoryStateTime::REF 1714072100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-10-10 23:45:41 +02:00
system.physmem_0.memoryStateTime::ACT 184500143546 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-10-10 23:45:41 +02:00
system.physmem_1.actEnergy 1792725480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 978173625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4925481600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3414972960 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1238461921980 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29712539014500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34314837317745 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.494534 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49429295042072 # Time in different power states
system.physmem_1.memoryStateTime::REF 1714072100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-10-10 23:45:41 +02:00
system.physmem_1.memoryStateTime::ACT 188150328928 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 436 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 400 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 400 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 25 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
2014-12-02 12:08:25 +01:00
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
2015-10-10 23:45:41 +02:00
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
2015-10-10 23:45:41 +02:00
system.cpu.branchPred.lookups 223690256 # Number of BP lookups
system.cpu.branchPred.condPredicted 149470273 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 12181359 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 157723580 # Number of BTB lookups
system.cpu.branchPred.BTBHits 103180902 # Number of BTB hits
2014-10-30 05:50:15 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-10-10 23:45:41 +02:00
system.cpu.branchPred.BTBHitPct 65.418818 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 30739943 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 342702 # Number of incorrect RAS predictions.
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-10-10 23:45:41 +02:00
system.cpu.dtb.walker.walks 934978 # Table walker walks requested
system.cpu.dtb.walker.walksLong 934978 # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15042 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154863 # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 425141 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 509837 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 2238.847906 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535 506434 99.33% 99.33% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071 1917 0.38% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607 986 0.19% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679 153 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215 25 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287 51 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 509837 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 473320 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535 462482 97.71% 97.71% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071 7672 1.62% 99.33% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607 2249 0.48% 99.81% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143 179 0.04% 99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679 532 0.11% 99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215 62 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751 112 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 23 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 473320 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 784047304876 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.724244 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.519446 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 781857637876 99.72% 99.72% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 1171824000 0.15% 99.87% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 476098500 0.06% 99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 199009000 0.03% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 143211000 0.02% 99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 120940000 0.02% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 26747000 0.00% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 49238000 0.01% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17 2599500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 784047304876 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 154864 91.15% 91.15% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M 15042 8.85% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 169906 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 934978 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-10-10 23:45:41 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 934978 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169906 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-10-10 23:45:41 +02:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169906 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 1104884 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-10-10 23:45:41 +02:00
system.cpu.dtb.read_hits 168982671 # DTB read hits
system.cpu.dtb.read_misses 669792 # DTB read misses
system.cpu.dtb.write_hits 147065605 # DTB write hits
system.cpu.dtb.write_misses 265186 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-10-10 23:45:41 +02:00
system.cpu.dtb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 71824 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 98 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 9312 # Number of TLB faults due to prefetch
2014-10-30 05:50:15 +01:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-10-10 23:45:41 +02:00
system.cpu.dtb.perms_faults 69742 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 169652463 # DTB read accesses
system.cpu.dtb.write_accesses 147330791 # DTB write accesses
2014-10-30 05:50:15 +01:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-10-10 23:45:41 +02:00
system.cpu.dtb.hits 316048276 # DTB hits
system.cpu.dtb.misses 934978 # DTB misses
system.cpu.dtb.accesses 316983254 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-10-30 05:50:15 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walks 161206 # Table walker walks requested
system.cpu.itb.walker.walksLong 161206 # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2 1436 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3 121549 # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 17620 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 143586 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 1244.532893 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 9274.227664 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767 142628 99.33% 99.33% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535 542 0.38% 99.71% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303 55 0.04% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071 79 0.06% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839 218 0.15% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607 29 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911 14 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 143586 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 140605 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 28864.162014 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535 137806 98.01% 98.01% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071 710 0.50% 98.51% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607 1778 1.26% 99.78% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143 108 0.08% 99.86% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679 117 0.08% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215 38 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751 35 0.02% 99.99% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 140605 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 663785102088 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.942542 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.233053 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 38191035356 5.75% 5.75% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 625543374232 94.24% 99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 49878500 0.01% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 812000 0.00% 100.00% # Table walker pending requests distribution
2015-07-03 16:15:03 +02:00
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walksPending::total 663785102088 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 121549 98.83% 98.83% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M 1436 1.17% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 122985 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161206 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 161206 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-10-10 23:45:41 +02:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122985 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 122985 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 284191 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 355626065 # ITB inst hits
system.cpu.itb.inst_misses 161206 # ITB inst misses
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2015-09-25 13:27:03 +02:00
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
2014-10-30 05:50:15 +01:00
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
2015-10-10 23:45:41 +02:00
system.cpu.itb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 52940 # Number of entries that have been flushed from TLB
2014-10-30 05:50:15 +01:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-10-10 23:45:41 +02:00
system.cpu.itb.perms_faults 369021 # Number of TLB faults due to permissions restrictions
2014-10-30 05:50:15 +01:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-10-10 23:45:41 +02:00
system.cpu.itb.inst_accesses 355787271 # ITB inst accesses
system.cpu.itb.hits 355626065 # DTB hits
system.cpu.itb.misses 161206 # DTB misses
system.cpu.itb.accesses 355787271 # DTB accesses
system.cpu.numCycles 1638586091 # number of cpu cycles simulated
2014-10-30 05:50:15 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-10-10 23:45:41 +02:00
system.cpu.fetch.icacheStallCycles 642614268 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 998103903 # Number of instructions fetch has processed
system.cpu.fetch.Branches 223690256 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 133920845 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 910005464 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26014386 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 3801464 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 28966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 9302327 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1031206 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 853 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 355240310 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 6091194 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 48629 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 1579791741 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.740255 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.146164 # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-10-10 23:45:41 +02:00
system.cpu.fetch.rateDist::0 1024362050 64.84% 64.84% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 213190505 13.49% 78.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 70458696 4.46% 82.80% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 271780490 17.20% 100.00% # Number of instructions fetched each cycle (Total)
2014-10-30 05:50:15 +01:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-10-10 23:45:41 +02:00
system.cpu.fetch.rateDist::total 1579791741 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.136514 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.609125 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 522893988 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 566130284 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 431833495 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 49726107 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 9207867 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 33553949 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 3859168 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 1081567524 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 28956293 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 9207867 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 567372760 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 69190624 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 368823691 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 437050453 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 128146346 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 1061861877 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 6771880 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 5087051 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 328687 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 662195 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 77193560 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 20256 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 1009820206 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1635273516 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1255804175 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 1470464 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 944392449 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 65427754 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 26765768 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 23112103 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 102007080 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 173010630 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 150618329 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 9860591 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8967243 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1027007600 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27059230 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1042343751 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 3268943 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 60307743 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 33600701 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 312855 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1579791741 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.659798 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.917984 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-10-10 23:45:41 +02:00
system.cpu.iq.issued_per_cycle::0 934526324 59.16% 59.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 332943694 21.08% 80.23% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234048480 14.82% 95.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 71809082 4.55% 99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 6444954 0.41% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 19207 0.00% 100.00% # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2015-10-10 23:45:41 +02:00
system.cpu.iq.issued_per_cycle::total 1579791741 # Number of insts issued each cycle
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-10-10 23:45:41 +02:00
system.cpu.iq.fu_full::IntAlu 57575402 35.04% 35.04% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 100057 0.06% 35.10% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 764 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 44168987 26.88% 62.00% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 62424891 38.00% 100.00% # attempts to use FU when none available
2014-10-30 05:50:15 +01:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
2015-10-10 23:45:41 +02:00
system.cpu.iq.FU_type_0::IntAlu 717769712 68.86% 68.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 2531817 0.24% 69.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 122691 0.01% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.12% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
2015-10-10 23:45:41 +02:00
system.cpu.iq.FU_type_0::SimdFloatMisc 121277 0.01% 69.13% # Type of FU issued
2015-09-25 13:27:03 +02:00
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
2015-10-10 23:45:41 +02:00
system.cpu.iq.FU_type_0::MemRead 172853843 16.58% 85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 148944351 14.29% 100.00% # Type of FU issued
2014-10-30 05:50:15 +01:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-10-10 23:45:41 +02:00
system.cpu.iq.FU_type_0::total 1042343751 # Type of FU issued
system.cpu.iq.rate 0.636124 # Inst issue rate
system.cpu.iq.fu_busy_cnt 164296841 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157623 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 3829567748 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 1113568735 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1024464263 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 2477278 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 947290 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 909965 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1205083989 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1556592 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 4287735 # Number of loads that had data forwarded from stores
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-10-10 23:45:41 +02:00
system.cpu.iew.lsq.thread0.squashedLoads 13755130 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 14415 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 142727 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6290239 # Number of stores squashed
2014-10-30 05:50:15 +01:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-10-10 23:45:41 +02:00
system.cpu.iew.lsq.thread0.rescheduledLoads 2513645 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1546946 # Number of times an access to memory failed due to the cache being blocked
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-10-10 23:45:41 +02:00
system.cpu.iew.iewSquashCycles 9207867 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 6935208 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 9652893 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1054288001 # Number of instructions dispatched to IQ
2014-10-30 05:50:15 +01:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-10-10 23:45:41 +02:00
system.cpu.iew.iewDispLoadInsts 173010630 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 150618329 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 22687803 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 56498 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 9524585 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 142727 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 3650015 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 5096410 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8746425 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1031209628 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 168969861 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 10209992 # Number of squashed instructions skipped in execute
2014-10-30 05:50:15 +01:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-10-10 23:45:41 +02:00
system.cpu.iew.exec_nop 221171 # number of nop insts executed
system.cpu.iew.exec_refs 316030804 # number of memory reference insts executed
system.cpu.iew.exec_branches 195653401 # Number of branches executed
system.cpu.iew.exec_stores 147060943 # Number of stores executed
system.cpu.iew.exec_rate 0.629329 # Inst execution rate
system.cpu.iew.wb_sent 1026179606 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1025374228 # cumulative count of insts written-back
system.cpu.iew.wb_producers 436457494 # num instructions producing a value
system.cpu.iew.wb_consumers 705894723 # num instructions consuming a value
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2015-10-10 23:45:41 +02:00
system.cpu.iew.wb_rate 0.625768 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.618304 # average fanout of values written-back
2014-10-30 05:50:15 +01:00
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2015-10-10 23:45:41 +02:00
system.cpu.commit.commitSquashedInsts 51232529 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 26746375 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 8382033 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1567845308 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.633837 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.270098 # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-10-10 23:45:41 +02:00
system.cpu.commit.committed_per_cycle::0 1057713558 67.46% 67.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 286814809 18.29% 85.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 120141410 7.66% 93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 36433500 2.32% 95.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 28325160 1.81% 97.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 13966043 0.89% 98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 8603569 0.55% 98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 4169387 0.27% 99.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 11677872 0.74% 100.00% # Number of insts commited each cycle
2014-10-30 05:50:15 +01:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-10-10 23:45:41 +02:00
system.cpu.commit.committed_per_cycle::total 1567845308 # Number of insts commited each cycle
system.cpu.commit.committedInsts 845761974 # Number of instructions committed
system.cpu.commit.committedOps 993759083 # Number of ops (including micro ops) committed
2014-10-30 05:50:15 +01:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2015-10-10 23:45:41 +02:00
system.cpu.commit.refs 303583589 # Number of memory references committed
system.cpu.commit.loads 159255499 # Number of loads committed
system.cpu.commit.membars 6904959 # Number of memory barriers committed
system.cpu.commit.branches 188760643 # Number of branches committed
system.cpu.commit.fp_insts 896514 # Number of committed floating point instructions.
system.cpu.commit.int_insts 913055926 # Number of committed integer instructions.
system.cpu.commit.function_calls 25211674 # Number of function calls committed.
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-10-10 23:45:41 +02:00
system.cpu.commit.op_class_0::IntAlu 687818920 69.21% 69.21% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 2146460 0.22% 69.43% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 98075 0.01% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 159255499 16.03% 85.48% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 144328090 14.52% 100.00% # Class of committed instruction
2014-10-30 05:50:15 +01:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-10-10 23:45:41 +02:00
system.cpu.commit.op_class_0::total 993759083 # Class of committed instruction
system.cpu.commit.bw_lim_events 11677872 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 2593635375 # The number of ROB reads
system.cpu.rob.rob_writes 2101836328 # The number of ROB writes
system.cpu.timesIdled 8111566 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 58794350 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 101024450248 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 845761974 # Number of Instructions Simulated
system.cpu.committedOps 993759083 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.937408 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.937408 # CPI: Total CPI of All Threads
system.cpu.ipc 0.516154 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.516154 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1220647692 # number of integer regfile reads
system.cpu.int_regfile_writes 729132584 # number of integer regfile writes
system.cpu.fp_regfile_reads 1462075 # number of floating regfile reads
system.cpu.fp_regfile_writes 783592 # number of floating regfile writes
system.cpu.cc_regfile_reads 224479860 # number of cc regfile reads
system.cpu.cc_regfile_writes 225129726 # number of cc regfile writes
system.cpu.misc_regfile_reads 2563991678 # number of misc regfile reads
system.cpu.misc_regfile_writes 26780868 # number of misc regfile writes
system.cpu.dcache.tags.replacements 9656863 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.972805 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 282353083 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9657375 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 29.237042 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit.
2015-10-10 23:45:41 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.972805 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-10-10 23:45:41 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-12-02 12:08:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-10-10 23:45:41 +02:00
system.cpu.dcache.tags.tag_accesses 1233161168 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1233161168 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 146769345 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 146769345 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 127879890 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 127879890 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 376551 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 376551 # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data 324490 # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total 324490 # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3281849 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3281849 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3677222 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3677222 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 274649235 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 274649235 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 275025786 # number of overall hits
system.cpu.dcache.overall_hits::total 275025786 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 9521174 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 9521174 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 11203473 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 11203473 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1164152 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1164152 # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data 1231188 # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total 1231188 # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 446606 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 446606 # number of LoadLockedReq misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_misses::cpu.data 20724647 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 20724647 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 21888799 # number of overall misses
system.cpu.dcache.overall_misses::total 21888799 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 166185133500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 166185133500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 435748871062 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 435748871062 # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 89257967135 # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total 89257967135 # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6843268000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 6843268000 # number of LoadLockedReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 276500 # number of StoreCondReq miss cycles
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_miss_latency::cpu.data 601934004562 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 601934004562 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 601934004562 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 601934004562 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 156290519 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 156290519 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 139083363 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 139083363 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1540703 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1540703 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data 1555678 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total 1555678 # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3728455 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3728455 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3677227 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3677227 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 295373882 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 295373882 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 296914585 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 296914585 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060920 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.060920 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080552 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.080552 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.755598 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.755598 # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791416 # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total 0.791416 # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119783 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119783 # miss rate for LoadLockedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_miss_rate::cpu.data 0.070164 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.070164 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.073721 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.073721 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17454.269137 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17454.269137 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38894.088562 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38894.088562 # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72497.431046 # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72497.431046 # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15322.830414 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15322.830414 # average LoadLockedReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55300 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55300 # average StoreCondReq miss latency
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29044.354992 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29044.354992 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27499.635981 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27499.635981 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 49670570 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.cpu.dcache.blocked::no_mshrs 1593951 # number of cycles access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.161918 # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-10-10 23:45:41 +02:00
system.cpu.dcache.writebacks::writebacks 7468918 # number of writebacks
system.cpu.dcache.writebacks::total 7468918 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4425833 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 4425833 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9207187 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 9207187 # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7019 # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total 7019 # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 219274 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 219274 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 13633020 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 13633020 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 13633020 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 13633020 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5095341 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 5095341 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1996286 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1996286 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1157368 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1157368 # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224169 # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total 1224169 # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227332 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 227332 # number of LoadLockedReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_mshr_misses::cpu.data 7091627 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 7091627 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8248995 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8248995 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses
2015-10-10 23:45:41 +02:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83980884000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 83980884000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76343937421 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 76343937421 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22998470000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22998470000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87650245635 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87650245635 # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3191570000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3191570000 # number of LoadLockedReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160324821421 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 160324821421 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183323291421 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 183323291421 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5829051500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5829051500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5836628967 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5836628967 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11665680467 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11665680467 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032602 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032602 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751195 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751195 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786904 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786904 # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060972 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060972 # mshr miss rate for LoadLockedReq accesses
2015-09-15 15:14:09 +02:00
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024009 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.024009 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027782 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.027782 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16481.896697 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16481.896697 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38242.985935 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38242.985935 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19871.354660 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19871.354660 # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71599.791887 # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71599.791887 # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14039.246564 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14039.246564 # average LoadLockedReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency
2015-10-10 23:45:41 +02:00
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22607.621836 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22607.621836 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22223.712273 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22223.712273 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173081.878378 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173081.878378 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173214.297454 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173214.297454 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 173148.105605 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 173148.105605 # average overall mshr uncacheable latency
2014-12-02 12:08:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-10-10 23:45:41 +02:00
system.cpu.icache.tags.replacements 15000702 # number of replacements
system.cpu.icache.tags.tagsinuse 511.916861 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 339450182 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 15001214 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 22.628181 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.warmup_cycle 24732660500 # Cycle when the warmup percentage was hit.
2015-10-10 23:45:41 +02:00
system.cpu.icache.tags.occ_blocks::cpu.inst 511.916861 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-10-10 23:45:41 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
2014-10-30 05:50:15 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-10-10 23:45:41 +02:00
system.cpu.icache.tags.tag_accesses 370220442 # Number of tag accesses
system.cpu.icache.tags.data_accesses 370220442 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 339450182 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 339450182 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 339450182 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 339450182 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 339450182 # number of overall hits
system.cpu.icache.overall_hits::total 339450182 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 15768830 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 15768830 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 15768830 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 15768830 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 15768830 # number of overall misses
system.cpu.icache.overall_misses::total 15768830 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 212844795884 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 212844795884 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 212844795884 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 212844795884 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 212844795884 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 212844795884 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 355219012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 355219012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 355219012 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 355219012 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 355219012 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 355219012 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044392 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.044392 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.044392 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.044392 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.044392 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.044392 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13497.817903 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13497.817903 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13497.817903 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13497.817903 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13497.817903 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13497.817903 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 22619 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.cpu.icache.blocked::no_mshrs 1385 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 16.331408 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-10-10 23:45:41 +02:00
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 767400 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 767400 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 767400 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 767400 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 767400 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 767400 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15001430 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 15001430 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 15001430 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 15001430 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15001430 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15001430 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
2015-10-10 23:45:41 +02:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 190561779393 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 190561779393 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 190561779393 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 190561779393 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 190561779393 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 190561779393 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684494000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684494000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684494000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 2684494000 # number of overall MSHR uncacheable cycles
2015-10-10 23:45:41 +02:00
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042231 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042231 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.042231 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042231 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.042231 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12702.907616 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12702.907616 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12702.907616 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12702.907616 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12702.907616 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12702.907616 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126062.174219 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126062.174219 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126062.174219 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.tags.replacements 1125228 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65275.787267 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 45935367 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1186879 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 38.702654 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.tags.warmup_cycle 22917959500 # Cycle when the warmup percentage was hit.
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 37021.466735 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 280.855675 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 393.338533 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8151.985016 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19428.141309 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.564903 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004286 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006002 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124389 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.296450 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.996029 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 269 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 61382 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 269 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 550 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2696 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52911 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004105 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.936615 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 407946828 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 407946828 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 779449 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 298283 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1077732 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 7468918 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 7468918 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 9287 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 9287 # number of UpgradeReq hits
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 1568942 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1568942 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14917877 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 14917877 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6228350 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 6228350 # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data 729417 # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total 729417 # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 779449 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 298283 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 14917877 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7797292 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 23792901 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 779449 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 298283 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 14917877 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7797292 # number of overall hits
system.cpu.l2cache.overall_hits::total 23792901 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3205 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3074 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 6279 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 33824 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 33824 # number of UpgradeReq misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 387344 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 387344 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83351 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 83351 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 248584 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 248584 # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data 494751 # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total 494751 # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 3205 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 3074 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 83351 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 635928 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 725558 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 3205 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 3074 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 83351 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 635928 # number of overall misses
system.cpu.l2cache.overall_misses::total 725558 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 442457500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 428037500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 870495000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1416950000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 1416950000 # number of UpgradeReq miss cycles
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53765073500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 53765073500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11215140000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 11215140000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34510288000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 34510288000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 76701730500 # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total 76701730500 # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 442457500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 428037500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 11215140000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 88275361500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 100360996500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 442457500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 428037500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 11215140000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 88275361500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 100360996500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 782654 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 301357 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1084011 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 7468918 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 7468918 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43111 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 43111 # number of UpgradeReq accesses(hits+misses)
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1956286 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1956286 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15001228 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 15001228 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6476934 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 6476934 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224168 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total 1224168 # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 782654 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 301357 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 15001228 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 8433220 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 24518459 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 782654 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 301357 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 15001228 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 8433220 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 24518459 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004095 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010201 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.005792 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784579 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784579 # miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.198000 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.198000 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005556 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005556 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038380 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038380 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.404153 # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total 0.404153 # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004095 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010201 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005556 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.075407 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.029592 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004095 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010201 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005556 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.029592 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138052.262090 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139244.469746 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 138635.929288 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 41891.851939 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 41891.851939 # average UpgradeReq miss latency
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138804.456762 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138804.456762 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134553.154731 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134553.154731 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138827.470795 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138827.470795 # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155030.976188 # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155030.976188 # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138052.262090 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139244.469746 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134553.154731 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138813.452938 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138322.500062 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138052.262090 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139244.469746 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134553.154731 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138813.452938 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138322.500062 # average overall miss latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.writebacks::writebacks 945403 # number of writebacks
system.cpu.l2cache.writebacks::total 945403 # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 20 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 20 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3205 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3074 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 6279 # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1050 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 1050 # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33824 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 33824 # number of UpgradeReq MSHR misses
2015-03-02 11:04:20 +01:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 387344 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 387344 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 83351 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 83351 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 248564 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 248564 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 494751 # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total 494751 # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3205 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3074 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 83351 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 635908 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 725538 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3205 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3074 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 83351 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 635908 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 725538 # number of overall MSHR misses
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54973 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable
2015-05-05 09:22:39 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88669 # number of overall MSHR uncacheable misses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 410407500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 397297500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 807705000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2393374500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2393374500 # number of UpgradeReq MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212000 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212000 # number of SCUpgradeReq MSHR miss cycles
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49891633500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49891633500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10381630000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10381630000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 32021997500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 32021997500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 71754220500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 71754220500 # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 410407500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 397297500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10381630000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81913631000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 93102966000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 410407500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 397297500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10381630000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81913631000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 93102966000 # number of overall MSHR miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418306500 # number of ReadReq MSHR uncacheable cycles
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5408063000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7826369500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5444622000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5444622000 # number of WriteReq MSHR uncacheable cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418306500 # number of overall MSHR uncacheable cycles
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10852685000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13270991500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005792 # mshr miss rate for ReadReq accesses
2015-07-03 16:15:03 +02:00
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784579 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784579 # mshr miss rate for UpgradeReq accesses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.198000 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.198000 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005556 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038377 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038377 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.404153 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.404153 # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.029592 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.029592 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128635.929288 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70759.652909 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70759.652909 # average UpgradeReq mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188 # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188 # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393 # average WriteReq mshr uncacheable latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency
2015-10-10 23:45:41 +02:00
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811 # average overall mshr uncacheable latency
2014-10-30 05:50:15 +01:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.snoop_filter.tot_requests 50050277 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 25391485 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3463 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2168 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2168 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 1617253 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23096406 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.trans_dist::Writeback 8520965 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 17374022 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 43114 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.trans_dist::UpgradeResp 43119 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1956286 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1956286 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 15001430 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 6485775 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 1330832 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp 1224168 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45043419 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29192673 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728958 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917333 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 76882383 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960419312 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017977630 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2410856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6261232 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 1987069030 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1835462 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 52366647 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.013365 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.114833 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.snoop_fanout::0 51666749 98.66% 98.66% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 699898 1.34% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.snoop_fanout::total 52366647 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32990991996 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.snoopLayer0.occupancy 1490388 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.respLayer0.occupancy 22530796241 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.respLayer1.occupancy 13336103780 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.respLayer2.occupancy 427917846 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.cpu.toL2Bus.respLayer3.occupancy 1135029759 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.iobus.trans_dist::ReadReq 40289 # Transaction distribution
system.iobus.trans_dist::ReadResp 40289 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.iobus.reqLayer27.occupancy 565927033 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.iocache.tags.replacements 115449 # number of replacements
system.iocache.tags.tagsinuse 10.422254 # Cycle average of tags in use
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2015-10-10 23:45:41 +02:00
system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks.
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2015-10-10 23:45:41 +02:00
system.iocache.tags.warmup_cycle 13103107121000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.543889 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.878365 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221493 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429898 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651391 # Average percentage of cache occupancy
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-10-10 23:45:41 +02:00
system.iocache.tags.tag_accesses 1039569 # Number of tag accesses
system.iocache.tags.data_accesses 1039569 # Number of data accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2015-10-10 23:45:41 +02:00
system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2015-10-10 23:45:41 +02:00
system.iocache.demand_misses::realview.ide 8804 # number of demand (read+write) misses
system.iocache.demand_misses::total 8844 # number of demand (read+write) misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2015-10-10 23:45:41 +02:00
system.iocache.overall_misses::realview.ide 8804 # number of overall misses
system.iocache.overall_misses::total 8844 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5106000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1685439007 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1690545007 # number of ReadReq miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
2015-10-10 23:45:41 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 13827154026 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13827154026 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5457000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1685439007 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1690896007 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5457000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1685439007 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1690896007 # number of overall miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2015-10-10 23:45:41 +02:00
system.iocache.ReadReq_accesses::realview.ide 8804 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8841 # number of ReadReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2015-10-10 23:45:41 +02:00
system.iocache.demand_accesses::realview.ide 8804 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8844 # number of demand (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2015-10-10 23:45:41 +02:00
system.iocache.overall_accesses::realview.ide 8804 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8844 # number of overall (read+write) accesses
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-10-10 23:45:41 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 138000 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 191440.141640 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 191216.492139 # average ReadReq miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
2015-10-10 23:45:41 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129632.809814 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 129632.809814 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 136425 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 191191.316938 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 136425 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 191440.141640 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 191191.316938 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34672 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-10-10 23:45:41 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.923297 # average number of cycles each access was blocked
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-03-02 11:04:20 +01:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2015-10-10 23:45:41 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8804 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8841 # number of ReadReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2015-10-10 23:45:41 +02:00
system.iocache.demand_mshr_misses::realview.ide 8804 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8844 # number of demand (read+write) MSHR misses
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2015-10-10 23:45:41 +02:00
system.iocache.overall_mshr_misses::realview.ide 8804 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8844 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3256000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1245239007 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1248495007 # number of ReadReq MSHR miss cycles
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2015-10-10 23:45:41 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8493954026 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8493954026 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3457000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1245239007 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1248696007 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3457000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1245239007 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1248696007 # number of overall MSHR miss cycles
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-10-10 23:45:41 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88000 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141440.141640 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 141216.492139 # average ReadReq mshr miss latency
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2015-10-10 23:45:41 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79632.809814 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79632.809814 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86425 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 141440.141640 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 141191.316938 # average overall mshr miss latency
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 54973 # Transaction distribution
2015-10-10 23:45:41 +02:00
system.membus.trans_dist::ReadResp 402008 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 33696 # Transaction distribution
system.membus.trans_dist::WriteResp 33696 # Transaction distribution
2015-10-10 23:45:41 +02:00
system.membus.trans_dist::Writeback 1052033 # Transaction distribution
system.membus.trans_dist::CleanEvict 186512 # Transaction distribution
system.membus.trans_dist::UpgradeReq 34605 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2015-10-10 23:45:41 +02:00
system.membus.trans_dist::UpgradeResp 34608 # Transaction distribution
system.membus.trans_dist::ReadExReq 881317 # Transaction distribution
system.membus.trans_dist::ReadExResp 881317 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 347035 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3680509 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3810131 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 342394 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4152525 # Packet count per connected master and slave (bytes)
2015-07-03 16:15:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
2015-10-10 23:45:41 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138873356 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 139043342 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266048 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7266048 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 146309390 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2606 # Total snoops (count)
system.membus.snoop_fanout::samples 2698981 # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-10-10 23:45:41 +02:00
system.membus.snoop_fanout::1 2698981 100.00% 100.00% # Request fanout histogram
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-10-10 23:45:41 +02:00
system.membus.snoop_fanout::total 2698981 # Request fanout histogram
system.membus.reqLayer0.occupancy 104149000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.membus.reqLayer2.occupancy 5470500 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.membus.reqLayer5.occupancy 7144084722 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.membus.respLayer2.occupancy 6645299856 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-10-10 23:45:41 +02:00
system.membus.respLayer3.occupancy 228305891 # Layer occupancy (ticks)
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2015-09-25 13:27:03 +02:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2015-09-25 13:27:03 +02:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-09-15 15:14:09 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2014-10-30 05:50:15 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-10-10 23:45:41 +02:00
system.cpu.kern.inst.quiesce 16105 # number of quiesce instructions executed
2014-10-30 05:50:15 +01:00
---------- End Simulation Statistics ----------
