2012-08-28 20:30:25 +02:00
---------- Begin Simulation Statistics ----------
2015-11-06 09:26:50 +01:00
sim_seconds 2.832918 # Number of seconds simulated
sim_ticks 2832917624000 # Number of ticks simulated
final_tick 2832917624000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
2012-08-28 20:30:25 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
2015-12-04 01:19:05 +01:00
host_inst_rate 70397 # Simulator instruction rate (inst/s)
host_op_rate 85384 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1763575466 # Simulator tick rate (ticks/s)
host_mem_usage 583680 # Number of bytes of host memory used
host_seconds 1606.35 # Real time elapsed on the host
2015-11-06 09:26:50 +01:00
sim_insts 113081477 # Number of instructions simulated
sim_ops 137157144 # Number of ops (including micro ops) simulated
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1316032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9392488 # Number of bytes read from this memory
2014-11-12 15:05:25 +01:00
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_read::total 10711336 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1316032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1316032 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8002368 # Number of bytes written to this memory
2014-10-30 05:18:29 +01:00
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
2015-11-06 09:26:50 +01:00
system.physmem.bytes_written::total 8019892 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22810 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147278 # Number of read requests responded to by this memory
2014-11-12 15:05:25 +01:00
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_reads::total 170132 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 125037 # Number of write requests responded to by this memory
2014-10-30 05:18:29 +01:00
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
2015-11-06 09:26:50 +01:00
system.physmem.num_writes::total 129418 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 464550 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3315482 # Total read bandwidth from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_read::total 3781026 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 464550 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 464550 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2824780 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2830965 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2824780 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 464550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3321668 # Total bandwidth to/from this memory (bytes/s)
2015-09-25 13:27:03 +02:00
system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
2015-11-06 09:26:50 +01:00
system.physmem.bw_total::total 6611992 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 170133 # Number of read requests accepted
system.physmem.writeReqs 129418 # Number of write requests accepted
system.physmem.readBursts 170133 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 129418 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10877696 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10816 # Total number of bytes read from write queue
system.physmem.bytesWritten 8031936 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10711400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8019892 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 169 # Number of DRAM read bursts serviced by the write queue
2015-09-25 13:27:03 +02:00
system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
2015-11-06 09:26:50 +01:00
system.physmem.neitherReadNorWriteReqs 48557 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11298 # Per bank write bursts
system.physmem.perBankRdBursts::1 10506 # Per bank write bursts
system.physmem.perBankRdBursts::2 10925 # Per bank write bursts
system.physmem.perBankRdBursts::3 11199 # Per bank write bursts
system.physmem.perBankRdBursts::4 12883 # Per bank write bursts
system.physmem.perBankRdBursts::5 10202 # Per bank write bursts
system.physmem.perBankRdBursts::6 10845 # Per bank write bursts
system.physmem.perBankRdBursts::7 11219 # Per bank write bursts
system.physmem.perBankRdBursts::8 10577 # Per bank write bursts
system.physmem.perBankRdBursts::9 10527 # Per bank write bursts
system.physmem.perBankRdBursts::10 10037 # Per bank write bursts
system.physmem.perBankRdBursts::11 8948 # Per bank write bursts
system.physmem.perBankRdBursts::12 9970 # Per bank write bursts
system.physmem.perBankRdBursts::13 10631 # Per bank write bursts
system.physmem.perBankRdBursts::14 9988 # Per bank write bursts
system.physmem.perBankRdBursts::15 10209 # Per bank write bursts
system.physmem.perBankWrBursts::0 8496 # Per bank write bursts
system.physmem.perBankWrBursts::1 7860 # Per bank write bursts
system.physmem.perBankWrBursts::2 8364 # Per bank write bursts
system.physmem.perBankWrBursts::3 8532 # Per bank write bursts
system.physmem.perBankWrBursts::4 7663 # Per bank write bursts
system.physmem.perBankWrBursts::5 7568 # Per bank write bursts
system.physmem.perBankWrBursts::6 8029 # Per bank write bursts
system.physmem.perBankWrBursts::7 8274 # Per bank write bursts
system.physmem.perBankWrBursts::8 8070 # Per bank write bursts
system.physmem.perBankWrBursts::9 7909 # Per bank write bursts
system.physmem.perBankWrBursts::10 7508 # Per bank write bursts
system.physmem.perBankWrBursts::11 6646 # Per bank write bursts
system.physmem.perBankWrBursts::12 7551 # Per bank write bursts
system.physmem.perBankWrBursts::13 8006 # Per bank write bursts
system.physmem.perBankWrBursts::14 7465 # Per bank write bursts
system.physmem.perBankWrBursts::15 7558 # Per bank write bursts
2013-11-01 16:56:34 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
2015-11-06 09:26:50 +01:00
system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
system.physmem.totGap 2832917392000 # Total gap between requests
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
2015-05-05 09:22:39 +02:00
system.physmem.readPktSize::2 542 # Read request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.readPktSize::3 14 # Read request sizes (log2)
2015-09-25 13:27:03 +02:00
system.physmem.readPktSize::4 2996 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.readPktSize::5 0 # Read request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.readPktSize::6 166581 # Read request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
2014-10-30 05:18:29 +01:00
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
2013-11-01 16:56:34 +01:00
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
2015-11-06 09:26:50 +01:00
system.physmem.writePktSize::6 125037 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 150592 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 16496 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 2133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 726 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
2014-10-30 05:18:29 +01:00
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
2014-03-23 16:12:19 +01:00
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::15 2033 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2422 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5707 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6701 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6905 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 7704 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 7288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8224 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 8301 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 8345 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 7922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 7435 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 7511 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6870 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6611 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6539 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 277 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 40 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see
2015-09-25 13:27:03 +02:00
system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
2015-11-06 09:26:50 +01:00
system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 62145 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 304.281406 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 179.810971 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.663684 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 23300 37.49% 37.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14989 24.12% 61.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6559 10.55% 72.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3523 5.67% 77.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2511 4.04% 81.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1609 2.59% 84.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1592 2.56% 87.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1065 1.71% 88.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6997 11.26% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 62145 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6266 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.121768 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 563.971651 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6265 99.98% 99.98% # Reads before turning the bus around for writes
2015-09-25 13:27:03 +02:00
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
2015-11-06 09:26:50 +01:00
system.physmem.rdPerTurnAround::total 6266 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6266 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.028567 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.454463 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.210745 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5460 87.14% 87.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 110 1.76% 88.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 30 0.48% 89.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 168 2.68% 92.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 26 0.41% 92.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 137 2.19% 94.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 53 0.85% 95.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 15 0.24% 95.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 11 0.18% 95.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 21 0.34% 96.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 6 0.10% 96.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 7 0.11% 96.46% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 165 2.63% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 5 0.08% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 4 0.06% 99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 23 0.37% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.02% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.66% # Writes before turning the bus around for reads
2015-09-25 13:27:03 +02:00
system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads
2015-11-06 09:26:50 +01:00
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 12 0.19% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6266 # Writes before turning the bus around for reads
system.physmem.totQLat 2116809750 # Total ticks spent queuing
system.physmem.totMemAccLat 5303634750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 849820000 # Total ticks spent in databus transfers
system.physmem.avgQLat 12454.46 # Average queueing delay per DRAM burst
2013-11-01 16:56:34 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
2015-11-06 09:26:50 +01:00
system.physmem.avgMemAccLat 31204.46 # Average memory access latency per DRAM burst
2015-09-25 13:27:03 +02:00
system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
2015-11-06 09:26:50 +01:00
system.physmem.avgWrBWSys 2.83 # Average system write bandwidth in MiByte/s
2013-11-01 16:56:34 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
2015-07-03 16:15:03 +02:00
system.physmem.busUtil 0.05 # Data bus utilization in percentage
2014-10-30 05:18:29 +01:00
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
2015-09-25 13:27:03 +02:00
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
2015-11-06 09:26:50 +01:00
system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing
system.physmem.readRowHits 139542 # Number of row buffer hits during reads
system.physmem.writeRowHits 93775 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.10 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 9457212.27 # Average gap between requests
system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 246546720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 134524500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 694792800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 419813280 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 83588992920 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1626422631000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1896539228820 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.466691 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2705562728250 # Time in different power states
system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_0.memoryStateTime::ACT 32757782250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.actEnergy 223269480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 121823625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 630918600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 393420240 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 81878542335 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1627923026250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1896202928130 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.347979 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2708066096500 # Time in different power states
system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
2015-11-06 09:26:50 +01:00
system.physmem_1.memoryStateTime::ACT 30247332250 # Time in different power states
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
2014-10-30 05:18:29 +01:00
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
2012-08-28 20:30:25 +02:00
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
2014-10-30 05:18:29 +01:00
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.lookups 46858822 # Number of BP lookups
system.cpu.branchPred.condPredicted 24018425 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1233385 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 29501817 # Number of BTB lookups
system.cpu.branchPred.BTBHits 21322160 # Number of BTB hits
2013-01-24 19:29:00 +01:00
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
2015-11-06 09:26:50 +01:00
system.cpu.branchPred.BTBHitPct 72.274057 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 11724285 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33905 # Number of incorrect RAS predictions.
2014-11-12 15:05:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
2014-12-23 15:31:20 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walks 9701 # Table walker walks requested
system.cpu.checker.dtb.walker.walksShort 9701 # Table walker walks initiated with short descriptors
system.cpu.checker.dtb.walker.walkWaitTime::samples 9701 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::0 9701 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walkWaitTime::total 9701 # Table walker wait (enqueue to first request) latency
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.walker.walksPending::samples 375751000 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 375751000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total 375751000 # Table walker pending requests distribution
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walkPageSizes::4K 6238 82.77% 82.77% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::1M 1299 17.23% 100.00% # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkPageSizes::total 7537 # Table walker page sizes translated
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9701 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9701 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7537 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7537 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin::total 17238 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.read_hits 24572028 # DTB read hits
system.cpu.checker.dtb.read_misses 8280 # DTB read misses
system.cpu.checker.dtb.write_hits 19630755 # DTB write hits
system.cpu.checker.dtb.write_misses 1421 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.dtb.flush_entries 4283 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2014-10-30 05:18:29 +01:00
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.read_accesses 24580308 # DTB read accesses
system.cpu.checker.dtb.write_accesses 19632176 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
2015-11-06 09:26:50 +01:00
system.cpu.checker.dtb.hits 44202783 # DTB hits
system.cpu.checker.dtb.misses 9701 # DTB misses
system.cpu.checker.dtb.accesses 44212484 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walks 4825 # Table walker walks requested
system.cpu.checker.itb.walker.walksShort 4825 # Table walker walks initiated with short descriptors
system.cpu.checker.itb.walker.walkWaitTime::samples 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::0 4825 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walkWaitTime::total 4825 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 375090000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total 375090000 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.26% 88.26% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::1M 372 11.74% 100.00% # Table walker page sizes translated
system.cpu.checker.itb.walker.walkPageSizes::total 3170 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4825 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4825 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.checker.itb.inst_hits 115778479 # ITB inst hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.inst_misses 4825 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.flush_entries 2976 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
2015-11-06 09:26:50 +01:00
system.cpu.checker.itb.inst_accesses 115783304 # ITB inst accesses
system.cpu.checker.itb.hits 115778479 # DTB hits
2015-09-25 13:27:03 +02:00
system.cpu.checker.itb.misses 4825 # DTB misses
2015-11-06 09:26:50 +01:00
system.cpu.checker.itb.accesses 115783304 # DTB accesses
system.cpu.checker.numCycles 139006189 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
2014-12-23 15:31:20 +01:00
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walks 71435 # Table walker walks requested
system.cpu.dtb.walker.walksShort 71435 # Table walker walks initiated with short descriptors
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29241 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22400 # Level at which table walker walks with short descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore 19794 # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples 51641 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean 426.153638 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 2576.445985 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-4095 49864 96.56% 96.56% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.13% 97.69% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.02% 98.71% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::12288-16383 340 0.66% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.43% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total 51641 # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples 17522 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 11533.700491 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 9159.086359 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 8173.463802 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-32767 17339 98.96% 98.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency
2015-09-25 13:27:03 +02:00
system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total 17522 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 131382086816 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean 0.616564 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev 0.493575 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1 131327318816 99.96% 99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3 37570000 0.03% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5 7000000 0.01% 99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7 6185500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9 1198500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution
2015-07-03 16:15:03 +02:00
system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walksPending::total 131382086816 # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K 6381 82.69% 82.69% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::1M 1336 17.31% 100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total 7717 # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71435 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71435 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7717 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7717 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 79152 # Table walker requests started/completed, data/inst
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.read_hits 25445516 # DTB read hits
system.cpu.dtb.read_misses 61525 # DTB read misses
system.cpu.dtb.write_hits 19906341 # DTB write hits
system.cpu.dtb.write_misses 9910 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-11-06 09:26:50 +01:00
system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch
2012-08-28 20:30:25 +02:00
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-11-06 09:26:50 +01:00
system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 25507041 # DTB read accesses
system.cpu.dtb.write_accesses 19916251 # DTB write accesses
2012-08-28 20:30:25 +02:00
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
2015-11-06 09:26:50 +01:00
system.cpu.dtb.hits 45351857 # DTB hits
system.cpu.dtb.misses 71435 # DTB misses
system.cpu.dtb.accesses 45423292 # DTB accesses
2014-12-23 15:31:20 +01:00
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
2014-01-24 22:29:34 +01:00
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walks 11899 # Table walker walks requested
system.cpu.itb.walker.walksShort 11899 # Table walker walks initiated with short descriptors
system.cpu.itb.walker.walksShortTerminationLevel::Level1 3941 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate
system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples 11678 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean 616.629560 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev 2880.318774 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-4095 11122 95.24% 95.24% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.25% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.62% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::20480-24575 32 0.27% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total 11678 # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples 3549 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 12870.386024 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 10191.624224 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 8688.844550 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.26% 73.26% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::16384-32767 892 25.13% 98.39% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::32768-49151 55 1.55% 99.94% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total 3549 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 24007842416 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean 0.962955 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev 0.189019 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 889977000 3.71% 3.71% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1 23117314916 96.29% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 24007842416 # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K 3008 90.38% 90.38% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::1M 320 9.62% 100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11899 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 11899 # Table walker requests started/completed, data/inst
2014-12-23 15:31:20 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
2015-11-06 09:26:50 +01:00
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 15227 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 66219818 # ITB inst hits
system.cpu.itb.inst_misses 11899 # ITB inst misses
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
2014-10-30 05:18:29 +01:00
system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
2015-11-06 09:26:50 +01:00
system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
2012-08-28 20:30:25 +02:00
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
2015-11-06 09:26:50 +01:00
system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions
2012-08-28 20:30:25 +02:00
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
2015-11-06 09:26:50 +01:00
system.cpu.itb.inst_accesses 66231717 # ITB inst accesses
system.cpu.itb.hits 66219818 # DTB hits
system.cpu.itb.misses 11899 # DTB misses
system.cpu.itb.accesses 66231717 # DTB accesses
system.cpu.numCycles 278809396 # number of cpu cycles simulated
2012-08-28 20:30:25 +02:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
2015-11-06 09:26:50 +01:00
system.cpu.fetch.icacheStallCycles 104752228 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 184594753 # Number of instructions fetch has processed
system.cpu.fetch.Branches 46858822 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 33046445 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 161837102 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 6149420 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 189977 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 9772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 357687 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 560902 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 181 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 66220013 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 1133469 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5179 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 270782559 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.831431 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.217897 # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::0 171565839 63.36% 63.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 29222654 10.79% 74.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 14067780 5.20% 79.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55926286 20.65% 100.00% # Number of instructions fetched each cycle (Total)
2012-08-28 20:30:25 +02:00
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
2014-09-03 13:42:59 +02:00
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
2015-11-06 09:26:50 +01:00
system.cpu.fetch.rateDist::total 270782559 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.168068 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.662082 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 77849645 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 121907615 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 64584092 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 3844418 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 2596789 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3423202 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 486322 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 157325754 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 3698413 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 2596789 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83693975 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 11775859 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 76672657 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62585691 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 33457588 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146699029 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 957260 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 452831 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 63761 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 16550 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 30707740 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150373398 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678238170 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164317610 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 141712294 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 8661101 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 2840653 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2644485 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 13863116 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 26394295 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 21292545 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1689185 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2215742 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143439670 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2121732 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 143229007 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 270292 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8404254 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14686510 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125844 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 270782559 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.528945 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.865530 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::0 182544969 67.41% 67.41% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 45137079 16.67% 84.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 32020155 11.83% 95.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10269839 3.79% 99.70% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 810484 0.30% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2014-09-03 13:42:59 +02:00
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2015-11-06 09:26:50 +01:00
system.cpu.iq.issued_per_cycle::total 270782559 # Number of insts issued each cycle
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2015-11-06 09:26:50 +01:00
system.cpu.iq.fu_full::IntAlu 7336568 32.74% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 5631848 25.13% 57.87% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 9441706 42.13% 100.00% # attempts to use FU when none available
2012-08-28 20:30:25 +02:00
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::IntAlu 95930740 66.98% 66.98% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 113813 0.08% 67.06% # Type of FU issued
2014-10-30 05:18:29 +01:00
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 26175663 18.28% 85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 20997878 14.66% 100.00% # Type of FU issued
2012-08-28 20:30:25 +02:00
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2015-11-06 09:26:50 +01:00
system.cpu.iq.FU_type_0::total 143229007 # Type of FU issued
system.cpu.iq.rate 0.513717 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22410154 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.156464 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 579885434 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 153971015 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140120635 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 165613479 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 322744 # Number of loads that had data forwarded from stores
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.squashedLoads 1495175 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 502 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18526 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 703988 # Number of stores squashed
2012-08-28 20:30:25 +02:00
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2015-11-06 09:26:50 +01:00
system.cpu.iew.lsq.thread0.rescheduledLoads 87827 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6407 # Number of times an access to memory failed due to the cache being blocked
2012-08-28 20:30:25 +02:00
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewSquashCycles 2596789 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1243570 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 532137 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 145762333 # Number of instructions dispatched to IQ
2014-09-03 13:42:59 +02:00
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2015-11-06 09:26:50 +01:00
system.cpu.iew.iewDispLoadInsts 26394295 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 21292545 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1096246 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17995 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 497968 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 18526 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 317449 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471196 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 788645 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 142286885 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 25773498 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 870795 # Number of squashed instructions skipped in execute
2012-08-28 20:30:25 +02:00
system.cpu.iew.exec_swp 0 # number of swp insts executed
2015-11-06 09:26:50 +01:00
system.cpu.iew.exec_nop 200931 # number of nop insts executed
system.cpu.iew.exec_refs 46642508 # number of memory reference insts executed
system.cpu.iew.exec_branches 26501737 # Number of branches executed
system.cpu.iew.exec_stores 20869010 # Number of stores executed
system.cpu.iew.exec_rate 0.510337 # Inst execution rate
system.cpu.iew.wb_sent 141900432 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140132002 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63223126 # num instructions producing a value
system.cpu.iew.wb_consumers 95712973 # num instructions consuming a value
system.cpu.iew.wb_rate 0.502609 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660549 # average fanout of values written-back
system.cpu.commit.commitSquashedInsts 7603118 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995888 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 755464 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 267848804 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.512648 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.117834 # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::0 194453826 72.60% 72.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 43232556 16.14% 88.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15468323 5.78% 94.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 4394328 1.64% 96.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6341907 2.37% 98.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1685586 0.63% 99.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 800919 0.30% 99.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 412081 0.15% 99.60% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 1059278 0.40% 100.00% # Number of insts commited each cycle
2012-08-28 20:30:25 +02:00
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2015-11-06 09:26:50 +01:00
system.cpu.commit.committed_per_cycle::total 267848804 # Number of insts commited each cycle
system.cpu.commit.committedInsts 113236382 # Number of instructions committed
system.cpu.commit.committedOps 137312049 # Number of ops (including micro ops) committed
2012-08-28 20:30:25 +02:00
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
2015-11-06 09:26:50 +01:00
system.cpu.commit.refs 45487677 # Number of memory references committed
system.cpu.commit.loads 24899120 # Number of loads committed
system.cpu.commit.membars 814929 # Number of memory barriers committed
system.cpu.commit.branches 26016406 # Number of branches committed
2015-09-25 13:27:03 +02:00
system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
2015-11-06 09:26:50 +01:00
system.cpu.commit.int_insts 120142081 # Number of committed integer instructions.
system.cpu.commit.function_calls 4881652 # Number of function calls committed.
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::IntAlu 91703052 66.78% 66.78% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 112745 0.08% 66.87% # Class of committed instruction
2014-10-30 05:18:29 +01:00
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # Class of committed instruction
2015-09-25 13:27:03 +02:00
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::MemRead 24899120 18.13% 85.01% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 20588557 14.99% 100.00% # Class of committed instruction
2014-05-10 00:58:50 +02:00
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2015-11-06 09:26:50 +01:00
system.cpu.commit.op_class_0::total 137312049 # Class of committed instruction
system.cpu.commit.bw_lim_events 1059278 # number cycles where commit BW limit reached
system.cpu.rob.rob_reads 389547304 # The number of ROB reads
system.cpu.rob.rob_writes 292761659 # The number of ROB writes
system.cpu.timesIdled 892855 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8026837 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 5387025853 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 113081477 # Number of Instructions Simulated
system.cpu.committedOps 137157144 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 2.465562 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.465562 # CPI: Total CPI of All Threads
system.cpu.ipc 0.405587 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.405587 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 155726558 # number of integer regfile reads
system.cpu.int_regfile_writes 88564581 # number of integer regfile writes
system.cpu.fp_regfile_reads 9527 # number of floating regfile reads
2014-10-30 05:18:29 +01:00
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
2015-11-06 09:26:50 +01:00
system.cpu.cc_regfile_reads 502647576 # number of cc regfile reads
system.cpu.cc_regfile_writes 53157224 # number of cc regfile writes
system.cpu.misc_regfile_reads 348272878 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521665 # number of misc regfile writes
system.cpu.dcache.tags.replacements 837515 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40092431 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 838027 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 47.841455 # Average number of references to valid blocks.
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor
2015-09-25 13:27:03 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.dcache.tags.tag_accesses 179262738 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 179262738 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 23296604 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 23296604 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 15545032 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 15545032 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 345927 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 345927 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 441660 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 441660 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 460331 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 460331 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 38841636 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 38841636 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 39187563 # number of overall hits
system.cpu.dcache.overall_hits::total 39187563 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 708765 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 708765 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 3602792 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 3602792 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 177926 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 177926 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 27128 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 27128 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 4311557 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 4311557 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 4489483 # number of overall misses
system.cpu.dcache.overall_misses::total 4489483 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11704891500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11704891500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 232547539185 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 232547539185 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 374670000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 374670000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 244252430685 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 244252430685 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 244252430685 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 244252430685 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24005369 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24005369 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19147824 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19147824 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 523853 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 523853 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468788 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 468788 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460338 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 460338 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 43153193 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 43153193 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 43677046 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 43677046 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029525 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.029525 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188157 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.188157 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339649 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.339649 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057868 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057868 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.099913 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.099913 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.102788 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.102788 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16514.488582 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16514.488582 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64546.479282 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64546.479282 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13811.191389 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13811.191389 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 56650.632401 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 56650.632401 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54405.469557 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54405.469557 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 871729 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.blocked::no_mshrs 6864 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.000146 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.dcache.writebacks::writebacks 695593 # number of writebacks
system.cpu.dcache.writebacks::total 695593 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295624 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 295624 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3303164 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3303164 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18735 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 18735 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3598788 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3598788 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3598788 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3598788 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413141 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 413141 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299628 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 299628 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119644 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 119644 # number of SoftPFReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8393 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8393 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 712769 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 712769 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 832413 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 832413 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386936500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386936500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19975151483 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 19975151483 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1701142500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1701142500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126808000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126808000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26362087983 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 26362087983 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28063230483 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28063230483 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6277199000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6277199000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075698951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075698951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352897951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352897951 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017210 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017210 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015648 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015648 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228392 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228392 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017904 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017904 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019058 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019058 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15459.459361 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15459.459361 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66666.504743 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66666.504743 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14218.368660 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14218.368660 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15108.781127 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15108.781127 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36985.458098 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36985.458098 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33713.109338 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 33713.109338 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201651.161297 # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201651.161297 # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184002.137067 # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184002.137067 # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193359.300184 # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193359.300184 # average overall mshr uncacheable latency
2014-11-12 15:05:25 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.replacements 1886833 # number of replacements
system.cpu.icache.tags.tagsinuse 511.154154 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 64237730 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1887345 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34.036029 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.154154 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
2015-09-25 13:27:03 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
2014-11-12 15:05:25 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.cpu.icache.tags.tag_accesses 68104377 # Number of tag accesses
system.cpu.icache.tags.data_accesses 68104377 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 64237730 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 64237730 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 64237730 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 64237730 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 64237730 # number of overall hits
system.cpu.icache.overall_hits::total 64237730 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1979279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1979279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1979279 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1979279 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1979279 # number of overall misses
system.cpu.icache.overall_misses::total 1979279 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 28148050491 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 28148050491 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 28148050491 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 28148050491 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 28148050491 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 28148050491 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 66217009 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 66217009 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 66217009 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 66217009 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 66217009 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 66217009 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029891 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.029891 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.029891 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.029891 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.029891 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.029891 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14221.365705 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 14221.365705 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 14221.365705 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14221.365705 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 14221.365705 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 4340 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.blocked::no_mshrs 160 # number of cycles access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.cpu.icache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked
2014-11-12 15:05:25 +01:00
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
2012-08-28 20:30:25 +02:00
system.cpu.icache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.icache.writebacks::writebacks 1886833 # number of writebacks
system.cpu.icache.writebacks::total 1886833 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91909 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 91909 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 91909 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 91909 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 91909 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 91909 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887370 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 1887370 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 1887370 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 1887370 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1887370 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1887370 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25183213993 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 25183213993 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25183213993 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 25183213993 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25183213993 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 25183213993 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377667500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377667500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 377667500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028503 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.028503 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028503 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.028503 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13343.019118 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13343.019118 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13343.019118 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 13343.019118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13343.019118 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13343.019118 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125721.537949 # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125721.537949 # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125721.537949 # average overall mshr uncacheable latency
2012-08-28 20:30:25 +02:00
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.replacements 96631 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65023.762629 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 4997690 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 161869 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 30.874905 # Average number of references to valid blocks.
2014-10-30 05:18:29 +01:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.tags.occ_blocks::writebacks 49540.037548 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.058123 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.836532 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 10328.574212 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 5143.256214 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.755921 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000153 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000028 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157602 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.078480 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.992184 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65226 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6640 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55528 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995270 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 44234795 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 44234795 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54117 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11847 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 65964 # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks 695593 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 695593 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1846839 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1846839 # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 33 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 33 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 4 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 161471 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 161471 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867481 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1867481 # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527598 # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total 527598 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 54117 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 11847 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 1867481 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 689069 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2622514 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 54117 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 11847 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 1867481 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 689069 # number of overall hits
system.cpu.l2cache.overall_hits::total 2622514 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 29 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2723 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2723 # number of UpgradeReq misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_misses::cpu.data 135531 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 135531 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19843 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 19843 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13450 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 13450 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 19843 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 148981 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 168853 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 8 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 19843 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 148981 # number of overall misses
system.cpu.l2cache.overall_misses::total 168853 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2920500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1140500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 4061000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2260500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 2260500 # number of UpgradeReq miss cycles
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17607551500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 17607551500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2626802500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total 2626802500 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1813838000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 1813838000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2920500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1140500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 2626802500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 19421389500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22052253000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2920500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1140500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 2626802500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 19421389500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22052253000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54138 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11855 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 65993 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks 695593 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 695593 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1846839 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1846839 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 297002 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 297002 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887324 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 1887324 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541048 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total 541048 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 11855 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 1887324 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 838050 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2791367 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 11855 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 1887324 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 838050 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2791367 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000388 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000675 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.000439 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988026 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988026 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.456330 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.456330 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010514 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010514 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024859 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024859 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000388 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000675 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010514 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.177771 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.060491 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000388 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000675 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010514 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.177771 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.060491 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139071.428571 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 142562.500000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 140034.482759 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 830.150569 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 830.150569 # average UpgradeReq miss latency
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129915.307199 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129915.307199 # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132379.302525 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132379.302525 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134857.843866 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134857.843866 # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139071.428571 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 142562.500000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132379.302525 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130361.519254 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 130600.303222 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139071.428571 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 142562.500000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132379.302525 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130361.519254 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 130600.303222 # average overall miss latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.writebacks::writebacks 88877 # number of writebacks
system.cpu.l2cache.writebacks::total 88877 # number of writebacks
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 29 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2723 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2723 # number of UpgradeReq MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135531 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 135531 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19817 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19817 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13338 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13338 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 19817 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 19817 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 148869 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 168715 # number of overall MSHR misses
2015-09-25 13:27:03 +02:00
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses
2015-11-06 09:26:50 +01:00
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2710500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1060500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3771000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192695000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192695000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16252241500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16252241500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425990000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425990000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1667259500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1667259500 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2710500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1060500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425990000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17919501000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 20349262000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2710500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1060500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425990000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17919501000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 20349262000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888077000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6228194000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756881000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756881000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644958000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10985075000 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000439 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988026 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988026 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456330 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456330 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024652 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024652 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060442 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000388 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177637 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.060442 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 130034.482759 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70765.699596 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70765.699596 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119915.307199 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119915.307199 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122419.639703 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122419.639703 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125000.712251 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125000.712251 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129071.428571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 132562.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122419.639703 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120370.936864 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120613.235338 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189150.856115 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182468.403012 # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172444.480696 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172444.480696 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181301.870082 # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177988.188211 # average overall mshr uncacheable latency
2012-10-15 14:09:54 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_filter.tot_requests 5484076 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758688 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47112 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::ReadReq 127589 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2556141 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.trans_dist::WritebackDirty 820637 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1846839 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 142823 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2763 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297002 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297002 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 541297 # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627539 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629603 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31270 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128179 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 8416591 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239034368 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98344937 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47420 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 337643277 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 197136 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025905 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.158851 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::0 2973765 97.41% 97.41% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 79083 2.59% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2015-09-25 13:27:03 +02:00
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5400072997 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer0.occupancy 2834880345 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer1.occupancy 1303595064 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer2.occupancy 19421986 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.cpu.toL2Bus.respLayer3.occupancy 74092896 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 59014 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer2.occupancy 29000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer3.occupancy 14500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer6.occupancy 91000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer7.occupancy 647500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer23.occupancy 6192000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer24.occupancy 167000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer25.occupancy 33054500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer26.occupancy 126000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer27.occupancy 186395016 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.iocache.tags.replacements 36409 # number of replacements
system.iocache.tags.tagsinuse 1.005392 # Cycle average of tags in use
system.iocache.tags.total_refs 30 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 256608771000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 1.005392 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.062837 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.062837 # Average percentage of cache occupancy
2014-10-30 05:18:29 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2015-11-06 09:26:50 +01:00
system.iocache.tags.tag_accesses 328227 # Number of tag accesses
system.iocache.tags.data_accesses 328227 # Number of data accesses
system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits
system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 31311876 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 31311876 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4715518140 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4715518140 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 31311876 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 31311876 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 31311876 # number of overall miss cycles
system.iocache.overall_miss_latency::total 31311876 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2015-11-06 09:26:50 +01:00
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 125750.506024 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125750.506024 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130280.926647 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 130280.926647 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125750.506024 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125750.506024 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125750.506024 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 725 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.blocked::no_mshrs 77 # number of cycles access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2015-11-06 09:26:50 +01:00
system.iocache.avg_blocked_cycles::no_mshrs 9.415584 # average number of cycles each access was blocked
2012-08-28 20:30:25 +02:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
2012-08-28 20:30:25 +02:00
system.iocache.cache_copies 0 # number of cache copies performed
2015-11-06 09:26:50 +01:00
system.iocache.writebacks::writebacks 36160 # number of writebacks
system.iocache.writebacks::total 36160 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18861876 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18861876 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2905768140 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2905768140 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18861876 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18861876 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18861876 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18861876 # number of overall MSHR miss cycles
2014-10-30 05:18:29 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2015-11-06 09:26:50 +01:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses
2014-10-30 05:18:29 +01:00
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2015-11-06 09:26:50 +01:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75750.506024 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 75750.506024 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80280.926647 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80280.926647 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75750.506024 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75750.506024 # average overall mshr miss latency
2012-08-28 20:30:25 +02:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::ReadReq 34133 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::ReadResp 67565 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::WriteReq 27585 # Transaction distribution
system.membus.trans_dist::WriteResp 27585 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::WritebackDirty 125037 # Transaction distribution
system.membus.trans_dist::CleanEvict 7766 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution
2015-09-25 13:27:03 +02:00
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
2015-11-06 09:26:50 +01:00
system.membus.trans_dist::UpgradeResp 4599 # Transaction distribution
system.membus.trans_dist::ReadExReq 133659 # Transaction distribution
system.membus.trans_dist::ReadExResp 133659 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 33433 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455099 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562669 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 671495 # Packet count per connected master and slave (bytes)
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
2014-11-12 15:05:25 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
2015-09-25 13:27:03 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
2015-11-06 09:26:50 +01:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16416028 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16579433 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 18894633 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 513 # Total snoops (count)
system.membus.snoop_fanout::samples 402650 # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::1 402650 100.00% 100.00% # Request fanout histogram
2014-11-12 15:05:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2015-11-06 09:26:50 +01:00
system.membus.snoop_fanout::total 402650 # Request fanout histogram
system.membus.reqLayer0.occupancy 83677500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer2.occupancy 1748500 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.reqLayer5.occupancy 874312374 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer2.occupancy 988164899 # Layer occupancy (ticks)
2015-03-02 11:04:20 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2015-11-06 09:26:50 +01:00
system.membus.respLayer3.occupancy 64093300 # Layer occupancy (ticks)
2014-11-12 15:05:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2014-11-12 15:05:25 +01:00
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2012-08-28 20:30:25 +02:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
2015-09-25 13:27:03 +02:00
system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed
2012-08-28 20:30:25 +02:00
---------- End Simulation Statistics ----------
