2007-03-04 04:45:26 +01:00
|
|
|
[root]
|
|
|
|
type=Root
|
|
|
|
children=system
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-02-12 23:07:43 +01:00
|
|
|
full_system=true
|
2014-05-12 23:22:17 +02:00
|
|
|
sim_quantum=0
|
2011-02-08 04:23:13 +01:00
|
|
|
time_sync_enable=false
|
|
|
|
time_sync_period=200000000
|
|
|
|
time_sync_spin_threshold=200000
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system]
|
|
|
|
type=SparcSystem
|
2014-09-01 23:55:52 +02:00
|
|
|
children=bridge clk_domain cpu cpu_clk_domain disk0 dvfs_handler hypervisor_desc intrctrl iobus membus nvram partition_desc physmem0 physmem1 rom t1000 voltage_domain
|
2007-03-04 04:45:26 +01:00
|
|
|
boot_osflags=a
|
2013-09-15 20:45:59 +02:00
|
|
|
cache_line_size=64
|
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2016-01-18 03:13:29 +01:00
|
|
|
exit_on_work_items=false
|
2007-03-04 04:45:26 +01:00
|
|
|
hypervisor_addr=1099243257856
|
2016-01-18 03:13:29 +01:00
|
|
|
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
2007-03-04 04:45:26 +01:00
|
|
|
hypervisor_desc=system.hypervisor_desc
|
|
|
|
hypervisor_desc_addr=133446500352
|
2016-01-18 03:13:29 +01:00
|
|
|
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
2007-03-04 04:45:26 +01:00
|
|
|
init_param=0
|
|
|
|
kernel=
|
2014-09-01 23:55:52 +02:00
|
|
|
kernel_addr_check=true
|
2011-02-08 04:23:13 +01:00
|
|
|
load_addr_mask=1099511627775
|
2014-05-12 23:22:17 +02:00
|
|
|
load_offset=0
|
2007-03-04 04:45:26 +01:00
|
|
|
mem_mode=atomic
|
2013-03-05 05:33:47 +01:00
|
|
|
mem_ranges=1048576:68157439 2147483648:2415919103
|
2015-07-04 17:43:47 +02:00
|
|
|
memories=system.hypervisor_desc system.nvram system.partition_desc system.physmem0 system.physmem1 system.rom
|
|
|
|
mmap_using_noreserve=false
|
2016-01-18 03:13:29 +01:00
|
|
|
multi_thread=false
|
2012-01-25 18:19:50 +01:00
|
|
|
num_work_ids=16
|
2007-03-04 04:45:26 +01:00
|
|
|
nvram=system.nvram
|
|
|
|
nvram_addr=133429198848
|
2016-01-18 03:13:29 +01:00
|
|
|
nvram_bin=/dist/m5/system/binaries/nvram1
|
2007-03-04 04:45:26 +01:00
|
|
|
openboot_addr=1099243716608
|
2016-01-18 03:13:29 +01:00
|
|
|
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
2007-03-04 04:45:26 +01:00
|
|
|
partition_desc=system.partition_desc
|
|
|
|
partition_desc_addr=133445976064
|
2016-01-18 03:13:29 +01:00
|
|
|
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
|
|
|
readfile=/z/stever/hg/gem5/tests/halt.sh
|
2007-03-04 04:45:26 +01:00
|
|
|
reset_addr=1099243192320
|
2016-01-18 03:13:29 +01:00
|
|
|
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
2007-03-04 04:45:26 +01:00
|
|
|
rom=system.rom
|
|
|
|
symbolfile=
|
2011-02-08 04:23:13 +01:00
|
|
|
work_begin_ckpt_count=0
|
|
|
|
work_begin_cpu_id_exit=-1
|
|
|
|
work_begin_exit_count=0
|
|
|
|
work_cpus_ckpt_count=0
|
|
|
|
work_end_ckpt_count=0
|
|
|
|
work_end_exit_count=0
|
|
|
|
work_item_id=-1
|
2012-05-09 20:52:14 +02:00
|
|
|
system_port=system.membus.slave[0]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.bridge]
|
|
|
|
type=Bridge
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2007-05-16 01:25:35 +02:00
|
|
|
delay=100
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-01-25 18:19:50 +01:00
|
|
|
ranges=133412421632:133412421639 134217728000:554050781183 644245094400:652835028991 725849473024:1095485095935 1099255955456:1099255955463
|
|
|
|
req_size=16
|
|
|
|
resp_size=16
|
2012-05-09 20:52:14 +02:00
|
|
|
master=system.iobus.slave[0]
|
|
|
|
slave=system.membus.master[2]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2013-09-15 20:45:59 +02:00
|
|
|
[system.clk_domain]
|
|
|
|
type=SrcClockDomain
|
|
|
|
clock=2
|
2014-09-01 23:55:52 +02:00
|
|
|
domain_id=-1
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2014-09-01 23:55:52 +02:00
|
|
|
init_perf_level=0
|
2013-09-15 20:45:59 +02:00
|
|
|
voltage_domain=system.voltage_domain
|
|
|
|
|
2007-03-04 04:45:26 +01:00
|
|
|
[system.cpu]
|
|
|
|
type=AtomicSimpleCPU
|
2013-03-05 05:33:47 +01:00
|
|
|
children=dtb interrupts isa itb tracer
|
2014-05-12 23:22:17 +02:00
|
|
|
branchPred=Null
|
2009-02-16 18:09:45 +01:00
|
|
|
checker=Null
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.cpu_clk_domain
|
2007-03-04 04:45:26 +01:00
|
|
|
cpu_id=0
|
|
|
|
do_checkpoint_insts=true
|
|
|
|
do_quiesce=true
|
|
|
|
do_statistics_insts=true
|
|
|
|
dtb=system.cpu.dtb
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
fastmem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
function_trace=false
|
|
|
|
function_trace_start=0
|
2008-11-06 17:11:42 +01:00
|
|
|
interrupts=system.cpu.interrupts
|
2013-03-05 05:33:47 +01:00
|
|
|
isa=system.cpu.isa
|
2007-03-04 04:45:26 +01:00
|
|
|
itb=system.cpu.itb
|
|
|
|
max_insts_all_threads=0
|
|
|
|
max_insts_any_thread=0
|
|
|
|
max_loads_all_threads=0
|
|
|
|
max_loads_any_thread=0
|
2008-09-28 23:16:26 +02:00
|
|
|
numThreads=1
|
2007-03-04 04:45:26 +01:00
|
|
|
profile=0
|
|
|
|
progress_interval=0
|
2013-09-15 20:45:59 +02:00
|
|
|
simpoint_start_insts=
|
2008-07-22 23:00:18 +02:00
|
|
|
simulate_data_stalls=false
|
|
|
|
simulate_inst_stalls=false
|
2014-05-12 23:22:17 +02:00
|
|
|
socket_id=0
|
2013-03-05 05:33:47 +01:00
|
|
|
switched_out=false
|
2007-03-04 04:45:26 +01:00
|
|
|
system=system
|
2007-08-27 05:27:53 +02:00
|
|
|
tracer=system.cpu.tracer
|
2007-03-04 04:45:26 +01:00
|
|
|
width=1
|
2012-02-12 23:07:43 +01:00
|
|
|
workload=
|
2012-05-09 20:52:14 +02:00
|
|
|
dcache_port=system.membus.slave[2]
|
|
|
|
icache_port=system.membus.slave[1]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.cpu.dtb]
|
2009-04-09 07:21:30 +02:00
|
|
|
type=SparcTLB
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
size=64
|
|
|
|
|
2008-11-06 17:11:42 +01:00
|
|
|
[system.cpu.interrupts]
|
|
|
|
type=SparcInterrupts
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2008-11-06 17:11:42 +01:00
|
|
|
|
2013-03-05 05:33:47 +01:00
|
|
|
[system.cpu.isa]
|
|
|
|
type=SparcISA
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2013-03-05 05:33:47 +01:00
|
|
|
|
2007-03-04 04:45:26 +01:00
|
|
|
[system.cpu.itb]
|
2009-04-09 07:21:30 +02:00
|
|
|
type=SparcTLB
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
size=64
|
|
|
|
|
2007-08-27 05:27:53 +02:00
|
|
|
[system.cpu.tracer]
|
|
|
|
type=ExeTracer
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-08-27 05:27:53 +02:00
|
|
|
|
2013-09-15 20:45:59 +02:00
|
|
|
[system.cpu_clk_domain]
|
|
|
|
type=SrcClockDomain
|
|
|
|
clock=2
|
2014-09-01 23:55:52 +02:00
|
|
|
domain_id=-1
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2014-09-01 23:55:52 +02:00
|
|
|
init_perf_level=0
|
2013-09-15 20:45:59 +02:00
|
|
|
voltage_domain=system.voltage_domain
|
|
|
|
|
2007-03-04 04:45:26 +01:00
|
|
|
[system.disk0]
|
|
|
|
type=MmDisk
|
|
|
|
children=image
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
image=system.disk0.image
|
|
|
|
pio_addr=134217728000
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
system=system
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[14]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.disk0.image]
|
|
|
|
type=CowDiskImage
|
|
|
|
children=child
|
|
|
|
child=system.disk0.image.child
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2009-02-16 18:09:45 +01:00
|
|
|
image_file=
|
2007-03-04 04:45:26 +01:00
|
|
|
read_only=false
|
|
|
|
table_size=65536
|
|
|
|
|
|
|
|
[system.disk0.image.child]
|
|
|
|
type=RawDiskImage
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2016-01-18 03:13:29 +01:00
|
|
|
image_file=/dist/m5/system/disks/disk.s10hw2
|
2007-03-04 04:45:26 +01:00
|
|
|
read_only=true
|
|
|
|
|
2014-09-01 23:55:52 +02:00
|
|
|
[system.dvfs_handler]
|
|
|
|
type=DVFSHandler
|
|
|
|
domains=
|
|
|
|
enable=false
|
|
|
|
eventq_index=0
|
|
|
|
sys_clk_domain=system.clk_domain
|
|
|
|
transition_latency=200000
|
|
|
|
|
2007-03-04 04:45:26 +01:00
|
|
|
[system.hypervisor_desc]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2013-03-05 05:33:47 +01:00
|
|
|
bandwidth=0.000000
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2008-09-28 23:16:26 +02:00
|
|
|
latency=60
|
2008-07-22 23:00:18 +02:00
|
|
|
latency_var=0
|
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=133446500352:133446508543
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[5]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.intrctrl]
|
|
|
|
type=IntrControl
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
sys=system
|
|
|
|
|
|
|
|
[system.iobus]
|
2014-09-22 05:04:39 +02:00
|
|
|
type=NoncoherentXBar
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2015-07-04 17:43:47 +02:00
|
|
|
forward_latency=1
|
|
|
|
frontend_latency=2
|
|
|
|
response_latency=2
|
2010-08-17 14:06:22 +02:00
|
|
|
use_default_range=false
|
2015-07-04 17:43:47 +02:00
|
|
|
width=16
|
2012-05-09 20:52:14 +02:00
|
|
|
master=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.disk0.pio
|
|
|
|
slave=system.bridge.master
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.membus]
|
2014-09-22 05:04:39 +02:00
|
|
|
type=CoherentXBar
|
2009-04-22 07:55:52 +02:00
|
|
|
children=badaddr_responder
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2015-07-04 17:43:47 +02:00
|
|
|
forward_latency=4
|
|
|
|
frontend_latency=3
|
|
|
|
response_latency=2
|
2014-09-22 05:04:39 +02:00
|
|
|
snoop_filter=Null
|
2015-07-04 17:43:47 +02:00
|
|
|
snoop_response_latency=4
|
2013-03-05 05:33:47 +01:00
|
|
|
system=system
|
2010-08-17 14:06:22 +02:00
|
|
|
use_default_range=false
|
2015-07-04 17:43:47 +02:00
|
|
|
width=16
|
2009-04-22 07:55:52 +02:00
|
|
|
default=system.membus.badaddr_responder.pio
|
2013-09-15 20:45:59 +02:00
|
|
|
master=system.t1000.iob.pio system.t1000.htod.pio system.bridge.slave system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.physmem0.port system.physmem1.port
|
2012-05-09 20:52:14 +02:00
|
|
|
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2009-04-22 07:55:52 +02:00
|
|
|
[system.membus.badaddr_responder]
|
2007-03-04 04:45:26 +01:00
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=0
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=true
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=false
|
|
|
|
warn_access=
|
|
|
|
pio=system.membus.default
|
|
|
|
|
|
|
|
[system.nvram]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2013-03-05 05:33:47 +01:00
|
|
|
bandwidth=0.000000
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2008-09-28 23:16:26 +02:00
|
|
|
latency=60
|
2008-07-22 23:00:18 +02:00
|
|
|
latency_var=0
|
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=133429198848:133429207039
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[4]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.partition_desc]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2013-03-05 05:33:47 +01:00
|
|
|
bandwidth=0.000000
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2008-09-28 23:16:26 +02:00
|
|
|
latency=60
|
2008-07-22 23:00:18 +02:00
|
|
|
latency_var=0
|
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=133445976064:133445984255
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[6]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2013-09-15 20:45:59 +02:00
|
|
|
[system.physmem0]
|
|
|
|
type=SimpleMemory
|
|
|
|
bandwidth=0.000000
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2013-09-15 20:45:59 +02:00
|
|
|
latency=60
|
|
|
|
latency_var=0
|
2008-07-22 23:00:18 +02:00
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=1048576:68157439
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[7]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2013-09-15 20:45:59 +02:00
|
|
|
[system.physmem1]
|
|
|
|
type=SimpleMemory
|
|
|
|
bandwidth=0.000000
|
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2013-09-15 20:45:59 +02:00
|
|
|
latency=60
|
|
|
|
latency_var=0
|
2008-07-22 23:00:18 +02:00
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=2147483648:2415919103
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[8]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.rom]
|
2012-05-09 20:52:14 +02:00
|
|
|
type=SimpleMemory
|
2013-03-05 05:33:47 +01:00
|
|
|
bandwidth=0.000000
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
|
|
|
conf_table_reported=true
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2012-05-09 20:52:14 +02:00
|
|
|
in_addr_map=true
|
2008-09-28 23:16:26 +02:00
|
|
|
latency=60
|
2008-07-22 23:00:18 +02:00
|
|
|
latency_var=0
|
|
|
|
null=false
|
2007-03-04 04:45:26 +01:00
|
|
|
range=1099243192320:1099251580927
|
2013-09-15 20:45:59 +02:00
|
|
|
port=system.membus.master[3]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000]
|
|
|
|
type=T1000
|
2008-07-22 23:00:18 +02:00
|
|
|
children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hterm htod hvuart iob pterm puart0
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
intrctrl=system.intrctrl
|
|
|
|
system=system
|
|
|
|
|
|
|
|
[system.t1000.fake_clk]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=644245094400
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=4294967296
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=false
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[0]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_jbi]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=549755813888
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=4294967296
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=false
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[11]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2_1]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=725849473024
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=1
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[2]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2_2]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=725849473088
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=1
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[3]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2_3]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=725849473152
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=1
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[4]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2_4]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=725849473216
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=1
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[5]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2esr_1]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=734439407616
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=0
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[6]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2esr_2]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=734439407680
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=0
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[7]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2esr_3]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=734439407744
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=0
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[8]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_l2esr_4]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=734439407808
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=8
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=0
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=true
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[9]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_membnks]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=648540061696
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=16384
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=0
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=false
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[1]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.fake_ssi]
|
|
|
|
type=IsaFake
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2011-11-28 10:19:57 +01:00
|
|
|
fake_mem=false
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=1095216660480
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_size=268435456
|
|
|
|
ret_bad_addr=false
|
|
|
|
ret_data16=65535
|
|
|
|
ret_data32=4294967295
|
|
|
|
ret_data64=18446744073709551615
|
|
|
|
ret_data8=255
|
|
|
|
system=system
|
|
|
|
update_data=false
|
|
|
|
warn_access=
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[10]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2008-07-22 23:00:18 +02:00
|
|
|
[system.t1000.hterm]
|
|
|
|
type=Terminal
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
intr_control=system.intrctrl
|
|
|
|
number=0
|
2008-07-22 23:00:18 +02:00
|
|
|
output=true
|
2007-03-04 04:45:26 +01:00
|
|
|
port=3456
|
|
|
|
|
|
|
|
[system.t1000.htod]
|
|
|
|
type=DumbTOD
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=1099255906296
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
system=system
|
2007-08-27 05:27:53 +02:00
|
|
|
time=Thu Jan 1 00:00:00 2009
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.membus.master[1]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.hvuart]
|
|
|
|
type=Uart8250
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=1099255955456
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
platform=system.t1000
|
|
|
|
system=system
|
2008-07-22 23:00:18 +02:00
|
|
|
terminal=system.t1000.hterm
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[13]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
|
|
|
[system.t1000.iob]
|
|
|
|
type=Iob
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_latency=2
|
|
|
|
platform=system.t1000
|
|
|
|
system=system
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.membus.master[0]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2008-07-22 23:00:18 +02:00
|
|
|
[system.t1000.pterm]
|
|
|
|
type=Terminal
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
intr_control=system.intrctrl
|
|
|
|
number=0
|
2008-07-22 23:00:18 +02:00
|
|
|
output=true
|
2007-03-04 04:45:26 +01:00
|
|
|
port=3456
|
|
|
|
|
|
|
|
[system.t1000.puart0]
|
|
|
|
type=Uart8250
|
2013-09-15 20:45:59 +02:00
|
|
|
clk_domain=system.clk_domain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2007-03-04 04:45:26 +01:00
|
|
|
pio_addr=133412421632
|
2013-03-05 05:33:47 +01:00
|
|
|
pio_latency=200
|
2007-03-04 04:45:26 +01:00
|
|
|
platform=system.t1000
|
|
|
|
system=system
|
2008-07-22 23:00:18 +02:00
|
|
|
terminal=system.t1000.pterm
|
2012-05-09 20:52:14 +02:00
|
|
|
pio=system.iobus.master[12]
|
2007-03-04 04:45:26 +01:00
|
|
|
|
2013-09-15 20:45:59 +02:00
|
|
|
[system.voltage_domain]
|
|
|
|
type=VoltageDomain
|
2014-05-12 23:22:17 +02:00
|
|
|
eventq_index=0
|
2013-09-15 20:45:59 +02:00
|
|
|
voltage=1.000000
|
|
|
|
|