add a sparc fs regression
src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
--HG--
extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
This commit is contained in:
Ali Saidi
parent
82874eefca
commit
a81143f06a
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@ -263,10 +263,9 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
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{
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// Only handle interrupts for the moment... Cpu Idle/reset/resume will be
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// later
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if (type != 0) {
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warn("Ignoring IntVecDis write\n");
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if (type != 0)
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return;
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}
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assert(type == 0);
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ic->post(cpu_id, SparcISA::IT_INT_VEC, vector);
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}
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@ -203,6 +203,9 @@ if env['FULL_SYSTEM']:
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'tsunami-simple-atomic-dual',
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'tsunami-simple-timing-dual',
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'twosys-tsunami-simple-atomic']
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if env['TARGET_ISA'] == 'sparc':
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configs += ['t1000-simple-atomic',
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't1000-simple-timing']
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else:
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configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest']
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39
tests/configs/t1000-simple-atomic.py
Normal file
39
tests/configs/t1000-simple-atomic.py
Normal file
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@ -0,0 +1,39 @@
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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import m5
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from m5.objects import *
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m5.AddToPath('../configs/common')
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import FSConfig
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cpu = AtomicSimpleCPU(cpu_id=0)
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system = FSConfig.makeSparcSystem('atomic')
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system.cpu = cpu
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cpu.connectMemPorts(system.membus)
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root = Root(clock = '2GHz', system = system)
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@ -0,0 +1,454 @@
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[root]
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type=Root
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children=system
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checkpoint=
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clock=2000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[system]
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type=SparcSystem
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children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
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boot_cpu_frequency=1
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boot_osflags=a
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hypervisor_addr=1099243257856
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hypervisor_bin=/dist/m5/system/binaries/q_new.bin
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hypervisor_desc=system.hypervisor_desc
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hypervisor_desc_addr=133446500352
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hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
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init_param=0
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kernel=
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mem_mode=atomic
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nvram=system.nvram
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nvram_addr=133429198848
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nvram_bin=/dist/m5/system/binaries/nvram1
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openboot_addr=1099243716608
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openboot_bin=/dist/m5/system/binaries/openboot_new.bin
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partition_desc=system.partition_desc
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partition_desc_addr=133445976064
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partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
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physmem=system.physmem
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readfile=tests/halt.sh
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reset_addr=1099243192320
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reset_bin=/dist/m5/system/binaries/reset_new.bin
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rom=system.rom
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symbolfile=
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[system.bridge]
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type=Bridge
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delay=0
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queue_size_a=16
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queue_size_b=16
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write_ack=false
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side_a=system.iobus.port[14]
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side_b=system.membus.port[2]
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[system.cpu]
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type=AtomicSimpleCPU
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children=dtb itb
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clock=1
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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phase=0
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profile=0
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progress_interval=0
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simulate_stalls=false
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system=system
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width=1
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dcache_port=system.membus.port[10]
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icache_port=system.membus.port[9]
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[system.cpu.dtb]
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type=SparcDTB
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size=64
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[system.cpu.itb]
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type=SparcITB
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size=64
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[system.disk0]
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type=MmDisk
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children=image
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image=system.disk0.image
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pio_addr=134217728000
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pio_latency=2
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platform=system.t1000
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system=system
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pio=system.iobus.port[15]
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[system.disk0.image]
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type=CowDiskImage
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children=child
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child=system.disk0.image.child
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read_only=false
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table_size=65536
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[system.disk0.image.child]
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type=RawDiskImage
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image_file=/dist/m5/system/disks/disk.s10hw2
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read_only=true
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[system.hypervisor_desc]
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type=PhysicalMemory
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file=
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latency=1
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range=133446500352:133446508543
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zero=false
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port=system.membus.port[7]
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[system.intrctrl]
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type=IntrControl
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sys=system
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[system.iobus]
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type=Bus
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children=responder
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bus_id=0
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clock=2
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responder_set=false
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width=64
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default=system.iobus.responder.pio
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port=system.t1000.fake_clk.pio system.t1000.fake_membnks.pio system.t1000.fake_l2_1.pio system.t1000.fake_l2_2.pio system.t1000.fake_l2_3.pio system.t1000.fake_l2_4.pio system.t1000.fake_l2esr_1.pio system.t1000.fake_l2esr_2.pio system.t1000.fake_l2esr_3.pio system.t1000.fake_l2esr_4.pio system.t1000.fake_ssi.pio system.t1000.fake_jbi.pio system.t1000.puart0.pio system.t1000.hvuart.pio system.bridge.side_a system.disk0.pio
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[system.iobus.responder]
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type=IsaFake
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pio_addr=0
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pio_latency=0
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pio_size=8
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platform=system.t1000
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ret_bad_addr=true
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.default
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[system.membus]
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type=Bus
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children=responder
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bus_id=1
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clock=2
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responder_set=false
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width=64
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default=system.membus.responder.pio
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port=system.t1000.iob.pio system.t1000.htod.pio system.bridge.side_b system.physmem.port system.physmem2.port system.rom.port system.nvram.port system.hypervisor_desc.port system.partition_desc.port system.cpu.icache_port system.cpu.dcache_port
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[system.membus.responder]
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type=IsaFake
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pio_addr=0
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pio_latency=0
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pio_size=8
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platform=system.t1000
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ret_bad_addr=true
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.membus.default
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[system.nvram]
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type=PhysicalMemory
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file=
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latency=1
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range=133429198848:133429207039
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zero=false
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port=system.membus.port[6]
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[system.partition_desc]
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type=PhysicalMemory
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file=
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latency=1
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range=133445976064:133445984255
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zero=false
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port=system.membus.port[8]
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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range=1048576:68157439
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zero=true
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port=system.membus.port[3]
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[system.physmem2]
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type=PhysicalMemory
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file=
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latency=1
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range=2147483648:2415919103
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zero=true
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port=system.membus.port[4]
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[system.rom]
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type=PhysicalMemory
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file=
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latency=1
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range=1099243192320:1099251580927
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zero=false
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port=system.membus.port[5]
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[system.t1000]
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type=T1000
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children=fake_clk fake_jbi fake_l2_1 fake_l2_2 fake_l2_3 fake_l2_4 fake_l2esr_1 fake_l2esr_2 fake_l2esr_3 fake_l2esr_4 fake_membnks fake_ssi hconsole htod hvuart iob pconsole puart0
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intrctrl=system.intrctrl
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system=system
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[system.t1000.fake_clk]
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type=IsaFake
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pio_addr=644245094400
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pio_latency=2
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pio_size=4294967296
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platform=system.t1000
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[0]
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[system.t1000.fake_jbi]
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type=IsaFake
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pio_addr=549755813888
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pio_latency=2
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pio_size=4294967296
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platform=system.t1000
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
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ret_data64=18446744073709551615
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ret_data8=255
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system=system
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update_data=false
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warn_access=
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pio=system.iobus.port[11]
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[system.t1000.fake_l2_1]
|
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type=IsaFake
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pio_addr=725849473024
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pio_latency=2
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pio_size=8
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platform=system.t1000
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ret_bad_addr=false
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ret_data16=65535
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ret_data32=4294967295
|
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ret_data64=1
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ret_data8=255
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system=system
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||||
update_data=true
|
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warn_access=
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pio=system.iobus.port[2]
|
||||
|
||||
[system.t1000.fake_l2_2]
|
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type=IsaFake
|
||||
pio_addr=725849473088
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[3]
|
||||
|
||||
[system.t1000.fake_l2_3]
|
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type=IsaFake
|
||||
pio_addr=725849473152
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
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pio=system.iobus.port[4]
|
||||
|
||||
[system.t1000.fake_l2_4]
|
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type=IsaFake
|
||||
pio_addr=725849473216
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[5]
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
pio_addr=734439407616
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[6]
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
pio_addr=734439407680
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[7]
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
pio_addr=734439407744
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[8]
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
pio_addr=734439407808
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=true
|
||||
warn_access=
|
||||
pio=system.iobus.port[9]
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
pio_addr=648540061696
|
||||
pio_latency=2
|
||||
pio_size=16384
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[1]
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
pio_addr=1095216660480
|
||||
pio_latency=2
|
||||
pio_size=268435456
|
||||
platform=system.t1000
|
||||
ret_bad_addr=false
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
ret_data8=255
|
||||
system=system
|
||||
update_data=false
|
||||
warn_access=
|
||||
pio=system.iobus.port[10]
|
||||
|
||||
[system.t1000.hconsole]
|
||||
type=SimConsole
|
||||
append_name=true
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=console
|
||||
port=3456
|
||||
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
pio_addr=1099255906296
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
time=2009 1 1 0 0 0 3 1
|
||||
pio=system.membus.port[1]
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
pio_addr=1099255955456
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
sim_console=system.t1000.hconsole
|
||||
system=system
|
||||
pio=system.iobus.port[13]
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
pio=system.membus.port[0]
|
||||
|
||||
[system.t1000.pconsole]
|
||||
type=SimConsole
|
||||
append_name=true
|
||||
intr_control=system.intrctrl
|
||||
number=0
|
||||
output=console
|
||||
port=3456
|
||||
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
pio_addr=133412421632
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
sim_console=system.t1000.pconsole
|
||||
system=system
|
||||
pio=system.iobus.port[12]
|
||||
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
[root]
|
||||
type=Root
|
||||
clock=2000000000
|
||||
max_tick=0
|
||||
progress_interval=0
|
||||
output_file=cout
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[1048576,68157439]
|
||||
latency=1
|
||||
zero=true
|
||||
|
||||
[system.rom]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[1099243192320,1099251580927]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system.nvram]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[133429198848,133429207039]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system.hypervisor_desc]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[133446500352,133446508543]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system.partition_desc]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[133445976064,133445984255]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=SparcSystem
|
||||
physmem=system.physmem
|
||||
rom=system.rom
|
||||
nvram=system.nvram
|
||||
hypervisor_desc=system.hypervisor_desc
|
||||
partition_desc=system.partition_desc
|
||||
mem_mode=atomic
|
||||
reset_addr=1099243192320
|
||||
hypervisor_addr=1099243257856
|
||||
openboot_addr=1099243716608
|
||||
nvram_addr=133429198848
|
||||
hypervisor_desc_addr=133446500352
|
||||
partition_desc_addr=133445976064
|
||||
kernel=
|
||||
reset_bin=/dist/m5/system/binaries/reset_new.bin
|
||||
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
|
||||
openboot_bin=/dist/m5/system/binaries/openboot_new.bin
|
||||
nvram_bin=/dist/m5/system/binaries/nvram1
|
||||
hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
|
||||
partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
|
||||
boot_cpu_frequency=1
|
||||
boot_osflags=a
|
||||
readfile=tests/halt.sh
|
||||
init_param=0
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
bus_id=1
|
||||
clock=2
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.intrctrl]
|
||||
type=IntrControl
|
||||
sys=system
|
||||
|
||||
[system.t1000]
|
||||
type=T1000
|
||||
system=system
|
||||
intrctrl=system.intrctrl
|
||||
|
||||
[system.membus.responder]
|
||||
type=IsaFake
|
||||
pio_addr=0
|
||||
pio_latency=0
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.physmem2]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
range=[2147483648,2415919103]
|
||||
latency=1
|
||||
zero=true
|
||||
|
||||
[system.bridge]
|
||||
type=Bridge
|
||||
queue_size_a=16
|
||||
queue_size_b=16
|
||||
delay=0
|
||||
write_ack=false
|
||||
|
||||
[system.disk0.image.child]
|
||||
type=RawDiskImage
|
||||
image_file=/dist/m5/system/disks/disk.s10hw2
|
||||
read_only=true
|
||||
|
||||
[system.disk0.image]
|
||||
type=CowDiskImage
|
||||
child=system.disk0.image.child
|
||||
image_file=
|
||||
table_size=65536
|
||||
read_only=false
|
||||
|
||||
[system.disk0]
|
||||
type=MmDisk
|
||||
pio_addr=134217728000
|
||||
pio_latency=2
|
||||
// pio_size not specified
|
||||
platform=system.t1000
|
||||
system=system
|
||||
image=system.disk0.image
|
||||
|
||||
[system.t1000.hconsole]
|
||||
type=SimConsole
|
||||
intr_control=system.intrctrl
|
||||
output=console
|
||||
port=3456
|
||||
append_name=true
|
||||
number=0
|
||||
|
||||
[system.t1000.hvuart]
|
||||
type=Uart8250
|
||||
pio_addr=1099255955456
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
sim_console=system.t1000.hconsole
|
||||
system=system
|
||||
|
||||
[system.t1000.htod]
|
||||
type=DumbTOD
|
||||
pio_addr=1099255906296
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
time=2009 1 1 0 0 0 3 1
|
||||
|
||||
[system.t1000.pconsole]
|
||||
type=SimConsole
|
||||
intr_control=system.intrctrl
|
||||
output=console
|
||||
port=3456
|
||||
append_name=true
|
||||
number=0
|
||||
|
||||
[system.t1000.puart0]
|
||||
type=Uart8250
|
||||
pio_addr=133412421632
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
sim_console=system.t1000.pconsole
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_membnks]
|
||||
type=IsaFake
|
||||
pio_addr=648540061696
|
||||
pio_latency=2
|
||||
pio_size=16384
|
||||
ret_bad_addr=false
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_ssi]
|
||||
type=IsaFake
|
||||
pio_addr=1095216660480
|
||||
pio_latency=2
|
||||
pio_size=268435456
|
||||
ret_bad_addr=false
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2_4]
|
||||
type=IsaFake
|
||||
pio_addr=725849473216
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2_1]
|
||||
type=IsaFake
|
||||
pio_addr=725849473024
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2_2]
|
||||
type=IsaFake
|
||||
pio_addr=725849473088
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2_3]
|
||||
type=IsaFake
|
||||
pio_addr=725849473152
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=1
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2esr_3]
|
||||
type=IsaFake
|
||||
pio_addr=734439407744
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2esr_2]
|
||||
type=IsaFake
|
||||
pio_addr=734439407680
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2esr_1]
|
||||
type=IsaFake
|
||||
pio_addr=734439407616
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_l2esr_4]
|
||||
type=IsaFake
|
||||
pio_addr=734439407808
|
||||
pio_latency=2
|
||||
pio_size=8
|
||||
ret_bad_addr=false
|
||||
update_data=true
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=0
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.iob]
|
||||
type=Iob
|
||||
pio_latency=2
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_clk]
|
||||
type=IsaFake
|
||||
pio_addr=644245094400
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.t1000.fake_jbi]
|
||||
type=IsaFake
|
||||
pio_addr=549755813888
|
||||
pio_latency=2
|
||||
pio_size=4294967296
|
||||
ret_bad_addr=false
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.iobus]
|
||||
type=Bus
|
||||
bus_id=0
|
||||
clock=2
|
||||
width=64
|
||||
responder_set=false
|
||||
|
||||
[system.iobus.responder]
|
||||
type=IsaFake
|
||||
pio_addr=0
|
||||
pio_latency=0
|
||||
pio_size=8
|
||||
ret_bad_addr=true
|
||||
update_data=false
|
||||
warn_access=
|
||||
ret_data8=255
|
||||
ret_data16=65535
|
||||
ret_data32=4294967295
|
||||
ret_data64=18446744073709551615
|
||||
platform=system.t1000
|
||||
system=system
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcITB
|
||||
size=64
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcDTB
|
||||
size=64
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
max_insts_any_thread=0
|
||||
max_insts_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
cpu_id=0
|
||||
itb=system.cpu.itb
|
||||
dtb=system.cpu.dtb
|
||||
profile=0
|
||||
do_quiesce=true
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
clock=1
|
||||
phase=0
|
||||
defer_registration=false
|
||||
width=1
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
cpu
|
||||
|
||||
Sun Fire T2000, No Keyboard
|
||||
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
|
||||
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
|
||||
[saidi obp #30]
|
||||
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
|
||||
|
||||
|
||||
|
||||
Boot device: /virtual-devices/disk@0 File and args: -vV
|
||||
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
|
||||
FCode UFS Reader 1.12 00/07/17 15:48:16.
|
||||
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
|
||||
Loading: /platform/sun4v/ufsboot
|
||||
device path '/virtual-devices@100/disk@0:a'
|
||||
The boot filesystem is logging.
|
||||
The ufs log is empty and will not be used.
|
||||
standalone = `kernel/sparcv9/unix', args = `-v'
|
||||
|Elf64 client
|
||||
Size: /-\|/-\|0x76e40+/-\|/-\|/-\|/-\0x1c872+|/-\0x3123a Bytes
|
||||
modpath: /platform/sun4v/kernel /kernel /usr/kernel
|
||||
|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-module /platform/sun4v/kernel/sparcv9/unix: text at [0x1000000, 0x1076e3f] data at 0x1800000
|
||||
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
|
||||
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738, 0x11dd437] data at 0x18531c0
|
||||
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438, 0x11dd43f] data at 0x18a4be0
|
||||
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at [0x11dd440, 0x11e06ff] data at 0x18a5300
|
||||
\
SunOS Release 5.10 Version Generic_118822-23 64-bit
|
||||
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
|
||||
Use is subject to license terms.
|
||||
|/-\|/-\|/-\|/-\|/-Ethernet address = 0:80:3:de:ad:3
|
||||
\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/mem = 262144K (0x10000000)
|
||||
avail mem = 237879296
|
||||
root nexus = Sun Fire T2000
|
||||
pseudo0 at root
|
||||
pseudo0 is /pseudo
|
||||
scsi_vhci0 at root
|
||||
scsi_vhci0 is /scsi_vhci
|
||||
virtual-device: hsimd0
|
||||
hsimd0 is /virtual-devices@100/disk@0
|
||||
root on /virtual-devices@100/disk@0:a fstype ufs
|
||||
pseudo-device: dld0
|
||||
dld0 is /pseudo/dld@0
|
||||
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
|
||||
iscsi0 at root
|
||||
iscsi0 is /iscsi
|
||||
Hostname: unknown
|
||||
Loading M5 readfile script...
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1214495 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 409828 # Number of bytes of host memory used
|
||||
host_seconds 1828.73 # Real time elapsed on the host
|
||||
host_tick_rate 1214601 # Simulator tick rate (ticks/s)
|
||||
sim_freq 2000000000 # Frequency of simulated ticks
|
||||
sim_insts 2220985165 # Number of instructions simulated
|
||||
sim_seconds 1.110589 # Number of seconds simulated
|
||||
sim_ticks 2221178828 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2221178829 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2220985165 # Number of instructions executed
|
||||
system.cpu.num_refs 545896474 # Number of memory references
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
Warning: rounding error > tolerance
|
||||
0.002000 rounded to 0
|
||||
Warning: rounding error > tolerance
|
||||
0.002000 rounded to 0
|
||||
warn: No kernel set for full system simulation. Assuming you know what you're doing...
|
||||
Listening for t1000 connection on port 3456
|
||||
Listening for t1000 connection on port 3457
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Ignoring write to SPARC ERROR regsiter
|
||||
warn: Ignoring write to SPARC ERROR regsiter
|
||||
warn: Don't know what interrupt to clear for console.
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2006
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 3 2007 19:48:02
|
||||
M5 started Sat Mar 3 19:58:15 2007
|
||||
M5 executing on zeep
|
||||
command line: build/SPARC_FS/m5.fast -d build/SPARC_FS/tests/fast/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic tests/run.py long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
|
||||
Exiting @ tick 2221178828 because m5_exit instruction encountered
|
||||
29
tests/long/80.solaris-boot/test.py
Normal file
29
tests/long/80.solaris-boot/test.py
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
# Copyright (c) 2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Ali Saidi
|
||||
|
||||
root.system.readfile = os.path.join(tests_root, 'halt.sh')
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
#! /usr/bin/env python
|
||||
# Copyright (c) 2005-2006 The Regents of The University of Michigan
|
||||
# Copyright (c) 2005-2007 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
|
|
@ -39,7 +39,7 @@ optparser.add_option('-v', '--verbose', dest='verbose', action='store_true',
|
|||
default=False,
|
||||
help='echo commands before executing')
|
||||
optparser.add_option('--builds', dest='builds',
|
||||
default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE',
|
||||
default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE,SPARC_FS',
|
||||
help='comma-separated list of build targets to test '
|
||||
" (default: '%default')" )
|
||||
optparser.add_option('--variants', dest='variants',
|
||||
|
|
|
|||
Loading…
Reference in a new issue