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gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

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X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- Begin Simulation Statistics ----------
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
sim_seconds 5.112155 # Number of seconds simulated
sim_ticks 5112155173500 # Number of ticks simulated
final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
host_inst_rate 1096092 # Simulator instruction rate (inst/s)
host_op_rate 2244090 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 28012193632 # Simulator tick rate (ticks/s)
host_mem_usage 637772 # Number of bytes of host memory used
host_seconds 182.50 # Real time elapsed on the host
sim_insts 200033988 # Number of instructions simulated
sim_ops 409540726 # Number of ops (including micro ops) simulated
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 13903768 # Transaction distribution
system.membus.trans_dist::ReadResp 13903768 # Transaction distribution
system.membus.trans_dist::WriteReq 13911 # Transaction distribution
system.membus.trans_dist::WriteResp 13911 # Transaction distribution
system.membus.trans_dist::Writeback 98349 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution
system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
system.membus.trans_dist::MessageResp 1696 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoops 0 # Total snoops (count)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.snoop_fanout::samples 328677 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.membus.snoop_fanout::total 328677 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.tags.replacements 47573 # number of replacements
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.tags.tag_accesses 428652 # Number of tag accesses
system.iocache.tags.data_accesses 428652 # Number of data accesses
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses
system.iocache.ReadReq_misses::total 908 # number of ReadReq misses
system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses
system.iocache.demand_misses::total 908 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses
system.iocache.overall_misses::total 908 # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Update stats for CPU and cache changes This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
2014-09-03 13:42:59 +02:00
system.iocache.fast_writes 46720 # number of fast writes performed
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution
system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution
system.iobus.trans_dist::WriteReq 57692 # Transaction distribution
system.iobus.trans_dist::WriteResp 10972 # Transaction distribution
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.iobus.trans_dist::MessageReq 1696 # Transaction distribution
system.iobus.trans_dist::MessageResp 1696 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes)
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.numCycles 10224314318 # number of cpu cycles simulated
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.committedInsts 200033988 # Number of instructions committed
system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.num_func_calls 2308777 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
system.cpu.num_int_insts 374550150 # number of integer instructions
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_insts 0 # number of float instructions
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
system.cpu.num_mem_refs 35680563 # number of memory refs
system.cpu.num_load_insts 27249389 # Number of load instructions
system.cpu.num_store_insts 8431174 # Number of store instructions
system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.955601 # Percentage of idle cycles
system.cpu.Branches 43145769 # Number of branches fetched
system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
stats: Bump stats for the fixes, and mostly DRAM controller changes
2014-05-10 00:58:50 +02:00
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.op_class::total 409541761 # Class of executed instruction
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.tags.replacements 791952 # number of replacements
system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
system.cpu.icache.overall_hits::total 243645979 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
system.cpu.icache.overall_misses::total 792471 # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks
system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.replacements 1623441 # number of replacements
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
stats: update stats for cache occupancy and clock domain changes
2014-01-24 22:29:33 +01:00
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits
system.cpu.dcache.overall_hits::total 20190999 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses
system.cpu.dcache.overall_misses::total 1626230 # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
system.cpu.dcache.writebacks::total 1536849 # number of writebacks
Tests: Update stats due to addition of fence microop
2011-11-05 21:32:23 +01:00
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoops 48008 # Total snoops (count)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
system.cpu.l2cache.tags.replacements 106197 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
stats: Update x86 stats after x87 fixes The updates to the x87 caused the stats for several regressions to change. This was mainly caused by the addition of a working 32-bit and 80-bit FP load instruction and xsave support.
2013-10-02 11:03:38 +02:00
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses)
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses)
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
stats: Bump stats for filter, crossbar and config changes This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
2014-09-20 23:18:53 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
stats: updates due to changes to x86, stale configs.
2014-10-11 23:18:51 +02:00
system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
system.cpu.l2cache.writebacks::total 98349 # number of writebacks
Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats.
2012-10-15 14:12:21 +02:00
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
X86: Add stats for the new x86 fs regressions.
2011-02-07 10:23:16 +01:00
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink