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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
sim_seconds 51.317219 # Number of seconds simulated
sim_ticks 51317219225000 # Number of ticks simulated
final_tick 51317219225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
host_inst_rate 203116 # Simulator instruction rate (inst/s)
host_op_rate 238662 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11427931870 # Simulator tick rate (ticks/s)
host_mem_usage 741344 # Number of bytes of host memory used
host_seconds 4490.51 # Real time elapsed on the host
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
sim_insts 912094204 # Number of instructions simulated
sim_ops 1071714405 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.physmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 178240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 158592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3667840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 28126168 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 173888 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 153280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3614336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 28857840 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory
system.physmem.bytes_read::total 65359176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3667840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3614336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7282176 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 83655232 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::total 83675812 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2785 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2478 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 57310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 439479 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2717 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2395 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 56474 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 450909 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1021250 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1307113 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1309686 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3473 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 3090 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 71474 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 548084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2987 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 70431 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 562342 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8360 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1273631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 71474 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 70431 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 141905 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1630159 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1630560 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1630159 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3473 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 3090 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 71474 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 548485 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3388 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 70431 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 562342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2904191 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1021250 # Number of read requests accepted
system.physmem.writeReqs 1309686 # Number of write requests accepted
system.physmem.readBursts 1021250 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1309686 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 65325376 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 34624 # Total number of bytes read from write queue
system.physmem.bytesWritten 83676352 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 65359176 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 83675812 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.perBankRdBursts::0 59538 # Per bank write bursts
system.physmem.perBankRdBursts::1 65186 # Per bank write bursts
system.physmem.perBankRdBursts::2 59192 # Per bank write bursts
system.physmem.perBankRdBursts::3 61503 # Per bank write bursts
system.physmem.perBankRdBursts::4 61968 # Per bank write bursts
system.physmem.perBankRdBursts::5 71297 # Per bank write bursts
system.physmem.perBankRdBursts::6 63621 # Per bank write bursts
system.physmem.perBankRdBursts::7 62505 # Per bank write bursts
system.physmem.perBankRdBursts::8 57971 # Per bank write bursts
system.physmem.perBankRdBursts::9 85989 # Per bank write bursts
system.physmem.perBankRdBursts::10 63150 # Per bank write bursts
system.physmem.perBankRdBursts::11 64998 # Per bank write bursts
system.physmem.perBankRdBursts::12 58754 # Per bank write bursts
system.physmem.perBankRdBursts::13 64690 # Per bank write bursts
system.physmem.perBankRdBursts::14 59967 # Per bank write bursts
system.physmem.perBankRdBursts::15 60380 # Per bank write bursts
system.physmem.perBankWrBursts::0 78521 # Per bank write bursts
system.physmem.perBankWrBursts::1 82873 # Per bank write bursts
system.physmem.perBankWrBursts::2 79926 # Per bank write bursts
system.physmem.perBankWrBursts::3 82832 # Per bank write bursts
system.physmem.perBankWrBursts::4 82609 # Per bank write bursts
system.physmem.perBankWrBursts::5 88110 # Per bank write bursts
system.physmem.perBankWrBursts::6 81518 # Per bank write bursts
system.physmem.perBankWrBursts::7 82656 # Per bank write bursts
system.physmem.perBankWrBursts::8 78895 # Per bank write bursts
system.physmem.perBankWrBursts::9 84228 # Per bank write bursts
system.physmem.perBankWrBursts::10 80757 # Per bank write bursts
system.physmem.perBankWrBursts::11 83094 # Per bank write bursts
system.physmem.perBankWrBursts::12 78112 # Per bank write bursts
system.physmem.perBankWrBursts::13 83897 # Per bank write bursts
system.physmem.perBankWrBursts::14 79365 # Per bank write bursts
system.physmem.perBankWrBursts::15 80050 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.numWrRetry 115 # Number of times write queue was full causing retry
system.physmem.totGap 51317218019000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.readPktSize::6 1021235 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.writePktSize::6 1307113 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 561294 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 302542 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 104557 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 46549 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 783 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 524 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 668 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 481 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 1322 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 400 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 431 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 183 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 154 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 750 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 741 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 734 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 728 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 725 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 21632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 29719 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 41729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 50195 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 67312 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 74771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 78166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 83727 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 87147 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 84488 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 87764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 90437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 82620 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 80818 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 81373 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 72156 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 70724 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 67158 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 4349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 3302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2629 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2261 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 2214 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 2078 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1799 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1706 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1735 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1630 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1549 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1568 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1286 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1289 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1072 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 1105 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 1011 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 993 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 1046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 913 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 967 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 1108 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 839 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 828 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 850 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 858 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 478 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 296 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 578062 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 257.760143 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 153.645909 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 296.380743 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 251223 43.46% 43.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 144003 24.91% 68.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 55356 9.58% 77.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 27668 4.79% 82.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 20975 3.63% 86.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11890 2.06% 88.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10828 1.87% 90.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 7399 1.28% 91.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 48720 8.43% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 578062 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61477 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 16.602941 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 65.801588 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 61469 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61477 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61477 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.267189 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.511196 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 23.879627 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31 57149 92.96% 92.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63 2185 3.55% 96.51% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-95 1043 1.70% 98.21% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-127 635 1.03% 99.24% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-159 196 0.32% 99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-191 105 0.17% 99.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-223 30 0.05% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-287 29 0.05% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319 5 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351 5 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::448-479 2 0.00% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-511 4 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-543 2 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-607 3 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-639 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::736-767 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-895 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61477 # Writes before turning the bus around for reads
system.physmem.totQLat 27580144715 # Total ticks spent queuing
system.physmem.totMemAccLat 46718438465 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5103545000 # Total ticks spent in databus transfers
system.physmem.avgQLat 27020.58 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.avgMemAccLat 45770.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.63 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.63 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.physmem.busUtil 0.02 # Data bus utilization in percentage
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.54 # Average write queue length when enqueuing
system.physmem.readRowHits 791160 # Number of row buffer hits during reads
system.physmem.writeRowHits 958928 # Number of row buffer hits during writes
system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.34 # Row buffer hit rate for writes
system.physmem.avgGap 22015713.01 # Average gap between requests
system.physmem.pageHitRate 75.17 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2219328720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1210943250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3937471200 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4270611600 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1232390071935 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29709283194000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34305102423585 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.491159 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49423935419086 # Time in different power states
system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem_0.memoryStateTime::ACT 179688951414 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem_1.actEnergy 2150820000 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1173562500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4024012200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4201619040 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1230344610120 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29711077467000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34304762893740 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.484542 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49426892036602 # Time in different power states
system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.physmem_1.memoryStateTime::ACT 176725372148 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.branchPred.lookups 133997601 # Number of BP lookups
system.cpu0.branchPred.condPredicted 89911686 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5854244 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 89985465 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 61739918 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.branchPred.BTBHitPct 68.610990 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17379215 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 192773 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 4943112 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2622279 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 2320833 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 406549 # Number of mispredicted indirect branches.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walks 931838 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 931838 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17645 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95375 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 582006 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 349832 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2584.187553 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14750.130751 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 347090 99.22% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1907 0.55% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 488 0.14% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 130 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 48 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkWaitTime::total 349832 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 445532 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23200.793658 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 19017.924437 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16422.337995 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 338631 76.01% 76.01% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 97435 21.87% 97.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 7291 1.64% 99.51% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1212 0.27% 99.78% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 239 0.05% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 222 0.05% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-229375 191 0.04% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::229376-262143 178 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-294911 71 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::294912-327679 21 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::360448-393215 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 445532 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 361726794756 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.119484 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.718354 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 360638415756 99.70% 99.70% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7 594419500 0.16% 99.86% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11 206814500 0.06% 99.92% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15 128366500 0.04% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19 51460000 0.01% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23 27618000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27 28344500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31 44148500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35 6546000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39 549000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43 65000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47 32000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51 15500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 361726794756 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 95376 84.39% 84.39% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 17645 15.61% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 113021 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 931838 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 931838 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113021 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113021 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 1044859 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.read_hits 105631864 # DTB read hits
system.cpu0.dtb.read_misses 640489 # DTB read misses
system.cpu0.dtb.write_hits 81680668 # DTB write hits
system.cpu0.dtb.write_misses 291349 # DTB write misses
system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 55450 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9899 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.perms_faults 56099 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 106272353 # DTB read accesses
system.cpu0.dtb.write_accesses 81972017 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dtb.hits 187312532 # DTB hits
system.cpu0.dtb.misses 931838 # DTB misses
system.cpu0.dtb.accesses 188244370 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walks 102509 # Table walker walks requested
system.cpu0.itb.walker.walksLong 102509 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2958 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69563 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 14385 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 88124 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1419.845899 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 9093.034945 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 87142 98.89% 98.89% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 616 0.70% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 206 0.23% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 105 0.12% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 24 0.03% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 88124 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 86906 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 28693.715048 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24359.274514 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18506.887432 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 84671 97.43% 97.43% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 1946 2.24% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 187 0.22% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 65 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkCompletionTime::total 86906 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 610832410424 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.899859 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.300566 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 61230050100 10.02% 10.02% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 549548390324 89.97% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 48170500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 4945000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 599000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 205000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 50500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 610832410424 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 69563 95.92% 95.92% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2958 4.08% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 72521 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102509 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102509 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72521 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72521 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 175030 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 94735666 # ITB inst hits
system.cpu0.itb.inst_misses 102509 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.flush_tlb_mva_asid 22090 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 40899 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.perms_faults 193621 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.itb.inst_accesses 94838175 # ITB inst accesses
system.cpu0.itb.hits 94735666 # DTB hits
system.cpu0.itb.misses 102509 # DTB misses
system.cpu0.itb.accesses 94838175 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.numPwrStateTransitions 16108 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 8054 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 3370274965.000869 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 64926982226.426781 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3593 44.61% 44.61% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.18% 99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 1988782302928 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 8054 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 24173024656883 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 27144194568117 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.numCycles 677363519 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.icacheStallCycles 248081332 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 593905796 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 133997601 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81741412 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 389608891 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 13373506 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2523552 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 22024 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 2940 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 4870394 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 168493 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 2299 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 94525599 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3651769 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 39552 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 651966408 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.065387 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.317537 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.rateDist::0 506080688 77.62% 77.62% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 18214646 2.79% 80.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 18100947 2.78% 83.19% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13291875 2.04% 85.23% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 28751599 4.41% 89.64% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 8986592 1.38% 91.02% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9770458 1.50% 92.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8414345 1.29% 93.81% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 40355258 6.19% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.fetch.rateDist::total 651966408 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.197822 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.876790 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 201025214 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 326077447 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 105614620 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 13934386 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5312657 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19632987 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1393622 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 647334053 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4303710 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5312657 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 208746840 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 23221789 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 263564774 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 111697152 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 39420825 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 631864038 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 81982 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1845422 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1714455 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 19477575 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 3876 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 604366839 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 973584661 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 745191594 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 824988 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 507520310 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 96846524 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15772416 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13809695 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 77902092 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 101804436 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85844339 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13951597 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14791131 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 598600479 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15906116 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 599443694 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 871420 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 82277994 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 51785989 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 367722 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 651966408 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.919440 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.646692 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iq.issued_per_cycle::0 416000229 63.81% 63.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 100627614 15.43% 79.24% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 43369864 6.65% 85.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 31012057 4.76% 90.65% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 22935032 3.52% 94.17% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 16054599 2.46% 96.63% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 11112799 1.70% 98.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6483448 0.99% 99.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4370766 0.67% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iq.issued_per_cycle::total 651966408 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iq.fu_full::IntAlu 3017859 25.71% 25.71% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 24275 0.21% 25.92% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 3125 0.03% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.95% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4815194 41.03% 66.98% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3875781 33.02% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 50 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 407248355 67.94% 67.94% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1425936 0.24% 68.18% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 67925 0.01% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 173 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 60970 0.01% 68.20% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.20% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.20% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.20% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 107889592 18.00% 86.20% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 82750693 13.80% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iq.FU_type_0::total 599443694 # Type of FU issued
system.cpu0.iq.rate 0.884966 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11736234 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019579 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1862428500 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 696963642 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 577071065 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1032950 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 531195 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 457217 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 610628639 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 551239 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4761086 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 16972106 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 721660 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 8682994 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 4003221 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 7891299 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iew.iewSquashCycles 5312657 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 14923194 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 6733387 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 614655210 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1737208 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 101804436 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85844339 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 13513919 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 247440 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 6392978 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 721660 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2504975 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2708374 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5213349 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 592463883 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 105622287 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 6061529 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.iew.exec_nop 148615 # number of nop insts executed
system.cpu0.iew.exec_refs 187306165 # number of memory reference insts executed
system.cpu0.iew.exec_branches 109885900 # Number of branches executed
system.cpu0.iew.exec_stores 81683878 # Number of stores executed
system.cpu0.iew.exec_rate 0.874662 # Inst execution rate
system.cpu0.iew.wb_sent 578962486 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 577528282 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 284712169 # num instructions producing a value
system.cpu0.iew.wb_consumers 495210168 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.852612 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.574932 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 82335465 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 15538394 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4479878 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 637982242 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.834237 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.825466 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.commit.committed_per_cycle::0 441101470 69.14% 69.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 98311443 15.41% 84.55% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 33085662 5.19% 89.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 15424273 2.42% 92.15% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10896564 1.71% 93.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6486229 1.02% 94.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6026213 0.94% 95.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3904773 0.61% 96.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 22745615 3.57% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.commit.committed_per_cycle::total 637982242 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 452758888 # Number of instructions committed
system.cpu0.commit.committedOps 532228596 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.commit.refs 161993674 # Number of memory references committed
system.cpu0.commit.loads 84832329 # Number of loads committed
system.cpu0.commit.membars 3784982 # Number of memory barriers committed
system.cpu0.commit.branches 101373358 # Number of branches committed
system.cpu0.commit.fp_insts 437523 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 488401874 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13443378 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.commit.op_class_0::IntAlu 369014830 69.33% 69.33% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1117216 0.21% 69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 51029 0.01% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 51847 0.01% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 84832329 15.94% 85.50% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 77161345 14.50% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.commit.op_class_0::total 532228596 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22745615 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1225734406 # The number of ROB reads
system.cpu0.rob.rob_writes 1243135976 # The number of ROB writes
system.cpu0.timesIdled 4186507 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 25397111 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 54288384692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 452758888 # Number of Instructions Simulated
system.cpu0.committedOps 532228596 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.496080 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.496080 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.668413 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.668413 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 697890382 # number of integer regfile reads
system.cpu0.int_regfile_writes 412518994 # number of integer regfile writes
system.cpu0.fp_regfile_reads 828341 # number of floating regfile reads
system.cpu0.fp_regfile_writes 487008 # number of floating regfile writes
system.cpu0.cc_regfile_reads 127089396 # number of cc regfile reads
system.cpu0.cc_regfile_writes 128258211 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1206144502 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15679564 # number of misc regfile writes
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.replacements 10794532 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 308661870 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10795044 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.592924 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 302.186929 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 209.796481 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.590209 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.409759 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.tags.tag_accesses 1362392595 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1362392595 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.ReadReq_hits::cpu0.data 80965730 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 82351460 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 163317190 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67604275 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 69208699 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 136812974 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205804 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202560 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 408364 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173367 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153044 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 326411 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1817125 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1785316 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3602441 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2093741 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2052340 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4146081 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 148743372 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 151713203 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 300456575 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 148949176 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 151915763 # number of overall hits
system.cpu0.dcache.overall_hits::total 300864939 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6366558 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6514512 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12881070 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6631964 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6534144 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 13166108 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 653449 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 684365 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1337814 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 649747 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 591897 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1241644 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 332470 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 326805 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 659275 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 7 # number of StoreCondReq misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 13648269 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 13640553 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 27288822 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 14301718 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 14324918 # number of overall misses
system.cpu0.dcache.overall_misses::total 28626636 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 98775047500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 99225424000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 198000471500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 232617199289 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 234560003141 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 467177202430 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 15059699162 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13113954300 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 28173653462 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4294097000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4198180000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 8492277000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 82000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 238000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 320000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 346451945951 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 346899381441 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 693351327392 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 346451945951 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 346899381441 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 693351327392 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 87332288 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 88865972 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 176198260 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74236239 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 75742843 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 149979082 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 859253 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 886925 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1746178 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 823114 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 744941 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1568055 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149595 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2112121 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4261716 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2093747 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2052347 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4146094 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 162391641 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 165353756 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 327745397 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 163250894 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 166240681 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 329491575 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072900 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.073307 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.073106 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089336 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086267 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.087786 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760485 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.771615 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766138 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789377 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.794556 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791837 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154666 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154728 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154697 # miss rate for LoadLockedReq accesses
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084045 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.082493 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.083262 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087606 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.086170 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.086881 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15514.670172 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15231.443890 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15371.430440 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35075.160132 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35897.587066 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 35483.318413 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23177.789450 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22155.804642 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22690.604925 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12915.742774 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12846.131485 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12881.236206 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13666.666667 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 34000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24615.384615 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25384.314007 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25431.474915 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25407.887793 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24224.498480 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24216.500328 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 24220.496163 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 50251301 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 54501 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3623821 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1019 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.866938 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 53.484789 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 8249196 # number of writebacks
system.cpu0.dcache.writebacks::total 8249196 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3454316 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3599973 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 7054289 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5516594 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5434587 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10951181 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3628 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3364 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 6992 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204992 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 201546 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406538 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8974538 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 9037924 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 18012462 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8974538 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 9037924 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 18012462 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2912242 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2914539 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5826781 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1115370 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1099557 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2214927 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 644396 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 668916 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1313312 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 646119 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 588533 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234652 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 127478 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 125259 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 252737 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 7 # number of StoreCondReq MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 4673731 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 4602629 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 9276360 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 5318127 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 5271545 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 10589672 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17867 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15813 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18974 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14723 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36841 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30536 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45309693000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 45038920000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90348613000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40408833272 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40500038516 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80908871788 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10386373000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12065937500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22452310500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14266559663 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12400788300 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26667347963 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1747255500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1706730500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3453986000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 76000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 231000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 307000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99985085935 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97939746816 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 197924832751 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 110371458935 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110005684316 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 220377143251 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3393465500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2870779500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264245000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3393465500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2870779500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264245000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033347 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032797 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033069 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015025 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014517 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014768 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749949 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754197 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752107 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.784969 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790040 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787378 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059303 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059305 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059304 # mshr miss rate for LoadLockedReq accesses
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027835 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.028304 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032576 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031710 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.032139 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15558.354354 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15453.188309 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15505.750602 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36229.083866 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36833.050507 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36528.911241 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16117.997318 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18038.045883 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17095.945594 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22080.390242 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21070.676241 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21599.080521 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13706.329720 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13625.611732 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13666.325073 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12666.666667 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23615.384615 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21392.991153 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21279.087847 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21336.476026 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20753.821587 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20867.826096 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20810.573099 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189929.227067 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181545.532157 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.022565 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92111.112619 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94012.951926 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.047182 # average overall mshr uncacheable latency
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.replacements 16477862 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.835978 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 172394682 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 16478374 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.461875 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 287.122432 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 224.713546 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.560786 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.438894 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999680 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.tags.tag_accesses 206602499 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 206602499 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.ReadReq_hits::cpu0.inst 85625549 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 86769133 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 172394682 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 85625549 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 86769133 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 172394682 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 85625549 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 86769133 # number of overall hits
system.cpu0.icache.overall_hits::total 172394682 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8887589 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8841593 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17729182 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8887589 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8841593 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17729182 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8887589 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8841593 # number of overall misses
system.cpu0.icache.overall_misses::total 17729182 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 116686112381 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116433434872 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 233119547253 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 116686112381 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 116433434872 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 233119547253 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 116686112381 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 116433434872 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 233119547253 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 94513138 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 95610726 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 190123864 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 94513138 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 95610726 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 190123864 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 94513138 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 95610726 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 190123864 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.094035 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.092475 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.093251 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.094035 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.092475 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.093251 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.094035 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092475 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.093251 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13129.107611 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13168.829969 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13148.917263 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13148.917263 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13129.107611 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13168.829969 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13148.917263 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 88437 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.blocked::no_mshrs 7555 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.705758 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.icache.writebacks::writebacks 16477862 # number of writebacks
system.cpu0.icache.writebacks::total 16477862 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 628355 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 622192 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1250547 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 628355 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 622192 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1250547 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 628355 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 622192 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1250547 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8259234 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8219401 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 16478635 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8259234 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8219401 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 16478635 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8259234 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8219401 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16478635 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12438 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8200 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20638 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12438 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8200 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20638 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103445364915 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103197184413 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 206642549328 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103445364915 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103197184413 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 206642549328 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103445364915 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103197184413 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 206642549328 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086673 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.086673 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087387 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085967 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.086673 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12540.028305 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12524.813429 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12555.316916 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12540.028305 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency
system.cpu1.branchPred.lookups 135004521 # Number of BP lookups
system.cpu1.branchPred.condPredicted 90686520 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5841333 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 91602372 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 61971036 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.branchPred.BTBHitPct 67.652218 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17264827 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 189835 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 5144550 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2721808 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 2422742 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 415682 # Number of mispredicted indirect branches.
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walks 920636 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 920636 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17624 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92524 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 572462 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 348174 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2542.994307 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 15098.255497 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 345444 99.22% 99.22% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1949 0.56% 99.78% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.12% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 137 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 118 0.03% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 24 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 58 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::720896-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 348174 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 432733 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23053.791830 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18897.650182 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16323.118118 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 333564 77.08% 77.08% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 89713 20.73% 97.81% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7384 1.71% 99.52% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1176 0.27% 99.79% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 238 0.05% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 198 0.05% 99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 173 0.04% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 170 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 52 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 27 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 432733 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 314249886000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.018496 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.687233 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 313186458000 99.66% 99.66% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 582171000 0.19% 99.85% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 205657500 0.07% 99.91% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 123171000 0.04% 99.95% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 50673000 0.02% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 26248000 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 27458500 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 40663500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 6954500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39 344500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43 34000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47 16000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::52-55 4000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::56-59 2500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 314249886000 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 92524 84.00% 84.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 17624 16.00% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 110148 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 920636 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 920636 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110148 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110148 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 1030784 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.read_hits 107706385 # DTB read hits
system.cpu1.dtb.read_misses 633869 # DTB read misses
system.cpu1.dtb.write_hits 83022369 # DTB write hits
system.cpu1.dtb.write_misses 286767 # DTB write misses
system.cpu1.dtb.flush_tlb 1089 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 55426 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 9714 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.perms_faults 57000 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 108340254 # DTB read accesses
system.cpu1.dtb.write_accesses 83309136 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.dtb.hits 190728754 # DTB hits
system.cpu1.dtb.misses 920636 # DTB misses
system.cpu1.dtb.accesses 191649390 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walks 101988 # Table walker walks requested
system.cpu1.itb.walker.walksLong 101988 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3087 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69367 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 14377 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 87611 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1414.069010 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 8744.624659 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 86637 98.89% 98.89% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 608 0.69% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 209 0.24% 99.82% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 111 0.13% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 21 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 11 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 87611 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 86831 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28749.490389 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24437.163786 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18363.738628 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 45615 52.53% 52.53% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 39084 45.01% 97.54% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 938 1.08% 98.62% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 923 1.06% 99.69% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.11% 99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 11 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 86831 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 606307709128 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.900370 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.299888 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 60468146000 9.97% 9.97% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 545785217128 90.02% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 47888000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 5793500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 658000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 6500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 606307709128 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 69367 95.74% 95.74% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 3087 4.26% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 72454 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101988 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101988 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72454 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72454 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 174442 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 95828100 # ITB inst hits
system.cpu1.itb.inst_misses 101988 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_tlb 1089 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.flush_tlb_mva_asid 21973 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 40809 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.perms_faults 188352 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.itb.inst_accesses 95930088 # ITB inst accesses
system.cpu1.itb.hits 95828100 # DTB hits
system.cpu1.itb.misses 101988 # DTB misses
system.cpu1.itb.accesses 95930088 # DTB accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.cpu1.numPwrStateTransitions 16766 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 8383 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 2803271183.603841 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 54004965145.463799 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3515 41.93% 41.93% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.84% 99.77% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 1988782222956 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 8383 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 27817396892849 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 23499822332151 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.numCycles 668684774 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.icacheStallCycles 248375133 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 600185967 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 135004521 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 81957671 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 381222161 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13317970 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2536848 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 21164 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 2785 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 4727264 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 160612 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 2602 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 95618947 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3633834 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 39185 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 643707284 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.089618 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.340143 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.rateDist::0 496523035 77.13% 77.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 18305041 2.84% 79.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 18509005 2.88% 82.85% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13552167 2.11% 84.96% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 28450532 4.42% 89.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 9097899 1.41% 90.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9820940 1.53% 92.32% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8391092 1.30% 93.62% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 41057573 6.38% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.fetch.rateDist::total 643707284 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.201896 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.897562 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 201561818 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 315815468 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 107257676 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13770315 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5299898 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 19801436 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1379430 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 654914208 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4252969 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5299898 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 209252042 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 22880216 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 253975050 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 113199216 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 39098550 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 639470628 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 86957 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 2174171 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1609351 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 19507965 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 3945 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 611072160 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 980685418 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 753664877 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 843607 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 514110066 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 96962094 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15327241 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13321250 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 76568402 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 103346770 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 87233341 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13784187 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14730689 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 606543686 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15379714 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 607376538 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 875474 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 82437591 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 51624950 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 357944 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 643707284 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.943560 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.668311 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iq.issued_per_cycle::0 406849245 63.20% 63.20% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 99415625 15.44% 78.65% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 43745607 6.80% 85.44% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 31472621 4.89% 90.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 23315391 3.62% 93.96% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 16399031 2.55% 96.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 11324350 1.76% 98.26% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6634295 1.03% 99.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4551119 0.71% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iq.issued_per_cycle::total 643707284 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iq.fu_full::IntAlu 3079713 25.38% 25.38% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 23466 0.19% 25.57% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 2047 0.02% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.59% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4953216 40.82% 66.41% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 4075474 33.59% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 411722588 67.79% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1463458 0.24% 68.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 65529 0.01% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 206 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 66963 0.01% 68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 109966089 18.11% 86.15% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 84091577 13.85% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iq.FU_type_0::total 607376538 # Type of FU issued
system.cpu1.iq.rate 0.908315 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 12133916 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.019978 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1870398622 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 704521244 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 584421121 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1071128 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 544645 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 476254 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 618939378 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 571011 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4788717 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 16961682 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 19758 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 716289 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 8689454 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 3983377 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 8390309 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iew.iewSquashCycles 5299898 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14473954 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 6659801 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 622069689 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1729386 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 103346770 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 87233341 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 13033934 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 237234 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 6338314 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 716289 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2501247 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2722291 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 5223538 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 600362187 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 107695161 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 6106837 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.iew.exec_nop 146289 # number of nop insts executed
system.cpu1.iew.exec_refs 190717674 # number of memory reference insts executed
system.cpu1.iew.exec_branches 110987821 # Number of branches executed
system.cpu1.iew.exec_stores 83022513 # Number of stores executed
system.cpu1.iew.exec_rate 0.897825 # Inst execution rate
system.cpu1.iew.wb_sent 586317808 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 584897375 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 289057464 # num instructions producing a value
system.cpu1.iew.wb_consumers 502211172 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.874698 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575570 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 82490328 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 15021770 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4481976 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 629716363 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.856712 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.853018 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.commit.committed_per_cycle::0 432763054 68.72% 68.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 96847267 15.38% 84.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 33152549 5.26% 89.37% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 15677479 2.49% 91.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 11079326 1.76% 93.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6740057 1.07% 94.69% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 6209892 0.99% 95.67% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3949846 0.63% 96.30% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 23296893 3.70% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.commit.committed_per_cycle::total 629716363 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 459335316 # Number of instructions committed
system.cpu1.commit.committedOps 539485809 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.commit.refs 164928975 # Number of memory references committed
system.cpu1.commit.loads 86385088 # Number of loads committed
system.cpu1.commit.membars 3716704 # Number of memory barriers committed
system.cpu1.commit.branches 102438773 # Number of branches committed
system.cpu1.commit.fp_insts 458507 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 495134645 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13388221 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.commit.op_class_0::IntAlu 373316618 69.20% 69.20% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1132929 0.21% 69.41% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 49236 0.01% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 58009 0.01% 69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 86385088 16.01% 85.44% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 78543887 14.56% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu1.commit.op_class_0::total 539485809 # Class of committed instruction
system.cpu1.commit.bw_lim_events 23296893 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1224452307 # The number of ROB reads
system.cpu1.rob.rob_writes 1257969342 # The number of ROB writes
system.cpu1.timesIdled 4181395 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 24977490 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 46999639814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 459335316 # Number of Instructions Simulated
system.cpu1.committedOps 539485809 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.455766 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.455766 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.686924 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.686924 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 706650375 # number of integer regfile reads
system.cpu1.int_regfile_writes 418043743 # number of integer regfile writes
system.cpu1.fp_regfile_reads 853513 # number of floating regfile reads
system.cpu1.fp_regfile_writes 519324 # number of floating regfile writes
system.cpu1.cc_regfile_reads 128705619 # number of cc regfile reads
system.cpu1.cc_regfile_writes 129852515 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1200738028 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15156718 # number of misc regfile writes
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.iobus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 47815500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer2.occupancy 346000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
stats: Update to reflect changes to PCI handling
2015-12-05 01:11:25 +01:00
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer23.occupancy 25701500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer24.occupancy 40146500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.reqLayer25.occupancy 568673363 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.tags.replacements 115457 # number of replacements
system.iocache.tags.tagsinuse 10.425589 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.tags.warmup_cycle 13089213782000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.544365 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.881224 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.tags.tag_accesses 1039641 # Number of tag accesses
system.iocache.tags.data_accesses 1039641 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.iocache.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.demand_misses::realview.ide 115476 # number of demand (read+write) misses
system.iocache.demand_misses::total 115516 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.overall_misses::realview.ide 115476 # number of overall misses
system.iocache.overall_misses::total 115516 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5146000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1631213114 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1636359114 # number of ReadReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12815787249 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12815787249 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5497000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14447000363 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14452497363 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5497000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14447000363 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14452497363 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.demand_accesses::realview.ide 115476 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115516 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.overall_accesses::realview.ide 115476 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115516 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139081.081081 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 185112.700182 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 184920.229856 # average ReadReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120151.009235 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 120151.009235 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 137425 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125112.515695 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 137425 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 125108.250745 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125112.515695 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31781 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.blocked::no_mshrs 3407 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.328148 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.demand_mshr_misses::realview.ide 115476 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115516 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.overall_mshr_misses::realview.ide 115476 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115516 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3296000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1190613114 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1193909114 # number of ReadReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7475677012 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7475677012 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3497000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8666290126 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8669787126 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3497000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8666290126 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8669787126 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89081.081081 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135112.700182 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 134920.229856 # average ReadReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70086.224143 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70086.224143 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87425 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 75048.409418 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 75052.695090 # average overall mshr miss latency
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.tags.replacements 1414907 # number of replacements
system.l2c.tags.tagsinuse 65322.046709 # Cycle average of tags in use
system.l2c.tags.total_refs 51048957 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1478359 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 34.530826 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2400888500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 35689.019526 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.312182 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 256.355195 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4109.760843 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 10213.253541 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.614140 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 239.422394 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3052.672621 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 11431.636266 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.544571 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002492 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003912 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.062710 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.155842 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002542 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.046580 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.174433 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996735 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 63141 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 309 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2809 # Occupied blocks per task id
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.l2c.tags.age_task_id_blocks_1024::3 5038 # Occupied blocks per task id
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.tags.age_task_id_blocks_1024::4 54676 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.963455 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 452888307 # Number of tag accesses
system.l2c.tags.data_accesses 452888307 # Number of data accesses
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.l2c.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.ReadReq_hits::cpu0.dtb.walker 548032 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 184031 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 541554 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 183989 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1457606 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 8249196 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 8249196 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 16473957 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 16473957 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 5214 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 5107 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 10321 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 811378 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 793383 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1604761 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 8214123 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 8170809 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 16384932 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3524231 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3539730 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 7063961 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 360855 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 358692 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 719547 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 548032 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 184031 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 8214123 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4335609 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 541554 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 183989 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 8170809 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4333113 # number of demand (read+write) hits
system.l2c.demand_hits::total 26511260 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 548032 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 184031 # number of overall hits
system.l2c.overall_hits::cpu0.inst 8214123 # number of overall hits
system.l2c.overall_hits::cpu0.data 4335609 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 541554 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 183989 # number of overall hits
system.l2c.overall_hits::cpu1.inst 8170809 # number of overall hits
system.l2c.overall_hits::cpu1.data 4333113 # number of overall hits
system.l2c.overall_hits::total 26511260 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2785 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2505 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2718 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2422 # number of ReadReq misses
system.l2c.ReadReq_misses::total 10430 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 18558 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 18477 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 37035 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 287141 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 288802 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 575943 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 44885 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 48310 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 93195 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 152964 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 162774 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 315738 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 285264 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 229841 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 515105 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2785 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2505 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 44885 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 440105 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2718 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2422 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 48310 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 451576 # number of demand (read+write) misses
system.l2c.demand_misses::total 995306 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2785 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2505 # number of overall misses
system.l2c.overall_misses::cpu0.inst 44885 # number of overall misses
system.l2c.overall_misses::cpu0.data 440105 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2718 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2422 # number of overall misses
system.l2c.overall_misses::cpu1.inst 48310 # number of overall misses
system.l2c.overall_misses::cpu1.data 451576 # number of overall misses
system.l2c.overall_misses::total 995306 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 248796500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 221765500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 241188500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 214650500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 926401000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 270107500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 268836500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 538944000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 164000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 29383889500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 29652599000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 59036488500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 3875850500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4147732000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 8023582500 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 13881270000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15087981500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 28969251500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 2198500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 1480500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 3679000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 248796500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 221765500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 3875850500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 43265159500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 241188500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 214650500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4147732000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 44740580500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 96955723500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 248796500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 221765500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 3875850500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 43265159500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 241188500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 214650500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4147732000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 44740580500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 96955723500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 550817 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 186536 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 544272 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 186411 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1468036 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 8249196 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 8249196 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 16473957 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 16473957 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 23772 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 23584 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 47356 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 7 # number of SCUpgradeReq accesses(hits+misses)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1098519 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 1082185 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2180704 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 8259008 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 8219119 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 16478127 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 3677195 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 3702504 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 7379699 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 646119 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 588533 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1234652 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 550817 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 186536 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 8259008 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4775714 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 544272 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 186411 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 8219119 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4784689 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 27506566 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 550817 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 186536 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 8259008 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4775714 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 544272 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 186411 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 8219119 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4784689 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 27506566 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005056 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013429 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004994 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.012993 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.007105 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.780666 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783455 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.782055 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.285714 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.153846 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.261389 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.266869 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.264109 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005435 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005878 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005656 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.041598 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.043963 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.042785 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.441504 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.390532 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.417207 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005056 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.013429 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.005435 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.092155 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004994 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.012993 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005878 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.094379 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.036184 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005056 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.013429 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.005435 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.092155 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004994 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.012993 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005878 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.094379 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.036184 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89334.470377 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88529.141717 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88737.490802 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88625.309661 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 88820.805369 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14554.774221 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 14549.791633 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 14552.288376 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 82000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 102332.615335 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102674.493251 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 102504.047276 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 86350.685084 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85856.592838 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 86094.559794 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90748.607515 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92692.822564 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 91750.918483 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 7.706896 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 6.441409 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 7.142233 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89334.470377 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88529.141717 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 86350.685084 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 98306.448461 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88737.490802 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88625.309661 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 85856.592838 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 99076.524217 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 97412.980028 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89334.470377 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88529.141717 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 86350.685084 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 98306.448461 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88737.490802 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88625.309661 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 85856.592838 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 99076.524217 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 97412.980028 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.writebacks::writebacks 1200483 # number of writebacks
system.l2c.writebacks::total 1200483 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 27 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 27 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
stats: Update stats to reflect forwarding of InvalidateReq
2016-02-24 10:16:59 +01:00
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 14 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 7 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker 27 # number of demand (read+write) MSHR hits
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.demand_mshr_hits::cpu0.data 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker 27 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 7 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker 27 # number of overall MSHR hits
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.overall_mshr_hits::cpu0.data 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker 27 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 7 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 77 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2785 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2478 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2717 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2395 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 10375 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 18558 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 18477 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 37035 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 287141 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 288802 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 575943 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 44884 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 48310 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 93194 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 152950 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 162767 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 315717 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 285264 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 229841 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 515105 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2785 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2478 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 44884 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 440091 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2717 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2395 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 48310 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 451569 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 995229 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2785 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2478 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 44884 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 440091 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2717 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2395 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 48310 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 451569 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 995229 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12438 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17867 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8200 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15813 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 54318 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18974 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14723 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12438 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 36841 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8200 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30536 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 88015 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 220944005 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 194989500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 213933501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 188651501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 818518507 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 352676500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 351580500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 704257000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 144000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 26512463532 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 26764568023 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 53277031555 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 3426968033 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 3664618527 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 7091586560 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 12350765593 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13459506075 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 25810271668 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 5940630751 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 4808089000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 10748719751 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 220944005 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 194989500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 3426968033 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 38863229125 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 213933501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 188651501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3664618527 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 40224074098 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 86997408290 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 220944005 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 194989500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 3426968033 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 38863229125 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 213933501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 188651501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3664618527 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 40224074098 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 86997408290 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 781472499 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3170031500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 514421000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2673046500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 7138971499 # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 781472499 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3170031500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 514421000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2673046500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 7138971499 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.007067 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.780666 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783455 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.782055 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.285714 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.261389 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.266869 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.264109 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005656 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041594 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.043961 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042782 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.441504 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.390532 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.417207 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.036182 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005056 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013284 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005435 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.092152 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004992 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012848 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005878 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.094378 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.036182 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 78893.350072 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19004.014441 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19028.007793 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19015.984879 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92332.559725 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92674.455243 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 92504.000491 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76094.883362 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80750.347127 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82691.860604 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81751.288869 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20825.027872 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20919.196314 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20867.046041 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79333.574506 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78688.256659 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76351.662797 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88307.257192 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78738.866765 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78768.893946 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75856.313952 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89076.252130 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 87414.462692 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177423.826048 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169041.073800 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.203929 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86046.293532 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87537.545848 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 81110.850412 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3192252 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 1599225 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 2999 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.membus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::ReadReq 54318 # Transaction distribution
system.membus.trans_dist::ReadResp 482453 # Transaction distribution
system.membus.trans_dist::WriteReq 33697 # Transaction distribution
system.membus.trans_dist::WriteResp 33697 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1307113 # Transaction distribution
system.membus.trans_dist::CleanEvict 222137 # Transaction distribution
system.membus.trans_dist::UpgradeReq 37798 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
stats: Update stats to reflect changes to cache and crossbar
2016-02-10 10:08:27 +01:00
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.trans_dist::ReadExReq 575301 # Transaction distribution
system.membus.trans_dist::ReadExResp 575301 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 428135 # Transaction distribution
system.membus.trans_dist::InvalidateReq 621651 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4001476 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4131122 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237676 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237676 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4368798 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 141781676 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 141953450 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7253312 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 149206762 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2813 # Total snoops (count)
system.membus.snoop_fanout::samples 1750905 # Request fanout histogram
system.membus.snoop_fanout::mean 0.020034 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.140117 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::0 1715827 98.00% 98.00% # Request fanout histogram
system.membus.snoop_fanout::1 35078 2.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.snoop_fanout::total 1750905 # Request fanout histogram
system.membus.reqLayer0.occupancy 114103000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.reqLayer2.occupancy 5413500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.reqLayer5.occupancy 8735804910 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.respLayer2.occupancy 5454823379 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.membus.respLayer3.occupancy 44601796 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to reflect cache changes Removed unused stats, now counting WriteLineReq, and changed how uncacheable writes are handled while responses are outstanding.
2016-04-21 10:48:24 +02:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: Update to reflect changes to RealView platform code
2015-12-04 01:19:05 +01:00
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_filter.tot_requests 55407066 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 28133350 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 5182 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 1867 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 1867 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee
2016-06-06 18:16:44 +02:00
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317219225000 # Cumulative time (in ticks) in various power states
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.trans_dist::ReadReq 2058891 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25917963 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 9449679 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 16477862 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2759760 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 47359 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 47372 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2180704 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2180704 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 16478635 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 7382055 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1266688 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1234652 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49475900 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32614875 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 885296 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2587313 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 85563384 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2110504128 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140051882 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2983576 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8760712 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3262300298 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 1987088 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 30865453 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.026594 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.160894 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::0 30044617 97.34% 97.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 820836 2.66% 100.00% # Request fanout histogram
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect snoop-filter changes
2015-09-25 13:27:03 +02:00
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
stats: Match current behaviour Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-09 18:13:40 +02:00
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoop_fanout::total 30865453 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 53089488175 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.snoopLayer0.occupancy 1406902 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer0.occupancy 24765766555 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer1.occupancy 15040405076 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer2.occupancy 512773114 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.toL2Bus.respLayer3.occupancy 1495395971 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: update for snoop filter tweak --HG-- extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
2016-05-31 12:07:18 +02:00
system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink