gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

2804 lines
329 KiB
Text
Raw Normal View History

---------- Begin Simulation Statistics ----------
sim_seconds 51.761757 # Number of seconds simulated
sim_ticks 51761756862000 # Number of ticks simulated
final_tick 51761756862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 265912 # Simulator instruction rate (inst/s)
host_op_rate 283734 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5899295346 # Simulator tick rate (ticks/s)
host_mem_usage 696216 # Number of bytes of host memory used
host_seconds 8774.23 # Real time elapsed on the host
sim_insts 2333170820 # Number of instructions simulated
sim_ops 2489548001 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 151872 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3595840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 25977120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 153216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 139456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3729408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 26080296 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 414272 # Number of bytes read from this memory
system.physmem.bytes_read::total 60373192 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3595840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3729408 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7325248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 78844864 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory
system.physmem.bytes_written::total 78865444 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2373 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 56185 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 405901 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2394 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2179 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 58272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 407509 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6473 # Number of read requests responded to by this memory
system.physmem.num_reads::total 943344 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1231951 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1234524 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 2934 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2545 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 69469 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 501859 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2960 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2694 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 72049 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 503853 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 8003 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1166367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 69469 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 72049 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 141519 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1523226 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 398 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1523624 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1523226 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 2934 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 69469 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 501859 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 72049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 504250 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 8003 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2689991 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 943344 # Number of read requests accepted
system.physmem.writeReqs 1234524 # Number of write requests accepted
system.physmem.readBursts 943344 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1234524 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 60330432 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 43584 # Total number of bytes read from write queue
system.physmem.bytesWritten 78865536 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 60373192 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 78865444 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 681 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 54550 # Per bank write bursts
system.physmem.perBankRdBursts::1 62293 # Per bank write bursts
system.physmem.perBankRdBursts::2 54512 # Per bank write bursts
system.physmem.perBankRdBursts::3 54260 # Per bank write bursts
system.physmem.perBankRdBursts::4 56553 # Per bank write bursts
system.physmem.perBankRdBursts::5 67360 # Per bank write bursts
system.physmem.perBankRdBursts::6 57276 # Per bank write bursts
system.physmem.perBankRdBursts::7 56002 # Per bank write bursts
system.physmem.perBankRdBursts::8 51757 # Per bank write bursts
system.physmem.perBankRdBursts::9 79766 # Per bank write bursts
system.physmem.perBankRdBursts::10 59095 # Per bank write bursts
system.physmem.perBankRdBursts::11 64327 # Per bank write bursts
system.physmem.perBankRdBursts::12 57398 # Per bank write bursts
system.physmem.perBankRdBursts::13 60635 # Per bank write bursts
system.physmem.perBankRdBursts::14 53657 # Per bank write bursts
system.physmem.perBankRdBursts::15 53222 # Per bank write bursts
system.physmem.perBankWrBursts::0 73571 # Per bank write bursts
system.physmem.perBankWrBursts::1 79159 # Per bank write bursts
system.physmem.perBankWrBursts::2 74534 # Per bank write bursts
system.physmem.perBankWrBursts::3 76045 # Per bank write bursts
system.physmem.perBankWrBursts::4 77226 # Per bank write bursts
system.physmem.perBankWrBursts::5 85193 # Per bank write bursts
system.physmem.perBankWrBursts::6 75384 # Per bank write bursts
system.physmem.perBankWrBursts::7 76786 # Per bank write bursts
system.physmem.perBankWrBursts::8 72797 # Per bank write bursts
system.physmem.perBankWrBursts::9 79168 # Per bank write bursts
system.physmem.perBankWrBursts::10 77101 # Per bank write bursts
system.physmem.perBankWrBursts::11 81604 # Per bank write bursts
system.physmem.perBankWrBursts::12 76385 # Per bank write bursts
system.physmem.perBankWrBursts::13 80183 # Per bank write bursts
system.physmem.perBankWrBursts::14 73603 # Per bank write bursts
system.physmem.perBankWrBursts::15 73535 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 35 # Number of times write queue was full causing retry
system.physmem.totGap 51761755618000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 943329 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1231951 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 533668 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 268938 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 92505 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 42053 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 700 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 557 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 1175 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 721 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 322 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 352 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 193 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 104 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 843 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 794 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 776 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 766 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 764 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 771 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 763 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 761 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 760 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 756 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 759 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 752 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 751 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 28091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 34078 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 47379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 52985 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 65862 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 69793 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 71135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 71701 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 73285 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 82317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 75479 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 88731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 75996 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 76486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 81843 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 71355 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 70124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 67349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 3609 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 1693 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 1279 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1096 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 877 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 731 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 652 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 637 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 403 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 395 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 278 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 166 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 139 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 547235 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 254.361625 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 151.756737 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 294.209115 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 240904 44.02% 44.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 136237 24.90% 68.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 52010 9.50% 78.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 25504 4.66% 83.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 19543 3.57% 86.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 10827 1.98% 88.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 10251 1.87% 90.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6912 1.26% 91.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 45047 8.23% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 547235 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 63900 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 14.751831 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 54.006816 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 63893 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4608-5119 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7680-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 63900 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 63900 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 19.284413 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.392697 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 8.437503 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-7 96 0.15% 0.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-15 74 0.12% 0.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 54483 85.26% 85.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 6734 10.54% 96.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 692 1.08% 97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 454 0.71% 97.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 539 0.84% 98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 107 0.17% 98.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 351 0.55% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 150 0.23% 99.66% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 153 0.24% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 9 0.01% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 2 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 6 0.01% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 5 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 2 0.00% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 11 0.02% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 5 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 15 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 5 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 63900 # Writes before turning the bus around for reads
system.physmem.totQLat 25011662426 # Total ticks spent queuing
system.physmem.totMemAccLat 42686593676 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 4713315000 # Total ticks spent in databus transfers
system.physmem.avgQLat 26532.98 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 45282.98 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
system.physmem.avgWrQLen 9.19 # Average write queue length when enqueuing
system.physmem.readRowHits 724331 # Number of row buffer hits during reads
system.physmem.writeRowHits 903369 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 73.31 # Row buffer hit rate for writes
system.physmem.avgGap 23767168.45 # Average gap between requests
system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2099502720 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1145562000 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 3609886800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4003979040 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1247139310140 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29963069496750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34601893756410 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.483818 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49846129273502 # Time in different power states
system.physmem_0.memoryStateTime::REF 1728438660000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 187184326498 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 2037593880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1111782375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 3742837800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 3981156480 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1247115577050 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29963090307000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34601905273545 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.484040 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49846127379717 # Time in different power states
system.physmem_1.memoryStateTime::REF 1728438660000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 187190202783 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 1024 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2148 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 1088 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1024 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2112 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 17 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 41 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 41 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 441769882 # Number of BP lookups
system.cpu0.branchPred.condPredicted 346318853 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5806285 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 315736094 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 267112052 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 84.599784 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17170317 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 190049 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 5021410 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2619937 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 2401473 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 415468 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 892710 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 892710 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17744 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89453 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 550305 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 342405 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2673.589755 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 15902.851063 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 339616 99.19% 99.19% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1452 0.42% 99.61% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 967 0.28% 99.89% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 143 0.04% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 137 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.00% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 33 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 342405 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 416567 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 23523.175143 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18877.823931 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 19885.199602 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 406963 97.69% 97.69% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7350 1.76% 99.46% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1585 0.38% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 137 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 275 0.07% 99.94% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 156 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 65 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 27 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 416567 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 844595026420 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.078472 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.490568 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 843548733920 99.88% 99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7 573107500 0.07% 99.94% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11 199238500 0.02% 99.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15 117034000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19 49115000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23 33953000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27 28746000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31 36613000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35 8069500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39 361500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43 23000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::44-47 9000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::48-51 14500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::56-59 3000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::60-63 2000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 844595026420 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 89453 83.45% 83.45% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 17744 16.55% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 107197 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 892710 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 892710 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107197 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 999907 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 311659377 # DTB read hits
system.cpu0.dtb.read_misses 618746 # DTB read misses
system.cpu0.dtb.write_hits 81669046 # DTB write hits
system.cpu0.dtb.write_misses 273964 # DTB write misses
system.cpu0.dtb.flush_tlb 1566 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 56873 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9024 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 58972 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 312278123 # DTB read accesses
system.cpu0.dtb.write_accesses 81943010 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 393328423 # DTB hits
system.cpu0.dtb.misses 892710 # DTB misses
system.cpu0.dtb.accesses 394221133 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 100670 # Table walker walks requested
system.cpu0.itb.walker.walksLong 100670 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3435 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68577 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 13827 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 86843 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1681.770551 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 11901.774457 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 85828 98.83% 98.83% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 525 0.60% 99.44% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 54 0.06% 99.50% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 177 0.20% 99.70% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 176 0.20% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 42 0.05% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 86843 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 85839 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 29252.396929 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 24357.820404 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 23461.302389 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 83908 97.75% 97.75% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 516 0.60% 98.35% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 1196 1.39% 99.74% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.09% 99.84% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 102 0.12% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 85839 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 638425660712 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.889219 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.314244 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 70792067924 11.09% 11.09% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 567575291288 88.90% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 51231500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 6018000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 857500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 106500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 88000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 638425660712 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 68577 95.23% 95.23% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 3435 4.77% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 72012 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 100670 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 100670 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72012 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72012 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 172682 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 300349481 # ITB inst hits
system.cpu0.itb.inst_misses 100670 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 1566 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 41410 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 188775 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 300450151 # ITB inst accesses
system.cpu0.itb.hits 300349481 # DTB hits
system.cpu0.itb.misses 100670 # DTB misses
system.cpu0.itb.accesses 300450151 # DTB accesses
system.cpu0.numCycles 1153591288 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 452660277 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 1310968350 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 441769882 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 286902306 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 657569557 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 13257965 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2520501 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 22487 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 4210 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 4808989 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 163286 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 3813 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 300145403 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3627233 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 38474 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 1124381714 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.254786 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.113096 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 722021873 64.22% 64.22% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 121051325 10.77% 74.98% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 18164334 1.62% 76.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13282328 1.18% 77.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 182681747 16.25% 94.03% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 8985206 0.80% 94.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9665427 0.86% 95.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8249650 0.73% 96.42% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 40279824 3.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 1124381714 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.382952 # Number of branch fetches per cycle
system.cpu0.fetch.rate 1.136424 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 405971329 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 336686919 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 362849881 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 13601656 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5263930 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 71142613 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1385162 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 1364494980 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4266008 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5263930 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 413565658 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 26498073 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 263444659 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 368730385 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 46870910 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 1349255091 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 116974 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 2261616 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1896807 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 27181012 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 3751 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 1320809578 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 1942299251 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 1409770765 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 775838 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 1225247186 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 95562392 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15257380 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13270852 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 75639942 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 307378259 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85793639 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13768177 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14589388 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 1316697465 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15319190 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 1317684473 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 854895 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 81379212 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 50931090 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 359979 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 1124381714 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 1.171919 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.498403 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 479017696 42.60% 42.60% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 355860200 31.65% 74.25% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 94607581 8.41% 82.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 82377744 7.33% 89.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 74414845 6.62% 96.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 16123062 1.43% 98.05% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 11093083 0.99% 99.03% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6457333 0.57% 99.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4430170 0.39% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 1124381714 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 3027806 25.46% 25.46% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 21993 0.18% 25.64% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 1913 0.02% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.66% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4879295 41.03% 66.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3961438 33.31% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 919558912 69.79% 69.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1403204 0.11% 69.89% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 63552 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 184 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 53817 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.90% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 313882941 23.82% 93.72% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 82721833 6.28% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 1317684473 # Type of FU issued
system.cpu0.iq.rate 1.142246 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11892445 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.009025 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 3771522724 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 1413606609 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 1295090800 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 975276 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 499965 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 431562 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 1329056054 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 520834 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4724292 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 16714956 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 20317 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 722500 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 8583352 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 3995442 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 8184292 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5263930 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 15793558 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 8769722 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 1332158998 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1730842 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 307378259 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85793639 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 12984237 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 229560 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 8457997 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 722500 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2474503 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2706494 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5180997 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 1310764150 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 311649701 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 6040737 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 142343 # number of nop insts executed
system.cpu0.iew.exec_refs 393318158 # number of memory reference insts executed
system.cpu0.iew.exec_branches 417986859 # Number of branches executed
system.cpu0.iew.exec_stores 81668457 # Number of stores executed
system.cpu0.iew.exec_rate 1.136247 # Inst execution rate
system.cpu0.iew.wb_sent 1296930060 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 1295522362 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 592614892 # num instructions producing a value
system.cpu0.iew.wb_consumers 1110609614 # num instructions consuming a value
system.cpu0.iew.wb_rate 1.123034 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.533594 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 81425087 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 14959211 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4440844 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 1110541032 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 1.126151 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.560922 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 504262189 45.41% 45.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 302033951 27.20% 72.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 135703334 12.22% 84.82% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 118428443 10.66% 95.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10778674 0.97% 96.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6605089 0.59% 97.05% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6100457 0.55% 97.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3862548 0.35% 97.95% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 22766347 2.05% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 1110541032 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 1171621966 # Number of instructions committed
system.cpu0.commit.committedOps 1250637443 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 367873590 # Number of memory references committed
system.cpu0.commit.loads 290663303 # Number of loads committed
system.cpu0.commit.membars 3675290 # Number of memory barriers committed
system.cpu0.commit.branches 409547032 # Number of branches committed
system.cpu0.commit.fp_insts 413703 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 1052721176 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13293497 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 881582024 70.49% 70.49% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1088872 0.09% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 47670 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.58% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 45287 0.00% 70.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.59% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.59% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 290663303 23.24% 93.83% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 77210287 6.17% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 1250637443 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22766347 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 2415886012 # The number of ROB reads
system.cpu0.rob.rob_writes 2677991243 # The number of ROB writes
system.cpu0.timesIdled 4174406 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 29209574 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 53218608185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 1171621966 # Number of Instructions Simulated
system.cpu0.committedOps 1250637443 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 0.984610 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.984610 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.015630 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.015630 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 1363459198 # number of integer regfile reads
system.cpu0.int_regfile_writes 822633893 # number of integer regfile writes
system.cpu0.fp_regfile_reads 827834 # number of floating regfile reads
system.cpu0.fp_regfile_writes 497604 # number of floating regfile writes
system.cpu0.cc_regfile_reads 434759871 # number of cc regfile reads
system.cpu0.cc_regfile_writes 435903549 # number of cc regfile writes
system.cpu0.misc_regfile_reads 2497252569 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15072789 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 10543122 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.973214 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 714246594 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10543634 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 67.741975 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 297.299431 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 214.673783 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.580663 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.419285 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 2981506473 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 2981506473 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 286698087 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 284974964 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 571673051 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67938381 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 66316619 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 134255000 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207203 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 195617 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 402820 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177871 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 146629 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 324500 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1740566 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1760771 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3501337 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2018486 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2021987 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4040473 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 354636468 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 351291583 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 705928051 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 354843671 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 351487200 # number of overall hits
system.cpu0.dcache.overall_hits::total 706330871 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6383220 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6242093 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12625313 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6497631 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6239975 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 12737606 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 683741 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 608697 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1292438 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 573671 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 664585 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1238256 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 331614 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 318292 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 649906 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 12880851 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 12482068 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 25362919 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 13564592 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 13090765 # number of overall misses
system.cpu0.dcache.overall_misses::total 26655357 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110753552000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111947542000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 222701094000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 287335391122 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 284659105303 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 571994496425 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 22737846434 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 30047699861 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 52785546295 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4579227500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4402893000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 8982120500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 138500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 96000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 234500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 398088943122 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 396606647303 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 794695590425 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 398088943122 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 396606647303 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 794695590425 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 293081307 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 291217057 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 584298364 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74436012 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 72556594 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 146992606 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 890944 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 804314 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1695258 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 751542 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 811214 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1562756 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072180 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2079063 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4151243 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2018491 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2021989 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4040480 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 367517319 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 363773651 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 731290970 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 368408263 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 364577965 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 732986228 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021780 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.021435 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.021608 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.087291 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086001 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.086655 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767434 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.756790 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762384 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763325 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.819247 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792354 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.160031 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153094 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.156557 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000002 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035048 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.034313 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.034682 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036819 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.035907 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.036365 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.733956 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17934.295756 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 17639.253300 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44221.561846 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45618.629130 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44905.965566 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 39635.690899 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45212.726530 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42628.944495 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13808.908852 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13832.873588 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13820.645601 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27700 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 48000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 33500 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30905.484670 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31774.113657 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 31332.970406 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29347.653296 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30296.674587 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 29813.729016 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 70477710 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 116225 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3519959 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1128 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20.022310 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 103.036348 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 8078087 # number of writebacks
system.cpu0.dcache.writebacks::total 8078087 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3526105 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3409163 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 6935268 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405186 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5181209 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10586395 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3376 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3483 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 6859 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204163 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 196814 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 400977 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8931291 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8590372 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 17521663 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8931291 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8590372 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 17521663 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2857115 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2832930 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5690045 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1092445 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1058766 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2151211 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668680 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 599708 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1268388 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 570295 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 661102 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1231397 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 127451 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 121478 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 248929 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3949560 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 3891696 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 7841256 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4618240 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4491404 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 9109644 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16758 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16944 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15500 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18208 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32258 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35152 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48892925500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49984550000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98877475500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 50989234756 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 50617210449 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101606445205 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13305949000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11256900000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24562849000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 21948256934 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 29156940361 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51105197295 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1850360000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1748512000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3598872000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 133500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 94000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99882160256 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100601760449 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 200483920705 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 113188109256 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111858660449 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 225046769705 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3097490500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3134623000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232113500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2979818500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3228691491 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6208509991 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6077309000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6363314491 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12440623491 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.009749 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.009728 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009738 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014676 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014592 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014635 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750530 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745614 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.748198 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758833 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.814954 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787965 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061506 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058429 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059965 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.010747 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.010698 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.010722 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.012536 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.012319 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.012428 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17112.690774 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17644.117574 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17377.274784 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46674.418168 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47807.740756 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47232.207908 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19898.829036 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18770.635042 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19365.406327 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38485.795832 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44103.542813 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41501.804288 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14518.206997 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14393.651525 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14457.423603 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26700 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32500 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25289.439901 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25850.364584 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25567.832590 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24508.927482 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24905.054288 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24704.233196 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184836.525838 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184998.996695 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.209602 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 192246.354839 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177322.687335 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184185.059659 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188396.955794 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 181022.829170 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184551.602003 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 16336648 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.932732 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 580722956 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 16337160 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.546139 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 19421278500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.802291 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.130441 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.546489 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.453380 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 614644224 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 614644224 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 291297674 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 289425282 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 580722956 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 291297674 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 289425282 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 580722956 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 291297674 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 289425282 # number of overall hits
system.cpu0.icache.overall_hits::total 580722956 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8834570 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8749295 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17583865 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8834570 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8749295 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17583865 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8834570 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8749295 # number of overall misses
system.cpu0.icache.overall_misses::total 17583865 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 118633487353 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118783272350 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 237416759703 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 118633487353 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 118783272350 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 237416759703 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 118633487353 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 118783272350 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 237416759703 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 300132244 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 298174577 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 598306821 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 300132244 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 298174577 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 598306821 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 300132244 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 298174577 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 598306821 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029436 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.029343 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.029389 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029436 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.029343 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.029389 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029436 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.029343 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.029389 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13428.326150 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.324990 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13501.966701 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13428.326150 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.324990 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13501.966701 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13428.326150 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.324990 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13501.966701 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 128000 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 8615 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.857806 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.writebacks::writebacks 16336648 # number of writebacks
system.cpu0.icache.writebacks::total 16336648 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 624990 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 621471 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1246461 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 624990 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 621471 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1246461 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 624990 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 621471 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1246461 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8209580 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8127824 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 16337404 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 8209580 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8127824 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 16337404 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8209580 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8127824 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16337404 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104820770896 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104795182400 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 209615953296 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104820770896 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104795182400 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 209615953296 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104820770896 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104795182400 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 209615953296 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027306 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.027306 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.027306 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12830.432136 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12830.432136 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12830.432136 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 439037695 # Number of BP lookups
system.cpu1.branchPred.condPredicted 344630545 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5789779 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 303336917 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 265424368 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 87.501505 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 16925953 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 188094 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 4924647 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2613751 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 2310896 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 404882 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 918796 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 918796 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17982 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92529 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 574433 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 344363 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2764.463662 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 16303.117040 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 341501 99.17% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1458 0.42% 99.59% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 968 0.28% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 172 0.05% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 169 0.05% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 30 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 344363 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 435626 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 23794.009081 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 19218.933550 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 19692.719928 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 425832 97.75% 97.75% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7550 1.73% 99.48% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1569 0.36% 99.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 287 0.07% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 141 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 90 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 435626 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 784789358776 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.079913 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.520502 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 783688095276 99.86% 99.86% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 587470000 0.07% 99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 214780500 0.03% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 128162000 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 51938500 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 36138500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 30357500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 44039000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 7811000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39 500500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47 17000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51 22000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 784789358776 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 92530 83.73% 83.73% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 17982 16.27% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 110512 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918796 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918796 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110512 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110512 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 1029308 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 308677787 # DTB read hits
system.cpu1.dtb.read_misses 638033 # DTB read misses
system.cpu1.dtb.write_hits 79810213 # DTB write hits
system.cpu1.dtb.write_misses 280763 # DTB write misses
system.cpu1.dtb.flush_tlb 1558 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 54702 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8626 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 52744 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 309315820 # DTB read accesses
system.cpu1.dtb.write_accesses 80090976 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 388488000 # DTB hits
system.cpu1.dtb.misses 918796 # DTB misses
system.cpu1.dtb.accesses 389406796 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 101960 # Table walker walks requested
system.cpu1.itb.walker.walksLong 101960 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3266 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68775 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 14205 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 87755 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1682.627770 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 11960.911223 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535 87281 99.46% 99.46% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071 225 0.26% 99.72% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607 206 0.23% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143 30 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 87755 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 86246 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 29588.885282 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24514.620158 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 24839.457997 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535 84146 97.57% 97.57% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071 550 0.64% 98.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607 1295 1.50% 99.70% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679 109 0.13% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 86246 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 630168052620 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.901316 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.298682 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 62259907956 9.88% 9.88% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 567845557664 90.11% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 54142000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 7434500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 754500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 241500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6 14500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 630168052620 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 68775 95.47% 95.47% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 3266 4.53% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 72041 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101960 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101960 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72041 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72041 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 174001 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 298391001 # ITB inst hits
system.cpu1.itb.inst_misses 101960 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 1558 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 40396 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 187550 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 298492961 # ITB inst accesses
system.cpu1.itb.hits 298391001 # DTB hits
system.cpu1.itb.misses 101960 # DTB misses
system.cpu1.itb.accesses 298492961 # DTB accesses
system.cpu1.numCycles 1146540967 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 449143632 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 1300356824 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 439037695 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 284964072 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 654346336 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13178215 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2532163 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 23392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 4389 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 4759392 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 175720 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 3551 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 298182140 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3594914 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 39494 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 1117577293 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.251423 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.109409 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 718189985 64.26% 64.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 120476918 10.78% 75.04% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 17851977 1.60% 76.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13155756 1.18% 77.82% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 181640077 16.25% 94.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 8775776 0.79% 94.86% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9591150 0.86% 95.71% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8236988 0.74% 96.45% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 39658666 3.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 1117577293 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.382924 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.134156 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 403258788 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 335088582 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 360694363 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13294705 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5232856 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 70476298 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1375606 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 1352424044 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4253100 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5232856 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 410740551 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 28469825 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 258278982 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 366370165 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 48476952 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 1337170119 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 127982 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 1950398 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1918017 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 29294510 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 3829 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 1310108256 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 1925124078 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 1396779335 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 887250 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 1214507358 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 95600893 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 14870121 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 12952577 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 74043380 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 305276022 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 83874418 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13450040 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14282158 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 1304947133 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 14993052 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 1304763464 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 862160 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 81029622 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 50869342 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 350473 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 1117577293 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.167493 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.494205 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 477542007 42.73% 42.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 353173077 31.60% 74.33% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 93863937 8.40% 82.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 81886889 7.33% 90.06% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 73787788 6.60% 96.66% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 15804378 1.41% 98.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 10888709 0.97% 99.05% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6347514 0.57% 99.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4282994 0.38% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 1117577293 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 2956708 25.80% 25.80% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 26444 0.23% 26.03% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 3429 0.03% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4659115 40.65% 66.71% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3815684 33.29% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 86 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 911406413 69.85% 69.85% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1450716 0.11% 69.96% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 68809 0.01% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 242 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 74568 0.01% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.97% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 310913309 23.83% 93.80% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 80849259 6.20% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 1304763464 # Type of FU issued
system.cpu1.iq.rate 1.138000 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 11461380 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.008784 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 3738310574 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 1401077508 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 1283063938 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1117187 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 574367 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 497584 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 1315629411 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 595347 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4624780 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 16729306 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 20042 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 692952 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 8476645 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 3812143 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 7452647 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 5232856 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 16688704 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 9539057 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 1320087759 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1712091 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 305276022 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 83874418 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12664409 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 233480 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 9218245 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 692952 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2475150 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2684103 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 5159253 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 1297880089 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 308665532 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 5977092 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 147574 # number of nop insts executed
system.cpu1.iew.exec_refs 388478968 # number of memory reference insts executed
system.cpu1.iew.exec_branches 415337436 # Number of branches executed
system.cpu1.iew.exec_stores 79813436 # Number of stores executed
system.cpu1.iew.exec_rate 1.131996 # Inst execution rate
system.cpu1.iew.wb_sent 1284971111 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 1283561522 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 586897530 # num instructions producing a value
system.cpu1.iew.wb_consumers 1100487939 # num instructions consuming a value
system.cpu1.iew.wb_rate 1.119508 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.533307 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 81091096 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14642579 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4433138 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 1103802352 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.122403 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.555476 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 502258397 45.50% 45.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 299485709 27.13% 72.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 134986499 12.23% 84.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 117786431 10.67% 95.53% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 10837119 0.98% 96.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6401807 0.58% 97.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5917729 0.54% 97.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3800615 0.34% 97.98% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 22328046 2.02% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 1103802352 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 1161548854 # Number of instructions committed
system.cpu1.commit.committedOps 1238910558 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 363944488 # Number of memory references committed
system.cpu1.commit.loads 288546715 # Number of loads committed
system.cpu1.commit.membars 3671917 # Number of memory barriers committed
system.cpu1.commit.branches 406943707 # Number of branches committed
system.cpu1.commit.fp_insts 477645 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 1042234207 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13083843 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 873720787 70.52% 70.52% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1128470 0.09% 70.61% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 51728 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 65043 0.01% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 288546715 23.29% 93.91% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 75397773 6.09% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 1238910558 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22328046 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 2397538789 # The number of ROB reads
system.cpu1.rob.rob_writes 2653800851 # The number of ROB writes
system.cpu1.timesIdled 4140984 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 28963674 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 48004396286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 1161548854 # Number of Instructions Simulated
system.cpu1.committedOps 1238910558 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 0.987079 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.987079 # CPI: Total CPI of All Threads
system.cpu1.ipc 1.013090 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 1.013090 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 1349751752 # number of integer regfile reads
system.cpu1.int_regfile_writes 814694732 # number of integer regfile writes
system.cpu1.fp_regfile_reads 925132 # number of floating regfile reads
system.cpu1.fp_regfile_writes 580436 # number of floating regfile writes
system.cpu1.cc_regfile_reads 432060294 # number of cc regfile reads
system.cpu1.cc_regfile_writes 433189790 # number of cc regfile writes
system.cpu1.misc_regfile_reads 2477616684 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14758914 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 40289 # Transaction distribution
system.iobus.trans_dist::ReadResp 40289 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 47809000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 351500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 25705000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 40136000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 566925706 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 115449 # number of replacements
system.iocache.tags.tagsinuse 10.471056 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 13096638509000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.513940 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.957116 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219621 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.434820 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.654441 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1039569 # Number of tag accesses
system.iocache.tags.data_accesses 1039569 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 8804 # number of demand (read+write) misses
system.iocache.demand_misses::total 8844 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8804 # number of overall misses
system.iocache.overall_misses::total 8844 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1671055077 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1676125077 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 13413972629 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 13413972629 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 1671055077 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1676476077 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 1671055077 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1676476077 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8804 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8841 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 8804 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8844 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 8804 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8844 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 189806.346774 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 189585.462844 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125759.137375 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125759.137375 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 189806.346774 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 189560.840909 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 189806.346774 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 189560.840909 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 34335 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3424 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 10.027745 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8804 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8841 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 8804 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8844 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8804 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8844 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1230855077 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1234075077 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8075705812 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 8075705812 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 1230855077 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1234276077 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 1230855077 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1234276077 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139806.346774 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 139585.462844 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75711.634778 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75711.634778 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 139806.346774 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 139560.840909 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 139806.346774 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 139560.840909 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 1328339 # number of replacements
system.l2c.tags.tagsinuse 65287.407442 # Cycle average of tags in use
system.l2c.tags.total_refs 50375413 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1391222 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 36.209471 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 4319218500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 35575.639274 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.468154 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 240.943849 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3221.018830 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 11891.666425 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 181.118375 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 261.193191 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3949.386858 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 9807.972486 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.542841 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002418 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003677 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.049149 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.181452 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002764 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003985 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.060263 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.149658 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996207 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 365 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62518 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 365 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 534 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2786 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5034 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54062 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.005569 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.953949 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 446176670 # Number of tag accesses
system.l2c.tags.data_accesses 446176670 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 522071 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 180522 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 538718 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 182834 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1424145 # number of ReadReq hits
system.l2c.WritebackDirty_hits::writebacks 8078087 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 8078087 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 16333029 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 16333029 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 5039 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4982 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 10021 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 814588 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 782344 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1596932 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 8166281 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 8076794 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 16243075 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3501095 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3399507 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6900602 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 361869 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 365570 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 727439 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 522071 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 180522 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 8166281 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4315683 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 538718 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 182834 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 8076794 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4181851 # number of demand (read+write) hits
system.l2c.demand_hits::total 26164754 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 522071 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 180522 # number of overall hits
system.l2c.overall_hits::cpu0.inst 8166281 # number of overall hits
system.l2c.overall_hits::cpu0.data 4315683 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 538718 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 182834 # number of overall hits
system.l2c.overall_hits::cpu1.inst 8076794 # number of overall hits
system.l2c.overall_hits::cpu1.data 4181851 # number of overall hits
system.l2c.overall_hits::total 26164754 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2382 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2080 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2398 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2211 # number of ReadReq misses
system.l2c.ReadReq_misses::total 9071 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 18406 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 17899 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 36305 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 260481 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 259931 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 520412 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 43082 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 50777 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 93859 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 146082 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 148220 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 294302 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 208426 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 295532 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 503958 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2382 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2080 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 43082 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 406563 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2398 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2211 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 50777 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 408151 # number of demand (read+write) misses
system.l2c.demand_misses::total 917644 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2382 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2080 # number of overall misses
system.l2c.overall_misses::cpu0.inst 43082 # number of overall misses
system.l2c.overall_misses::cpu0.data 406563 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2398 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2211 # number of overall misses
system.l2c.overall_misses::cpu1.inst 50777 # number of overall misses
system.l2c.overall_misses::cpu1.data 408151 # number of overall misses
system.l2c.overall_misses::total 917644 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 328467000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 287802500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 333096500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 309339500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 1258705500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 720994000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 707940000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 1428934000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 39260568000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 39326078500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 78586646500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 5834073500 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6880458998 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 12714532498 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 20593358000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 20805919500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 41399277500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 4602500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 4134500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 8737000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 328467000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 287802500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 5834073500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 59853926000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 333096500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 309339500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 6880458998 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 60131998000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 133959161998 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 328467000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 287802500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 5834073500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 59853926000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 333096500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 309339500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 6880458998 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 60131998000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 133959161998 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 524453 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 182602 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 541116 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 185045 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1433216 # number of ReadReq accesses(hits+misses)
system.l2c.WritebackDirty_accesses::writebacks 8078087 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 8078087 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 16333029 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 16333029 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 23445 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 22881 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 46326 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1075069 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 1042275 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2117344 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 8209363 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 8127571 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 16336934 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 3647177 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 3547727 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 7194904 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 570295 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 661102 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1231397 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 524453 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 182602 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 8209363 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4722246 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 541116 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 185045 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 8127571 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4590002 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 27082398 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 524453 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 182602 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 8209363 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4722246 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 541116 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 185045 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 8127571 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4590002 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 27082398 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011391 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011948 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785071 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782265 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.783685 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.500000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.242292 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.249388 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.245785 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005248 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006248 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005745 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040053 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.041779 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.040904 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.365471 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.447029 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.409257 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.011391 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.005248 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.086095 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.011948 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.006248 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.088922 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.033883 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.011391 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.005248 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.086095 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.011948 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.006248 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.088922 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.033883 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138366.586538 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 139909.317051 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 138761.492669 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39171.683147 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39551.930275 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 39359.151632 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150723.346424 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 151294.299256 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 151008.521133 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135417.889142 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135503.456250 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 135464.180292 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140971.221643 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140371.876265 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 140669.371938 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 22.082178 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 13.990025 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 17.336762 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138366.586538 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 135417.889142 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 147219.314104 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139909.317051 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 135503.456250 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 147327.822301 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 145981.624680 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138366.586538 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 135417.889142 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 147219.314104 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139909.317051 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 135503.456250 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 147327.822301 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 145981.624680 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 1125321 # number of writebacks
system.l2c.writebacks::total 1125321 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 9 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 22 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 32 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 6 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 16 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.dtb.walker 9 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker 22 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker 32 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 9 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker 22 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker 32 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 90 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2373 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2058 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2394 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2179 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 9004 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 18406 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 17899 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 36305 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 260481 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 259931 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 520412 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 43082 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 50776 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 93858 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 146076 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 148204 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 294280 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 208426 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 295532 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 503958 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2373 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2058 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 43082 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 406557 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2394 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2179 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 50776 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 408135 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 917554 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2373 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2058 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 43082 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 406557 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2394 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2179 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 50776 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 408135 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 917554 # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16758 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16944 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 54348 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15500 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 18208 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32258 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35152 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 88056 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 264543501 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 283810502 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1160435511 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1251234000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1216921000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 2468155000 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 71000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 36655262703 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 36726203379 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 73381466082 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 5403192134 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6372607642 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 11775799776 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19131795349 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 19321739325 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 38453534674 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 14581285500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 20639326500 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 35220612000 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 264543501 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 5403192134 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 55787058052 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 283810502 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 6372607642 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 56047942704 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 124771236043 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 264543501 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 5403192134 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 55787058052 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 283810502 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 6372607642 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 56047942704 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 124771236043 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1472133000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2887938500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 844117498 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2922748500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 8126937498 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2801523500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3017706998 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5819230498 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1472133000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5689462000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 844117498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5940455498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 13946167996 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.006282 # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785071 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782265 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.783685 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.242292 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249388 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.245785 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005745 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040052 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.041774 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040901 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.365471 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.447029 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.409257 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.086094 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.088918 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.033880 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.086094 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.088918 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.033880 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 128879.999000 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67979.680539 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67988.211632 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67983.886517 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140721.444954 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 141292.125137 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 141006.483482 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125463.996420 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130971.517217 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130372.589977 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130669.888113 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69959.052613 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69837.873733 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69887.990666 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137218.294242 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137326.969517 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 135982.444677 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137218.294242 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137326.969517 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 135982.444677 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172331.931018 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172494.599858 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149535.171451 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180743.451613 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165735.226164 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172636.480895 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 176373.674747 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168993.385810 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 158378.395521 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 54348 # Transaction distribution
system.membus.trans_dist::ReadResp 460331 # Transaction distribution
system.membus.trans_dist::WriteReq 33708 # Transaction distribution
system.membus.trans_dist::WriteResp 33708 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1231951 # Transaction distribution
system.membus.trans_dist::CleanEvict 210742 # Transaction distribution
system.membus.trans_dist::UpgradeReq 37070 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
system.membus.trans_dist::ReadExReq 519762 # Transaction distribution
system.membus.trans_dist::ReadExResp 519762 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 405983 # Transaction distribution
system.membus.trans_dist::InvalidateReq 610510 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747708 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 3877418 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237430 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4114848 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 132000044 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 132171886 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7238592 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 139410478 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3037 # Total snoops (count)
system.membus.snoop_fanout::samples 3104114 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 3104114 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 3104114 # Request fanout histogram
system.membus.reqLayer0.occupancy 114095000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 5418502 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 8237516188 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5046734585 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 44568865 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests 54620375 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 27739287 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 4920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 2097 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 2097 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq 2026549 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25559589 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 9310073 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 16336648 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2676872 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 46329 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 46336 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2117344 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2117344 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 16337404 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 7203745 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1338061 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1231397 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49052277 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31858634 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 875155 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2530262 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 84316328 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2092430528 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1113218798 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2941176 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8524552 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 3217115054 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2099522 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 30547038 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.026857 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.161665 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 29726637 97.31% 97.31% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 820401 2.69% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 30547038 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 52365395385 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1392915 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 24553415616 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 14664140678 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 507934109 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1467755168 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 16352 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------