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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt

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arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
---------- Begin Simulation Statistics ----------
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
sim_seconds 51.241896 # Number of seconds simulated
sim_ticks 51241895910000 # Number of ticks simulated
final_tick 51241895910000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
host_inst_rate 95627 # Simulator instruction rate (inst/s)
host_op_rate 112378 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 5423934154 # Simulator tick rate (ticks/s)
host_mem_usage 730628 # Number of bytes of host memory used
host_seconds 9447.37 # Real time elapsed on the host
sim_insts 903425057 # Number of instructions simulated
sim_ops 1061671663 # Number of ops (including micro ops) simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.bytes_read::cpu0.dtb.walker 165376 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 148160 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 3796224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 45159832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 160832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 148224 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3625536 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 44632368 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 406656 # Number of bytes read from this memory
system.physmem.bytes_read::total 98243208 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 3796224 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3625536 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7421760 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 83214784 # Number of bytes written to this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.bytes_written::total 83235364 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 2584 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2315 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 59316 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 705630 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2513 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 2316 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 56649 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 697386 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6354 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1535063 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1300231 # Number of write requests responded to by this memory
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.num_writes::total 1302804 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 2891 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 74084 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 881307 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 2893 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 70753 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 871013 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 7936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1917244 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 74084 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 70753 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 144838 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1623960 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1624362 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1623960 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 2891 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 74084 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 881708 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 2893 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 70753 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 871013 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 7936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3541605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1535063 # Number of read requests accepted
system.physmem.writeReqs 1302804 # Number of write requests accepted
system.physmem.readBursts 1535063 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1302804 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 98199040 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 44992 # Total number of bytes read from write queue
system.physmem.bytesWritten 83234496 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 98243208 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 83235364 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 703 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 144188 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 94050 # Per bank write bursts
system.physmem.perBankRdBursts::1 94624 # Per bank write bursts
system.physmem.perBankRdBursts::2 91446 # Per bank write bursts
system.physmem.perBankRdBursts::3 92243 # Per bank write bursts
system.physmem.perBankRdBursts::4 98717 # Per bank write bursts
system.physmem.perBankRdBursts::5 106707 # Per bank write bursts
system.physmem.perBankRdBursts::6 93934 # Per bank write bursts
system.physmem.perBankRdBursts::7 93123 # Per bank write bursts
system.physmem.perBankRdBursts::8 90055 # Per bank write bursts
system.physmem.perBankRdBursts::9 118648 # Per bank write bursts
system.physmem.perBankRdBursts::10 94680 # Per bank write bursts
system.physmem.perBankRdBursts::11 96202 # Per bank write bursts
system.physmem.perBankRdBursts::12 91550 # Per bank write bursts
system.physmem.perBankRdBursts::13 95334 # Per bank write bursts
system.physmem.perBankRdBursts::14 93205 # Per bank write bursts
system.physmem.perBankRdBursts::15 89842 # Per bank write bursts
system.physmem.perBankWrBursts::0 79067 # Per bank write bursts
system.physmem.perBankWrBursts::1 80858 # Per bank write bursts
system.physmem.perBankWrBursts::2 78439 # Per bank write bursts
system.physmem.perBankWrBursts::3 80901 # Per bank write bursts
system.physmem.perBankWrBursts::4 84568 # Per bank write bursts
system.physmem.perBankWrBursts::5 88799 # Per bank write bursts
system.physmem.perBankWrBursts::6 79324 # Per bank write bursts
system.physmem.perBankWrBursts::7 81423 # Per bank write bursts
system.physmem.perBankWrBursts::8 78366 # Per bank write bursts
system.physmem.perBankWrBursts::9 84879 # Per bank write bursts
system.physmem.perBankWrBursts::10 80434 # Per bank write bursts
system.physmem.perBankWrBursts::11 83122 # Per bank write bursts
system.physmem.perBankWrBursts::12 79318 # Per bank write bursts
system.physmem.perBankWrBursts::13 82355 # Per bank write bursts
system.physmem.perBankWrBursts::14 80105 # Per bank write bursts
system.physmem.perBankWrBursts::15 78581 # Per bank write bursts
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.numWrRetry 26 # Number of times write queue was full causing retry
system.physmem.totGap 51241894805000 # Total gap between requests
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.readPktSize::6 1535048 # Read request sizes (log2)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.writePktSize::6 1300231 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 696212 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 434080 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 231480 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 166858 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 935 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 497 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 499 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 804 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 871 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 222 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 153 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 126 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.rdQLenPdf::19 67 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::0 765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 752 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 744 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 738 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 743 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 734 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::6 736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 737 # What write queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::8 732 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 729 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 730 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 729 # What write queue length does an incoming req see
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrQLenPdf::15 14109 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 16691 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 29697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44633 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 65149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 77035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 77508 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 81035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 83877 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 86632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 85119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 87954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 84437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 96180 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 104378 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 81922 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 85007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 77822 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 547 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 419 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 381 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 371 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 357 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 287 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 255 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 239 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 213 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 252 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 220 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 270 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 151 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 90 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 599076 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 302.854983 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 174.463010 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 332.270126 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 239456 39.97% 39.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 137779 23.00% 62.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 58288 9.73% 72.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 28412 4.74% 77.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 23965 4.00% 81.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 14114 2.36% 83.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 13744 2.29% 86.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 10019 1.67% 87.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 73299 12.24% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 599076 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 75110 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 20.428012 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 233.528819 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 75106 99.99% 99.99% # Reads before turning the bus around for writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::61440-63487 1 0.00% 100.00% # Reads before turning the bus around for writes
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.rdPerTurnAround::total 75110 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 75110 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.315124 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.869848 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 6.130210 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 32 0.04% 0.04% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 20 0.03% 0.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 14 0.02% 0.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 62 0.08% 0.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 70906 94.40% 94.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 1379 1.84% 96.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 596 0.79% 97.20% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 313 0.42% 97.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 370 0.49% 98.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 506 0.67% 98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 145 0.19% 98.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 36 0.05% 99.03% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 45 0.06% 99.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 34 0.05% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 32 0.04% 99.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 33 0.04% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 412 0.55% 99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 33 0.04% 99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 44 0.06% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 25 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 12 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 8 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.00% 99.94% # Writes before turning the bus around for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 27 0.04% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 4 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 75110 # Writes before turning the bus around for reads
system.physmem.totQLat 44722536913 # Total ticks spent queuing
system.physmem.totMemAccLat 73491786913 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 7671800000 # Total ticks spent in databus transfers
system.physmem.avgQLat 29147.36 # Average queueing delay per DRAM burst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.avgMemAccLat 47897.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.92 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.62 # Average system write bandwidth in MiByte/s
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing
system.physmem.readRowHits 1262545 # Number of row buffer hits during reads
system.physmem.writeRowHits 973277 # Number of row buffer hits during writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem.writeRowHitRate 74.84 # Row buffer hit rate for writes
system.physmem.avgGap 18056482.14 # Average gap between requests
system.physmem.pageHitRate 78.87 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 2313095400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 1262105625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 5965736400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4233895920 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1235329874865 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 29661514581750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 34257490791960 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.544567 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 49344314821819 # Time in different power states
system.physmem_0.memoryStateTime::REF 1711079500000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_0.memoryStateTime::ACT 186501218681 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_1.actEnergy 2215919160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1209082875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 6002224800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4193596800 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3346871502000 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1231628029245 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 29664761814750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 34256882169630 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.532689 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 49349717648088 # Time in different power states
system.physmem_1.memoryStateTime::REF 1711079500000 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.physmem_1.memoryStateTime::ACT 181098330662 # Time in different power states
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 2212 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 1408 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 2176 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 22 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 27 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 43 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 27 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 42 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.branchPred.lookups 131237057 # Number of BP lookups
system.cpu0.branchPred.condPredicted 89167205 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 5638568 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 88557097 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 64192129 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.branchPred.BTBHitPct 72.486713 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 17175820 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 188370 # Number of incorrect RAS predictions.
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu_clk_domain.clock 500 # Clock period in ticks
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walks 905525 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 905525 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16897 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 92924 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 558822 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 346703 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2425.430412 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 13757.880539 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 344211 99.28% 99.28% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 1816 0.52% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 412 0.12% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 106 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 81 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 346703 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 421563 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22489.281555 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18275.838186 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 16656.658640 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 412599 97.87% 97.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7935 1.88% 99.76% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 523 0.12% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 370 0.09% 99.97% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 86 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 421563 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 359417936788 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.126321 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.679023 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-3 358421610788 99.72% 99.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-7 547811500 0.15% 99.88% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-11 199809500 0.06% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-15 118742000 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-19 45429500 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::20-23 23353000 0.01% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::24-27 23408000 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::28-31 31953500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::32-35 5493500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::36-39 315500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::40-43 10000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 359417936788 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 92925 84.61% 84.61% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 16897 15.39% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 109822 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 905525 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 905525 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109822 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109822 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 1015347 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.read_hits 104324024 # DTB read hits
system.cpu0.dtb.read_misses 622142 # DTB read misses
system.cpu0.dtb.write_hits 81549080 # DTB write hits
system.cpu0.dtb.write_misses 283383 # DTB write misses
system.cpu0.dtb.flush_tlb 1078 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 56138 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 9448 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.perms_faults 55690 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 104946166 # DTB read accesses
system.cpu0.dtb.write_accesses 81832463 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dtb.hits 185873104 # DTB hits
system.cpu0.dtb.misses 905525 # DTB misses
system.cpu0.dtb.accesses 186778629 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walks 104491 # Table walker walks requested
system.cpu0.itb.walker.walksLong 104491 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2977 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70833 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 14071 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 90420 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1597.942933 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 9019.721733 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 89473 98.95% 98.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 526 0.58% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 276 0.31% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 90 0.10% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 22 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 90420 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 87881 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27928.608004 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23671.030961 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 18442.594011 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 85773 97.60% 97.60% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 1788 2.03% 99.64% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 210 0.24% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 26 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 87881 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 587048610976 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.928143 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.258729 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 42249088256 7.20% 7.20% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 544740674220 92.79% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 52941500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 5346000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4 541000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::5 5000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::6 15000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 587048610976 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 70833 95.97% 95.97% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 2977 4.03% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 73810 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 104491 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 104491 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73810 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73810 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 178301 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 93910274 # ITB inst hits
system.cpu0.itb.inst_misses 104491 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.flush_tlb 1078 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.flush_tlb_mva_asid 22319 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 542 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 41605 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.perms_faults 209342 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.itb.inst_accesses 94014765 # ITB inst accesses
system.cpu0.itb.hits 93910274 # DTB hits
system.cpu0.itb.misses 104491 # DTB misses
system.cpu0.itb.accesses 94014765 # DTB accesses
system.cpu0.numCycles 672837873 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.fetch.icacheStallCycles 242596168 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 583871358 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 131237057 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 81367949 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 391672300 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 12912795 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2559887 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 21371 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingDrainCycles 5907 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu0.fetch.PendingTrapStallCycles 5496890 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 161597 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 2291 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 93683695 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 3482115 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 41656 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 648972539 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.054070 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.303352 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.fetch.rateDist::0 504751488 77.78% 77.78% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 18012631 2.78% 80.55% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 17993966 2.77% 83.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 13374247 2.06% 85.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 28570124 4.40% 89.79% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 8915108 1.37% 91.16% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 9700378 1.49% 92.66% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 8355653 1.29% 93.94% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 39298944 6.06% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.fetch.rateDist::total 648972539 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.195050 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.867774 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 196814484 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 328839067 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 104545498 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 13685712 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5085585 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19454701 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 1390261 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 638009836 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 4286683 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5085585 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 204391005 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 27392255 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 259209600 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 110517948 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 42373779 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 623249202 # Number of instructions processed by rename
system.cpu0.rename.ROBFullEvents 71579 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 1876177 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 1615058 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 22749976 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 3905 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 596805281 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 963507479 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 737465972 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 746816 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 504819765 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 91985511 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 15562034 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 13603964 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 76990444 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 100130044 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 85693466 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 13752433 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 14485683 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 591325254 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 15668453 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 593122197 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 836144 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 77301127 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 49722084 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 361977 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 648972539 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.913940 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.642087 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iq.issued_per_cycle::0 415433099 64.01% 64.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 99398694 15.32% 79.33% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 43154141 6.65% 85.98% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 30671240 4.73% 90.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 22754813 3.51% 94.21% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 15949435 2.46% 96.67% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 10913282 1.68% 98.35% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 6427298 0.99% 99.34% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 4270537 0.66% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iq.issued_per_cycle::total 648972539 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iq.fu_full::IntAlu 2981405 25.56% 25.56% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 22602 0.19% 25.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 2507 0.02% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.78% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 4779561 40.98% 66.76% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 3875984 33.24% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iq.FU_type_0::No_OpClass 47 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 402622584 67.88% 67.88% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1399505 0.24% 68.12% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 65721 0.01% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 48 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 57538 0.01% 68.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 106372763 17.93% 86.07% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 82603986 13.93% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iq.FU_type_0::total 593122197 # Type of FU issued
system.cpu0.iq.rate 0.881523 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 11662060 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1846708499 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 684493895 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 571889273 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1006638 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 498386 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 446935 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 604246281 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 537929 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 4762645 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iew.lsq.thread0.squashedLoads 15679208 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 19927 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 708487 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 8639603 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iew.lsq.thread0.rescheduledLoads 3917286 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 7883426 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iew.iewSquashCycles 5085585 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 15009758 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 10941422 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 607129936 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 1704783 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 100130044 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 85693466 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 13307217 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 240581 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 10607814 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 708487 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 2549086 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 2233115 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 4782201 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 586634430 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 104313037 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 5594967 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.exec_swp 0 # number of swp insts executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iew.exec_nop 136229 # number of nop insts executed
system.cpu0.iew.exec_refs 185865379 # number of memory reference insts executed
system.cpu0.iew.exec_branches 108795926 # Number of branches executed
system.cpu0.iew.exec_stores 81552342 # Number of stores executed
system.cpu0.iew.exec_rate 0.871881 # Inst execution rate
system.cpu0.iew.wb_sent 573547999 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 572336208 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 282398495 # num instructions producing a value
system.cpu0.iew.wb_consumers 490722197 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.iew.wb_rate 0.850630 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.575475 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.commitSquashedInsts 77341674 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 15306476 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4267486 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 635759269 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.833165 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.828636 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.committed_per_cycle::0 440698390 69.32% 69.32% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 96997007 15.26% 84.58% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 32966862 5.19% 89.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 15106149 2.38% 92.14% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 10791866 1.70% 93.83% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 6453132 1.02% 94.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6019295 0.95% 95.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3918041 0.62% 96.41% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 22808527 3.59% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.committed_per_cycle::total 635759269 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 450546917 # Number of instructions committed
system.cpu0.commit.committedOps 529692575 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.refs 161504698 # Number of memory references committed
system.cpu0.commit.loads 84450835 # Number of loads committed
system.cpu0.commit.membars 3736231 # Number of memory barriers committed
system.cpu0.commit.branches 100681556 # Number of branches committed
system.cpu0.commit.fp_insts 429176 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 486199452 # Number of committed integer instructions.
system.cpu0.commit.function_calls 13322938 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.op_class_0::IntAlu 366991615 69.28% 69.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1098704 0.21% 69.49% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 48820 0.01% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 48738 0.01% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 84450835 15.94% 85.45% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 77053863 14.55% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.commit.op_class_0::total 529692575 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22808527 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1215947592 # The number of ROB reads
system.cpu0.rob.rob_writes 1227300023 # The number of ROB writes
system.cpu0.timesIdled 4042817 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 23865334 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 48376378387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 450546917 # Number of Instructions Simulated
system.cpu0.committedOps 529692575 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.493380 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.493380 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.669622 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.669622 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 692384326 # number of integer regfile reads
system.cpu0.int_regfile_writes 408324633 # number of integer regfile writes
system.cpu0.fp_regfile_reads 809160 # number of floating regfile reads
system.cpu0.fp_regfile_writes 477572 # number of floating regfile writes
system.cpu0.cc_regfile_reads 126161613 # number of cc regfile reads
system.cpu0.cc_regfile_writes 127342866 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1198291262 # number of misc regfile reads
system.cpu0.misc_regfile_writes 15447790 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 10676503 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.983474 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 304546323 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 10677015 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 28.523545 # Average number of references to valid blocks.
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.warmup_cycle 1659069500 # Cycle when the warmup percentage was hit.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.occ_blocks::cpu0.data 293.453166 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 218.530308 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.573151 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.426817 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.tags.tag_accesses 1344556090 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 1344556090 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 79999086 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 80528903 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 160527989 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 67561475 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 67996777 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 135558252 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 203785 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202222 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 406007 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 172640 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153185 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 325825 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1797141 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1773094 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 3570235 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2068264 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2042534 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 4110798 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 147560561 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 148525680 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 296086241 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 147764346 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 148727902 # number of overall hits
system.cpu0.dcache.overall_hits::total 296492248 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 6141795 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 6528764 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 12670559 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 6608479 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 6465845 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 13074324 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649478 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 677361 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 1326839 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 635249 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu1.data 605487 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 1240736 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 328601 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 329591 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 658192 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7 # number of StoreCondReq misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_misses::cpu1.data 3 # number of StoreCondReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 12750274 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 12994609 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 25744883 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 13399752 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 13671970 # number of overall misses
system.cpu0.dcache.overall_misses::total 27071722 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 94431381500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 100570450000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 195001831500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 229012929937 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 223645956318 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 452658886255 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 33967464475 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 32913724847 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 66881189322 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4162185500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4276509000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 8438694500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 161500 # number of StoreCondReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 108000 # number of StoreCondReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_miss_latency::total 269500 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 323444311437 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 324216406318 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 647660717755 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 323444311437 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 324216406318 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 647660717755 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 86140881 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 87057667 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 173198548 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 74169954 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 74462622 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 148632576 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853263 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 879583 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 1732846 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 807889 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 758672 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 1566561 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2125742 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2102685 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 4228427 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2068271 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2042537 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 4110808 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 160310835 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 161520289 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 321831124 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 161164098 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 162399872 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 323563970 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071299 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074994 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.073156 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089099 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086833 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.087964 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761170 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.770093 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765699 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.786307 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.798088 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792013 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154582 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156748 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.155659 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000003 # miss rate for StoreCondReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079535 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080452 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.079995 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.083144 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.084187 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.083667 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15375.208958 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15404.209740 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15390.152202 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34654.408365 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34588.821155 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34621.972521 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 53471.102631 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 54359.094162 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 53904.448103 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12666.381113 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12975.199566 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12821.022589 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23071.428571 # average StoreCondReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36000 # average StoreCondReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26950 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25367.636134 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24950.070165 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 25156.871669 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24138.081917 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23713.949513 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 23923.883296 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 67819583 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 50977 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 3590540 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 1007 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.888408 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 50.622642 # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.writebacks::writebacks 8163245 # number of writebacks
system.cpu0.dcache.writebacks::total 8163245 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3314208 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3616670 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 6930878 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5502274 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5376459 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 10878733 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3693 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3290 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 6983 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 202459 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 202911 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 405370 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 8816482 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 8993129 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 17809611 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 8816482 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 8993129 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 17809611 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2827587 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2912094 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 5739681 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1106205 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1089386 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 2195591 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 640410 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 661534 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 1301944 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 631556 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 602197 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 1233753 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126142 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 126680 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 252822 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7 # number of StoreCondReq MSHR misses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 3 # number of StoreCondReq MSHR misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 3933792 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 4001480 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 7935272 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4574202 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4663014 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 9237216 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17080 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16596 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33676 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18113 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15582 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33695 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35193 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 32178 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67371 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43873755000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 45263684000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 89137439000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39703297752 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 38710304225 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 78413601977 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10229018500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12106764000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22335782500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 33180093475 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 32187853347 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65367946822 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1698558000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1735409000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3433967000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 154500 # number of StoreCondReq MSHR miss cycles
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 105000 # number of StoreCondReq MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 259500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83577052752 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83973988225 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 167551040977 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 93806071252 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96080752225 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 189886823477 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2986588500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2854625000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5841213500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2919463491 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2774139500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5693602991 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5906051991 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5628764500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11534816491 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032825 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033450 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033139 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014914 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014630 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014772 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750542 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752100 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751333 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.781736 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.793751 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787555 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059340 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060247 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059791 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024539 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024774 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.024657 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028382 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028713 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.028548 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15516.323636 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15543.345785 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15530.033638 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35891.446660 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35534.057006 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35714.120698 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15972.608954 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18301.045751 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17155.716759 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 52537.056848 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 53450.703585 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 52983.009421 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13465.443706 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13699.155352 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13582.548196 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22071.428571 # average StoreCondReq mshr miss latency
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25950 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21245.925751 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20985.732335 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21114.719316 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20507.636360 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20604.860338 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20556.715733 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174858.811475 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172006.808870 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173453.305024 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161180.560426 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178034.879990 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168974.714082 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 167818.941011 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174925.865498 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 171213.378026 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.replacements 16087139 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.947221 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 170921783 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 16087651 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 10.624409 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 16333976500 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.838488 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 236.108732 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.538747 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.461150 # Average percentage of cache occupancy
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.tags.occ_percent::total 0.999897 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.tags.tag_accesses 204325556 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 204325556 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 85081339 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 85840444 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 170921783 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 85081339 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 85840444 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 170921783 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 85081339 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 85840444 # number of overall hits
system.cpu0.icache.overall_hits::total 170921783 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 8589868 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 8726123 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 17315991 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 8589868 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 8726123 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 17315991 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 8589868 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 8726123 # number of overall misses
system.cpu0.icache.overall_misses::total 17315991 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 112329905402 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 114108527365 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 226438432767 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 112329905402 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 114108527365 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 226438432767 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 112329905402 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 114108527365 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 226438432767 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 93671207 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 94566567 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 188237774 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 93671207 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 94566567 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 188237774 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 93671207 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 94566567 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 188237774 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.091702 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.092275 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.091990 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.091702 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.092275 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.091990 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.091702 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.092275 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.091990 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13077.023466 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13076.658141 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 13076.839366 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13077.023466 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13076.658141 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 13076.839366 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13077.023466 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13076.658141 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 13076.839366 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 85300 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.blocked::no_mshrs 7438 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.avg_blocked_cycles::no_mshrs 11.468137 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 606680 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 621529 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 1228209 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 606680 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu1.inst 621529 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 1228209 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 606680 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu1.inst 621529 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 1228209 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7983188 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8104594 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 16087782 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 7983188 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 8104594 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 16087782 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 7983188 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8104594 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16087782 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12465 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8175 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20640 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12465 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8175 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20640 # number of overall MSHR uncacheable misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99492670437 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101031835906 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 200524506343 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99492670437 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101031835906 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 200524506343 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99492670437 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101031835906 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 200524506343 # number of overall MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 965827500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 632670500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1598498000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 965827500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 632670500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1598498000 # number of overall MSHR uncacheable cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085465 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.085465 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085226 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085703 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.085465 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12464.397289 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12464.397289 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12462.774325 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12465.995941 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12464.397289 # average overall mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 77446.608527 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 77483.152828 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 77390.886850 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 77446.608527 # average overall mshr uncacheable latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.branchPred.lookups 132090219 # Number of BP lookups
system.cpu1.branchPred.condPredicted 89757318 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 5756723 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 89315962 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 64542834 # Number of BTB hits
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.branchPred.BTBHitPct 72.263493 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17132912 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 188342 # Number of incorrect RAS predictions.
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walks 899065 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 899065 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16912 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92517 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 553507 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 345558 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2400.667905 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13912.564680 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535 343096 99.29% 99.29% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071 1764 0.51% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607 399 0.12% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.02% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 345558 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 421889 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 22499.157361 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18375.438889 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 16484.116423 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535 412836 97.85% 97.85% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8131 1.93% 99.78% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607 432 0.10% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143 347 0.08% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215 30 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 421889 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 324784285420 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.056472 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.661085 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-3 323808973920 99.70% 99.70% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-7 531761500 0.16% 99.86% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-11 194206000 0.06% 99.92% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-15 116904000 0.04% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-19 46719500 0.01% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::20-23 26039000 0.01% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::24-27 24606500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::28-31 29193500 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::32-35 5603500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::40-43 17000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::48-51 2000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 324784285420 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 92517 84.55% 84.55% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 16912 15.45% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 109429 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 899065 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 899065 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109429 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109429 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 1008494 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.read_hits 105725858 # DTB read hits
system.cpu1.dtb.read_misses 617527 # DTB read misses
system.cpu1.dtb.write_hits 81869169 # DTB write hits
system.cpu1.dtb.write_misses 281538 # DTB write misses
system.cpu1.dtb.flush_tlb 1084 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 55091 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 8923 # Number of TLB faults due to prefetch
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.perms_faults 57008 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 106343385 # DTB read accesses
system.cpu1.dtb.write_accesses 82150707 # DTB write accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.dtb.hits 187595027 # DTB hits
system.cpu1.dtb.misses 899065 # DTB misses
system.cpu1.dtb.accesses 188494092 # DTB accesses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walks 107064 # Table walker walks requested
system.cpu1.itb.walker.walksLong 107064 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3059 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 73056 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 14602 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 92462 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 1594.287383 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 9428.868117 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 91539 99.00% 99.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 493 0.53% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 272 0.29% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 87 0.09% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 28 0.03% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-229375 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 92462 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 90717 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 28181.123714 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 24098.190167 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18325.203286 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 49691 54.78% 54.78% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 38968 42.96% 97.73% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 889 0.98% 98.71% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 845 0.93% 99.64% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 113 0.12% 99.77% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 103 0.11% 99.88% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 30 0.03% 99.91% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 24 0.03% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 11 0.01% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.01% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 90717 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 612488746252 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.881369 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.323767 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 72732513396 11.87% 11.87% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 539691898856 88.11% 99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 57837000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 5354000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 885500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::5 253500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::6 4000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 612488746252 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 73056 95.98% 95.98% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 3059 4.02% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 76115 # Table walker page sizes translated
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 107064 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 107064 # Table walker requests started/completed, data/inst
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 76115 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 76115 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 183179 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 94801988 # ITB inst hits
system.cpu1.itb.inst_misses 107064 # ITB inst misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.flush_tlb 1084 # Number of times complete TLB was flushed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 529 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 40979 # Number of entries that have been flushed from TLB
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.perms_faults 204318 # Number of TLB faults due to permissions restrictions
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.itb.inst_accesses 94909052 # ITB inst accesses
system.cpu1.itb.hits 94801988 # DTB hits
system.cpu1.itb.misses 107064 # DTB misses
system.cpu1.itb.accesses 94909052 # DTB accesses
system.cpu1.numCycles 671476106 # number of cpu cycles simulated
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.fetch.icacheStallCycles 245366519 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 588017734 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 132090219 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 81675746 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 387641424 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 13138102 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 2647355 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 22361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingDrainCycles 4505 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu1.fetch.PendingTrapStallCycles 5327205 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 166052 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 2673 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 94574767 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 3547562 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 42774 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 647746875 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.062629 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.311059 # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.fetch.rateDist::0 502555880 77.59% 77.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 18134910 2.80% 80.38% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 18417584 2.84% 83.23% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 13370411 2.06% 85.29% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 28474947 4.40% 89.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 9035668 1.39% 91.08% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 9746929 1.50% 92.59% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 8410613 1.30% 93.89% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 39599933 6.11% 100.00% # Number of instructions fetched each cycle (Total)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.fetch.rateDist::total 647746875 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.196716 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.875709 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 199564404 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 323792643 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 105578746 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 13636228 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 5172543 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 19679879 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 1416500 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 642218643 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 4358994 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 5172543 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 207175837 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 26230498 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 253904637 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 111453983 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 43806880 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 627356682 # Number of instructions processed by rename
system.cpu1.rename.ROBFullEvents 88872 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 2222363 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 1667701 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 24272659 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 3825 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 600705753 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 967034808 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 741797210 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 803110 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 507019119 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 93686634 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 15251472 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 13261267 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 76352353 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 101066741 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 86034098 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 13578571 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 14575923 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 595450227 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 15308226 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 597111513 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 840860 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 78779365 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 50277835 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 362203 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 647746875 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.921828 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.648992 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.issued_per_cycle::0 413645402 63.86% 63.86% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 98786426 15.25% 79.11% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 43350634 6.69% 85.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 30948406 4.78% 90.58% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 23128317 3.57% 94.15% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 16110243 2.49% 96.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 11031117 1.70% 98.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 6443224 0.99% 99.34% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 4303106 0.66% 100.00% # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.issued_per_cycle::total 647746875 # Number of insts issued each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.fu_full::IntAlu 3034292 25.34% 25.34% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 25435 0.21% 25.56% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 2765 0.02% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.58% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 4931574 41.19% 66.77% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 3978849 33.23% 100.00% # attempts to use FU when none available
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.FU_type_0::No_OpClass 52 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 404756244 67.79% 67.79% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1480116 0.25% 68.03% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 67236 0.01% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 53 0.00% 68.04% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.FU_type_0::SimdMultAcc 2 0.00% 68.04% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.04% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.04% # Type of FU issued
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.FU_type_0::SimdFloatMisc 71191 0.01% 68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 107813613 18.06% 86.11% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 82922942 13.89% 100.00% # Type of FU issued
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iq.FU_type_0::total 597111513 # Type of FU issued
system.cpu1.iq.rate 0.889252 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 11972916 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.020051 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1853695544 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 689699314 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 575118751 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1088133 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 538121 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 485191 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 608503665 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 580712 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 4698016 # Number of loads that had data forwarded from stores
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iew.lsq.thread0.squashedLoads 15955461 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 21531 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 710912 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 8765717 # Number of stores squashed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iew.lsq.thread0.rescheduledLoads 3921205 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 8400525 # Number of times an access to memory failed due to the cache being blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iew.iewSquashCycles 5172543 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 14653668 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 9919586 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 610892135 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 1742457 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 101066741 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 86034098 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12972500 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 236911 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 9594506 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 710912 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 2600980 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2287673 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4888653 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 590524927 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 105716307 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 5700612 # Number of squashed instructions skipped in execute
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.exec_swp 0 # number of swp insts executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iew.exec_nop 133682 # number of nop insts executed
system.cpu1.iew.exec_refs 187585376 # number of memory reference insts executed
system.cpu1.iew.exec_branches 109412564 # Number of branches executed
system.cpu1.iew.exec_stores 81869069 # Number of stores executed
system.cpu1.iew.exec_rate 0.879443 # Inst execution rate
system.cpu1.iew.wb_sent 576824246 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 575603942 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 284399442 # num instructions producing a value
system.cpu1.iew.wb_consumers 494076723 # num instructions consuming a value
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.iew.wb_rate 0.857222 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.575618 # average fanout of values written-back
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.commitSquashedInsts 78818099 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14946023 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4359945 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 634288153 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.838703 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.835068 # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.committed_per_cycle::0 439406713 69.28% 69.28% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 96089140 15.15% 84.42% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 33004326 5.20% 89.63% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 15342101 2.42% 92.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 10933751 1.72% 93.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 6607641 1.04% 94.81% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 6115019 0.96% 95.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3924026 0.62% 96.40% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 22865436 3.60% 100.00% # Number of insts commited each cycle
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.committed_per_cycle::total 634288153 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 452878140 # Number of instructions committed
system.cpu1.commit.committedOps 531979088 # Number of ops (including micro ops) committed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.refs 162379661 # Number of memory references committed
system.cpu1.commit.loads 85111280 # Number of loads committed
system.cpu1.commit.membars 3699604 # Number of memory barriers committed
system.cpu1.commit.branches 101084293 # Number of branches committed
system.cpu1.commit.fp_insts 466365 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 488261253 # Number of committed integer instructions.
system.cpu1.commit.function_calls 13274874 # Number of function calls committed.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.op_class_0::IntAlu 368350296 69.24% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 1137362 0.21% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 50458 0.01% 69.46% # Class of committed instruction
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.46% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.op_class_0::SimdFloatMisc 61269 0.01% 69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 85111280 16.00% 85.48% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 77268381 14.52% 100.00% # Class of committed instruction
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu1.commit.op_class_0::total 531979088 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22865436 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1218285123 # The number of ROB reads
system.cpu1.rob.rob_writes 1235075441 # The number of ROB writes
system.cpu1.timesIdled 4119845 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 23729231 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 52762738169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 452878140 # Number of Instructions Simulated
system.cpu1.committedOps 531979088 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.482686 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.482686 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.674452 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.674452 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 696400049 # number of integer regfile reads
system.cpu1.int_regfile_writes 410875535 # number of integer regfile writes
system.cpu1.fp_regfile_reads 865968 # number of floating regfile reads
system.cpu1.fp_regfile_writes 525416 # number of floating regfile writes
system.cpu1.cc_regfile_reads 127021368 # number of cc regfile reads
system.cpu1.cc_regfile_writes 128126601 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1197743929 # number of misc regfile reads
system.cpu1.misc_regfile_writes 15078416 # number of misc regfile writes
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::ReadReq 40301 # Transaction distribution
system.iobus.trans_dist::ReadResp 40301 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_count::total 353744 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.pkt_size::total 7492192 # Cumulative packet size per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iobus.reqLayer27.occupancy 568866585 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer3.occupancy 147720000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.replacements 115461 # number of replacements
system.iocache.tags.tagsinuse 10.416117 # Cycle average of tags in use
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks.
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.tags.warmup_cycle 13093305735000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.549567 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 6.866551 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.221848 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.429159 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.651007 # Average percentage of cache occupancy
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.tags.tag_accesses 1039677 # Number of tag accesses
system.iocache.tags.data_accesses 1039677 # Number of data accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses
system.iocache.demand_misses::total 8856 # number of demand (read+write) misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_misses::realview.ide 8816 # number of overall misses
system.iocache.overall_misses::total 8856 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_miss_latency::realview.ide 1629394165 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1634463165 # number of ReadReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.WriteLineReq_miss_latency::realview.ide 12612717420 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12612717420 # number of WriteLineReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_miss_latency::realview.ide 1629394165 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 1634814165 # number of demand (read+write) miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_miss_latency::realview.ide 1629394165 # number of overall miss cycles
system.iocache.overall_miss_latency::total 1634814165 # number of overall miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_avg_miss_latency::realview.ide 184822.387137 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 184622.519485 # average ReadReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118247.181992 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 118247.181992 # average WriteLineReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 184599.612127 # average overall miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_avg_miss_latency::realview.ide 184822.387137 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 184599.612127 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 31652 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.avg_blocked_cycles::no_mshrs 9.451179 # average number of cycles each access was blocked
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.iocache.fast_writes 0 # number of fast writes performed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.writebacks::writebacks 106630 # number of writebacks
system.iocache.writebacks::total 106630 # number of writebacks
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_mshr_misses::realview.ide 8816 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8853 # number of ReadReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_mshr_misses::realview.ide 8816 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 8856 # number of demand (read+write) MSHR misses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_mshr_misses::realview.ide 8816 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8856 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188594165 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1191813165 # number of ReadReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7279517420 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7279517420 # number of WriteLineReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_mshr_miss_latency::realview.ide 1188594165 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 1192014165 # number of demand (read+write) MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_mshr_miss_latency::realview.ide 1188594165 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 1192014165 # number of overall MSHR miss cycles
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134822.387137 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 134622.519485 # average ReadReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68247.181992 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68247.181992 # average WriteLineReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.demand_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.iocache.overall_avg_mshr_miss_latency::realview.ide 134822.387137 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 134599.612127 # average overall mshr miss latency
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.replacements 1414414 # number of replacements
system.l2c.tags.tagsinuse 65287.875921 # Cycle average of tags in use
system.l2c.tags.total_refs 50028752 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1477251 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 33.866115 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 15277469000 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 35504.413846 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 175.319867 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 252.399214 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 3604.019001 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 8668.612883 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 168.198781 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 249.035174 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 3764.497441 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 12901.379713 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.541754 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002675 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.003851 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.054993 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.132273 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002567 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.003800 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.057442 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.196859 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.996214 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 266 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 62571 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2814 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 5105 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 54035 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.004059 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.954758 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 445125308 # Number of tag accesses
system.l2c.tags.data_accesses 445125308 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 529471 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 186836 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 532880 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 194253 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1443440 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 8163245 # number of Writeback hits
system.l2c.Writeback_hits::total 8163245 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 5159 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4935 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 10094 # number of UpgradeReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadExReq_hits::cpu0.data 802127 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 795144 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 1597271 # number of ReadExReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 7936245 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 8056010 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::total 15992255 # number of ReadCleanReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 3437949 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 3523138 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 6961087 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 361682 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 352463 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 714145 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 529471 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 186836 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 7936245 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 4240076 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 532880 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 194253 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 8056010 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 4318282 # number of demand (read+write) hits
system.l2c.demand_hits::total 25994053 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 529471 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 186836 # number of overall hits
system.l2c.overall_hits::cpu0.inst 7936245 # number of overall hits
system.l2c.overall_hits::cpu0.data 4240076 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 532880 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 194253 # number of overall hits
system.l2c.overall_hits::cpu1.inst 8056010 # number of overall hits
system.l2c.overall_hits::cpu1.data 4318282 # number of overall hits
system.l2c.overall_hits::total 25994053 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 2596 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2347 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 2527 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.itb.walker 2344 # number of ReadReq misses
system.l2c.ReadReq_misses::total 9814 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 18684 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 17988 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 36672 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 286935 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 277647 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 564582 # number of ReadExReq misses
system.l2c.ReadCleanReq_misses::cpu0.inst 46865 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::cpu1.inst 48510 # number of ReadCleanReq misses
system.l2c.ReadCleanReq_misses::total 95375 # number of ReadCleanReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 149491 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 170842 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 320333 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 269874 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 249734 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 519608 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 2596 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2347 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 46865 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 436426 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 2527 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 2344 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 48510 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 448489 # number of demand (read+write) misses
system.l2c.demand_misses::total 990104 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 2596 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2347 # number of overall misses
system.l2c.overall_misses::cpu0.inst 46865 # number of overall misses
system.l2c.overall_misses::cpu0.data 436426 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 2527 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 2344 # number of overall misses
system.l2c.overall_misses::cpu1.inst 48510 # number of overall misses
system.l2c.overall_misses::cpu1.data 448489 # number of overall misses
system.l2c.overall_misses::total 990104 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 226666000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 208137000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 222854000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.itb.walker 211048000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 868705000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0.data 286606000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 278244500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 564850500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 28759533500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 27874280000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 56633813500 # number of ReadExReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4006344499 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4103874000 # number of ReadCleanReq miss cycles
system.l2c.ReadCleanReq_miss_latency::total 8110218499 # number of ReadCleanReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 13350704000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 15601640500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 28952344500 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 27675709000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 26863663000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 54539372000 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 226666000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 208137000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 4006344499 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 42110237500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 222854000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 211048000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4103874000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 43475920500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 94565081499 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 226666000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 208137000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 4006344499 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 42110237500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 222854000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 211048000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4103874000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 43475920500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 94565081499 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 532067 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 189183 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 535407 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 196597 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1453254 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 8163245 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 8163245 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 23843 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 22923 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 46766 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 7 # number of SCUpgradeReq accesses(hits+misses)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_accesses::cpu1.data 3 # number of SCUpgradeReq accesses(hits+misses)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 1089062 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 1072791 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 2161853 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu0.inst 7983110 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::cpu1.inst 8104520 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadCleanReq_accesses::total 16087630 # number of ReadCleanReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 3587440 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 3693980 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 7281420 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 631556 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 602197 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 1233753 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 532067 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 189183 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 7983110 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 4676502 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 535407 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 196597 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 8104520 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 4766771 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 26984157 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 532067 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 189183 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 7983110 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 4676502 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 535407 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 196597 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 8104520 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 4766771 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 26984157 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004879 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012406 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004720 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011923 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.006753 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.783626 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.784714 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.784159 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.142857 # miss rate for SCUpgradeReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.333333 # miss rate for SCUpgradeReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.263470 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.258808 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.261157 # miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005871 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005986 # miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_miss_rate::total 0.005928 # miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.041671 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.046249 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.043993 # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data 0.427316 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data 0.414705 # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total 0.421160 # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004879 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.012406 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.005871 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.093323 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004720 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.011923 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.005986 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.094087 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.036692 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004879 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.012406 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.005871 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.093323 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004720 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.011923 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.005986 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.094087 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.036692 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87313.559322 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88682.147422 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88189.157103 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 90037.542662 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 88516.914612 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15339.648897 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15468.340004 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15402.773233 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 100230.134002 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 100394.673812 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 100311.050476 # average ReadExReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 85486.919855 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 84598.515770 # average ReadCleanReq miss latency
system.l2c.ReadCleanReq_avg_miss_latency::total 85035.056346 # average ReadCleanReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89307.744279 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91322.043174 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 90382.022770 # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 102550.482818 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 107569.105528 # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total 104962.533294 # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87313.559322 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88682.147422 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 85486.919855 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 96488.837741 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88189.157103 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 90037.542662 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 84598.515770 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 96938.655129 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 95510.250942 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87313.559322 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88682.147422 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 85486.919855 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 96488.837741 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88189.157103 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 90037.542662 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 84598.515770 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 96938.655129 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 95510.250942 # average overall miss latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.writebacks::writebacks 1193601 # number of writebacks
system.l2c.writebacks::total 1193601 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 12 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 32 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 14 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 28 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadSharedReq_mshr_hits::cpu0.data 10 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data 12 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.demand_mshr_hits::cpu0.dtb.walker 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.itb.walker 32 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.demand_mshr_hits::cpu0.data 10 # number of demand (read+write) MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.demand_mshr_hits::cpu1.dtb.walker 14 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.itb.walker 28 # number of demand (read+write) MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.dtb.walker 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.itb.walker 32 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_hits::cpu0.data 10 # number of overall MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_hits::cpu1.dtb.walker 14 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.itb.walker 28 # number of overall MSHR hits
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_hits::total 110 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2584 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2315 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2513 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2316 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 9728 # number of ReadReq MSHR misses
system.l2c.CleanEvict_mshr_misses::writebacks 1098 # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total 1098 # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 18684 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 17988 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 36672 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
2014-12-23 15:31:20 +01:00
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 286935 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 277647 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 564582 # number of ReadExReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 46863 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 48510 # number of ReadCleanReq MSHR misses
system.l2c.ReadCleanReq_mshr_misses::total 95373 # number of ReadCleanReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 149481 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 170830 # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total 320311 # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data 269874 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data 249734 # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total 519608 # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker 2584 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2315 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 46863 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 436416 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 2513 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker 2316 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 48510 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 448477 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 989994 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker 2584 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2315 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 46863 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 436416 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 2513 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker 2316 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 48510 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 448477 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 989994 # number of overall MSHR misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 12465 # number of ReadReq MSHR uncacheable
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17080 # number of ReadReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 8175 # number of ReadReq MSHR uncacheable
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16596 # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total 54316 # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18113 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 15582 # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total 33695 # number of WriteReq MSHR uncacheable
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 12465 # number of overall MSHR uncacheable misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35193 # number of overall MSHR uncacheable misses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 8175 # number of overall MSHR uncacheable misses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 32178 # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total 88011 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 199854500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 182923500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 196571500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 185980500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 765330000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 387591999 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 373200500 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 760792499 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 71000 # number of SCUpgradeReq MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 25890183500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 25097810000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 50987993500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 3537569999 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 3618774000 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadCleanReq_mshr_miss_latency::total 7156343999 # number of ReadCleanReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11855172500 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13892574000 # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 25747746500 # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 24976969000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 24366323000 # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total 49343292000 # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 199854500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 182923500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 3537569999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 37745356000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 196571500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 185980500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 3618774000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 38990384000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 84657413999 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 199854500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 182923500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 3537569999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 37745356000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196571500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 185980500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 3618774000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 38990384000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 84657413999 # number of overall MSHR miss cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 772594499 # number of ReadReq MSHR uncacheable cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2773087000 # number of ReadReq MSHR uncacheable cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 505958000 # number of ReadReq MSHR uncacheable cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2647172500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 6698811999 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2709591500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2594934500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 5304526000 # number of WriteReq MSHR uncacheable cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 772594499 # number of overall MSHR uncacheable cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5482678500 # number of overall MSHR uncacheable cycles
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 505958000 # number of overall MSHR uncacheable cycles
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5242107000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 12003337999 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004857 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012237 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004694 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011780 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.006694 # mshr miss rate for ReadReq accesses
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.783626 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784714 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.784159 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.142857 # mshr miss rate for SCUpgradeReq accesses
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.333333 # mshr miss rate for SCUpgradeReq accesses
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.263470 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.258808 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.261157 # mshr miss rate for ReadExReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005870 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005986 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005928 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041668 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.046246 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.043990 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.427316 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.414705 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.421160 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004857 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012237 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005870 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.093321 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004694 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011780 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005986 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.094084 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.036688 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004857 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012237 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005870 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.093321 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004694 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011780 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005986 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.094084 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.036688 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 78672.902961 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20744.594252 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20747.192573 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20745.868755 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 90230.134002 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 90394.673812 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 90311.050476 # average ReadExReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75035.324452 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79308.892100 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81323.971199 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 80383.585016 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 92550.482818 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 97569.105528 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 94962.533294 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77343.072755 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79016.630670 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75487.484775 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86489.395439 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78221.846399 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80302.461140 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74598.515770 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86939.539820 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 85513.057654 # average overall mshr miss latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average ReadReq mshr uncacheable latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162358.723653 # average ReadReq mshr uncacheable latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average ReadReq mshr uncacheable latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159506.658231 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 123330.363042 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149593.744824 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166534.109870 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 157427.689568 # average WriteReq mshr uncacheable latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61981.107020 # average overall mshr uncacheable latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155788.892678 # average overall mshr uncacheable latency
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61890.886850 # average overall mshr uncacheable latency
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162909.658773 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 136384.520105 # average overall mshr uncacheable latency
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.trans_dist::ReadReq 54316 # Transaction distribution
system.membus.trans_dist::ReadResp 488581 # Transaction distribution
system.membus.trans_dist::WriteReq 33695 # Transaction distribution
system.membus.trans_dist::WriteResp 33695 # Transaction distribution
system.membus.trans_dist::Writeback 1300231 # Transaction distribution
system.membus.trans_dist::CleanEvict 226932 # Transaction distribution
system.membus.trans_dist::UpgradeReq 37530 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.membus.trans_dist::UpgradeResp 37532 # Transaction distribution
system.membus.trans_dist::ReadExReq 1083335 # Transaction distribution
system.membus.trans_dist::ReadExResp 1083335 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 434265 # Transaction distribution
stats: Update stats for cache, crossbar and DRAM changes This update includes the changes to whole-line writes, the refinement of Read to ReadClean and ReadShared, the introduction of CleanEvict for snoop-filter tracking, and updates to the DRAM command scheduler for bank-group-aware scheduling. Needless to say, almost every regression is affected.
2015-07-03 16:15:03 +02:00
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6852 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4552687 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4682321 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341290 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 341290 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5023611 # Packet count per connected master and slave (bytes)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13704 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174247596 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 174419346 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7230976 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7230976 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 181650322 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3166 # Total snoops (count)
system.membus.snoop_fanout::samples 3279708 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::1 3279708 100.00% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.snoop_fanout::total 3279708 # Request fanout histogram
system.membus.reqLayer0.occupancy 114259000 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.reqLayer2.occupancy 5427500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.reqLayer5.occupancy 8793071023 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.respLayer2.occupancy 8222412889 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.membus.respLayer3.occupancy 228888550 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
stats: Update ARM stats to include programmable oscillators
2015-08-07 16:39:17 +02:00
system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.trans_dist::ReadReq 2064834 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 25434780 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33695 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33695 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 9463502 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 18825810 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 46769 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 46779 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 2161853 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 2161853 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 16087782 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 7290273 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 1340417 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 1233753 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48300519 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32258677 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 920526 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2543246 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 84022968 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1030929280 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1127055058 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3086240 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8539792 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2169610370 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2203584 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 57319196 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.063782 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.244364 # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoop_fanout::1 53663256 93.62% 93.62% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 3655940 6.38% 100.00% # Request fanout histogram
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
stats: Update stats to reflect cache changes
2015-05-05 09:22:39 +02:00
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoop_fanout::total 57319196 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 36016999461 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.snoopLayer0.occupancy 1117500 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer0.occupancy 24175146802 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer1.occupancy 14858261870 # Layer occupancy (ticks)
stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
2015-03-02 11:04:20 +01:00
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer2.occupancy 535144651 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.toL2Bus.respLayer3.occupancy 1478603615 # Layer occupancy (ticks)
stats: Bump stats for fixes, mostly TLB and WriteInvalidate
2014-12-02 12:08:25 +01:00
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
stats: updates due to recent changesets including d0934b57735a
2015-09-15 15:14:09 +02:00
system.cpu0.kern.inst.quiesce 19287 # number of quiesce instructions executed
arm, tests: Add 64-bit ARM regression tests
2014-10-30 05:50:15 +01:00
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue Copy permalink