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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

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Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- Begin Simulation Statistics ----------
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
sim_seconds 0.000111 # Number of seconds simulated
sim_ticks 110804500 # Number of ticks simulated
final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
sim_freq 1000000000000 # Frequency of simulated ticks
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
host_inst_rate 170931 # Simulator instruction rate (inst/s)
host_op_rate 170931 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 18163832 # Simulator tick rate (ticks/s)
host_mem_usage 247816 # Number of bytes of host memory used
host_seconds 6.10 # Real time elapsed on the host
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
sim_insts 1042724 # Number of instructions simulated
sim_ops 1042724 # Number of ops (including micro ops) simulated
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 4672 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_read::total 42176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 4672 # Number of instructions bytes read from this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 73 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bw_read::cpu0.inst 205623418 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 97035770 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 5775939 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 7508720 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 42164353 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 11551877 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 3465563 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 7508720 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 380634361 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205623418 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 5775939 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 42164353 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 3465563 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 257029272 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205623418 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 97035770 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 5775939 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 7508720 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 42164353 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 11551877 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 3465563 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7508720 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 380634361 # Total bandwidth to/from this memory (bytes/s)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.readReqs 660 # Total number of read requests accepted by DRAM controller
system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
system.physmem.readBursts 660 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesRead 42176 # Total number of bytes read from memory
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesWritten 0 # Total number of bytes written to memory
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.neitherReadNorWrite 76 # Reqs where no action is needed
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.totGap 110776500 # Total gap between requests
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readPktSize::6 660 # Categorize read packet sizes
stats: Update stats to reflect SimpleDRAM changes This patch bumps the stats to reflect the slight change in how the retry is handled, and also the pruning of some redundant stats.
2013-03-01 19:20:30 +01:00
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.rdQLenPdf::0 404 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 193 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::mean 281.500000 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 172.723314 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 317.555625 # Bytes accessed per row activation
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.bytesPerActivate::1152 1 0.78% 98.44% # Bytes accessed per row activation
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.totQLat 3818750 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 18118750 # Sum of mem lat for all requests
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.totBusLat 3300000 # Total cycles spent in databus access
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.totBankLat 11000000 # Total cycles spent in bank access
system.physmem.avgQLat 5785.98 # Average queueing delay per request
system.physmem.avgBankLat 16666.67 # Average bank access latency per request
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.avgBusLat 5000.00 # Average bus latency per request
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgMemAccLat 27452.65 # Average memory access latency
system.physmem.avgRdBW 380.63 # Average achieved read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgConsumedRdBW 380.63 # Average consumed read bandwidth in MB/s
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.busUtil 2.97 # Data bus utilization in percentage
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.avgRdQLen 0.16 # Average read queue length over time
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.avgWrQLen 0.00 # Average write queue length over time
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHits 532 # Number of row buffer hits during reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
stats: Update stats to reflect use of SimpleDRAM This patch bumps the stats to match the use of SimpleDRAM instead of SimpleMemory in all inorder and O3 regressions, and also all full-system regressions. A number of performance-related stats change, and a whole bunch of stats are added for the memory controller.
2012-10-25 19:14:42 +02:00
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.physmem.avgGap 167843.18 # Average gap between requests
system.membus.throughput 380634361 # Throughput (bytes/s)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::ReadReq 529 # Transaction distribution
system.membus.trans_dist::ReadResp 528 # Transaction distribution
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
system.membus.trans_dist::ReadExReq 163 # Transaction distribution
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.data_through_bus 42176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.reqLayer0.occupancy 929000 # Layer occupancy (ticks)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.membus.respLayer1.occupancy 6308925 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 416.979851 # Cycle average of tags in use
system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.800256 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 284.888559 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 58.382327 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 7.813679 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 0.733163 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 55.504569 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 5.417548 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 2.743977 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.695773 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.004347 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000119 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000847 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.006363 # Average percentage of cache occupancy
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_hits::cpu1.inst 412 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 421 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 421 # number of demand (read+write) hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_hits::cpu1.inst 412 # number of overall hits
system.l2c.overall_hits::cpu1.data 11 # number of overall hits
system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
system.l2c.overall_hits::cpu2.data 5 # number of overall hits
system.l2c.overall_hits::cpu3.inst 421 # number of overall hits
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_hits::total 1443 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_misses::cpu1.inst 16 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
stats: update stats for the changes I pushed re: shared cache occupancy
2010-02-25 19:08:41 +01:00
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_misses::cpu1.inst 16 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_misses::cpu1.inst 16 # number of overall misses
system.l2c.overall_misses::cpu1.data 13 # number of overall misses
system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
system.l2c.overall_misses::cpu2.data 20 # number of overall misses
system.l2c.overall_misses::cpu3.inst 9 # number of overall misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_misses::total 674 # number of overall misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_miss_latency::cpu0.inst 24362500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 5673000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 1205500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 88750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 5263750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 523750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst 570250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 88750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 37776250 # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 7324500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 823750 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1067249 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 882250 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 10097749 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 24362500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 12997500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 1205500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 912500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 5263750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 1590999 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 570250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 971000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 47873999 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 24362500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 12997500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 1205500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 912500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 5263750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 1590999 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 570250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 971000 # number of overall miss cycles
system.l2c.overall_miss_latency::total 47873999 # number of overall miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 18 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_miss_rate::cpu1.inst 0.037383 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.020930 # miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_miss_rate::cpu1.inst 0.037383 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.020930 # miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_miss_rate::cpu1.inst 0.037383 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.020930 # miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 67862.116992 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 76662.162162 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75343.750000 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 88750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69259.868421 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 74821.428571 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 63361.111111 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 88750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 69569.521179 # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77920.212766 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68645.833333 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82096.076923 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 73520.833333 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 77082.053435 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 71029.672107 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 67862.116992 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 77366.071429 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 75343.750000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 70192.307692 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 69259.868421 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 79549.950000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 63361.111111 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 74692.307692 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 71029.672107 # average overall miss latency
stats: update reference outputs now that compatibility is gone Because of the initialization bug, it wasn't consistent anyway.
2009-04-22 19:25:17 +02:00
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
stats: update stats for no_value -> nan Lots of accumulated older changes too.
2012-05-09 20:52:14 +02:00
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.fast_writes 0 # number of fast writes performed
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
system.l2c.cache_copies 0 # number of cache copies performed
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
update stats for preceeding changes
2012-11-02 17:50:06 +01:00
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31 13:49:16 +01:00
system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 73 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::cpu3.inst 6 # number of ReadReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 18 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 73 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::cpu3.inst 6 # number of demand (read+write) MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 73 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::cpu3.inst 6 # number of overall MSHR misses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19789750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4760500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 695750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4180000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 327500 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 76250 # number of ReadReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_miss_latency::total 30342250 # number of ReadReq MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 177515 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 180018 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 777575 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6148500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 672250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 907249 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 731250 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8459249 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 19789750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 10909000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 695750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 748500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 4180000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1343499 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 327500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 807500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 38801499 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 19789750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 10909000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 695750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 748500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 4180000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1343499 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 327500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 807500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 38801499 # number of overall MSHR miss cycles
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for ReadReq accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses
stats: update stats for insts/ops and master id changes
2012-02-12 23:07:43 +01:00
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
all: Update stats for memory per master and total fix.
2012-06-05 07:23:16 +02:00
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
Stats: Updates due to bus changes This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
2012-07-09 18:35:41 +02:00
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.171765 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses
Stats: Update stats for RAS and LRU fixes.
2012-06-29 17:19:03 +02:00
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64331.081081 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69575 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76250 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.ReadReq_avg_mshr_miss_latency::total 57357.750473 # average ReadReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 11094.687500 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
stats: Update the stats to reflect bus and memory changes This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
2013-05-30 18:54:18 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
stats: Update stats for monitor, cache and bus changes This patch removes the sparse histogram total from the CommMonitor stats. It also bumps the stats after the unit fixes in the atomic cache access. Lastly, it updates the stats to match the new port ordering. All numbers are the same, and the only thing that changes is which master corresponds to what port index.
2013-06-27 11:49:51 +02:00
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10231.250000 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65409.574468 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56020.833333 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69788.384615 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 60937.500000 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 64574.419847 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55433.473389 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64934.523810 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69575 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57576.923077 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57260.273973 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 67174.950000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 54583.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 62115.384615 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58790.150000 # average overall mshr miss latency
sparc: update o3 regressions
2011-06-11 04:15:34 +02:00
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19 09:52:36 +02:00
system.toL2Bus.throughput 1691772446 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 393 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 393 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 586 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 135488 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 51968 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 1623982 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2710248 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1462515 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1929494 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1189495 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 1927246 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 1192987 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 1937245 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 1118007 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
system.cpu0.branchPred.lookups 82992 # Number of BP lookups
system.cpu0.branchPred.condPredicted 80791 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 80321 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 78273 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 97.450231 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 221610 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 17247 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 492529 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82992 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 78785 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 161677 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3808 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 13819 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1570 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 493 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 196760 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 2.503197 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.215126 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 35083 17.83% 17.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 80084 40.70% 58.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 76189 38.72% 98.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2456 1.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 196760 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.374496 # Number of branch fetches per cycle
system.cpu0.fetch.rate 2.222503 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 17898 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 15432 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 160701 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 287 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2442 # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts 489694 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 2442 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 18563 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 848 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 13994 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 160355 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 558 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 486837 # Number of instructions processed by rename
system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups
system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 3605 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 155755 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 78714 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 75965 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 75781 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 407125 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 404423 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10748 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 9686 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 196760 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 2.055413 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.097364 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 34065 17.31% 17.31% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 4908 2.49% 19.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 77935 39.61% 59.42% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 77266 39.27% 98.69% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1571 0.80% 99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 648 0.33% 99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 262 0.13% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 89 0.05% 99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 196760 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 57 25.91% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.91% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 51 23.18% 49.09% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 112 50.91% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 170994 42.28% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 155300 38.40% 80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 78129 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 404423 # Type of FU issued
system.cpu0.iq.rate 1.824931 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 220 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000544 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1005954 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 418838 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 402603 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 404643 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 75498 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2188 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1424 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2442 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 391 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 484551 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 155755 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 78714 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 403352 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 154964 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1071 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 76515 # number of nop insts executed
system.cpu0.iew.exec_refs 232993 # number of memory reference insts executed
system.cpu0.iew.exec_branches 80132 # Number of branches executed
system.cpu0.iew.exec_stores 78029 # Number of stores executed
system.cpu0.iew.exec_rate 1.820098 # Inst execution rate
system.cpu0.iew.wb_sent 402944 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 402603 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 238549 # num instructions producing a value
system.cpu0.iew.wb_consumers 241004 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 1.816719 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.989813 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 12240 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 194318 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 2.430470 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 2.136197 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 34493 17.75% 17.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 79895 41.12% 58.87% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2401 1.24% 60.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 689 0.35% 60.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 530 0.27% 60.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 75316 38.76% 99.49% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 445 0.23% 99.72% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 242 0.12% 99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 307 0.16% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 194318 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 472284 # Number of instructions committed
system.cpu0.commit.committedOps 472284 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 230857 # Number of memory references committed
system.cpu0.commit.loads 153567 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
system.cpu0.commit.branches 79177 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 318286 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.bw_lim_events 307 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 677374 # The number of ROB reads
system.cpu0.rob.rob_writes 971507 # The number of ROB writes
system.cpu0.timesIdled 326 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 24850 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 396291 # Number of Instructions Simulated
system.cpu0.committedOps 396291 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 396291 # Number of Instructions Simulated
system.cpu0.cpi 0.559210 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.559210 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.788236 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.788236 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 721592 # number of integer regfile reads
system.cpu0.int_regfile_writes 325227 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 234817 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.tags.replacements 297 # number of replacements
system.cpu0.icache.tags.tagsinuse 241.148232 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.148232 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470993 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.470993 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits
system.cpu0.icache.overall_hits::total 5079 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
system.cpu0.icache.overall_misses::total 756 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35147245 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 35147245 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 35147245 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 35147245 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 35147245 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 35147245 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46491.064815 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 46491.064815 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 46491.064815 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46491.064815 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 46491.064815 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27250252 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 27250252 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27250252 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 27250252 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27250252 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 27250252 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46343.965986 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46343.965986 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 46343.965986 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 141.869283 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 155614 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 915.376471 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.869283 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277088 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.277088 # Average percentage of cache occupancy
system.cpu0.dcache.ReadReq_hits::cpu0.data 78995 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 78995 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 76703 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 76703 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 155698 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 155698 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 155698 # number of overall hits
system.cpu0.dcache.overall_hits::total 155698 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 410 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 410 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 955 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 955 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 955 # number of overall misses
system.cpu0.dcache.overall_misses::total 955 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13319205 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 13319205 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35150505 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 35150505 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 418750 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 418750 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 48469710 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 48469710 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 48469710 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 48469710 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 79405 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 79405 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77248 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77248 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 156653 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 156653 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 156653 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 156653 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005163 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.005163 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007055 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006096 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.006096 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006096 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.006096 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32485.865854 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 32485.865854 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64496.339450 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 64496.339450 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19940.476190 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19940.476190 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 50753.623037 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50753.623037 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 50753.623037 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 503 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.952381 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 223 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 593 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 593 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 593 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 593 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 187 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6285007 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6285007 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7788228 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7788228 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 375250 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 375250 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14073235 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 14073235 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14073235 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 14073235 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002355 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002265 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002265 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002311 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002311 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002311 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33609.663102 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33609.663102 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44504.160000 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44504.160000 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17869.047619 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17869.047619 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38876.339779 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38876.339779 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 43495 # Number of BP lookups
system.cpu1.branchPred.condPredicted 40766 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 37360 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 36580 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 97.912206 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 665 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.numCycles 177681 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 34028 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 233746 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 43495 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 37245 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 88254 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3762 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 42089 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines 25656 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 175306 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.333360 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.985884 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 87052 49.66% 49.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 46435 26.49% 76.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 9084 5.18% 81.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3194 1.82% 83.15% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 686 0.39% 83.54% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 23635 13.48% 97.02% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1173 0.67% 97.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 772 0.44% 98.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3275 1.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 175306 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.244793 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.315537 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 41969 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 35783 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 79597 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 7812 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2406 # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts 230200 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 2406 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 42677 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 23059 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11946 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 72053 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 15426 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 227940 # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups
system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 18203 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 60713 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 26873 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 30033 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 21821 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 184781 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 9329 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 189617 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10957 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 10934 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 690 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 175306 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.081634 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.264768 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 84668 48.30% 48.30% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 30997 17.68% 65.98% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 27119 15.47% 81.45% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 27768 15.84% 97.29% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3226 1.84% 99.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1160 0.66% 99.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 175306 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 42 15.91% 20.45% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 95616 50.43% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.43% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 67820 35.77% 86.19% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 26181 13.81% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 189617 # Type of FU issued
system.cpu1.iq.rate 1.067177 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001392 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 554912 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 205110 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 187814 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 189881 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 21562 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2474 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 2406 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 736 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 43 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 225068 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 373 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 60713 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 26873 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1076 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 939 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1392 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 188449 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 59619 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1168 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 30958 # number of nop insts executed
system.cpu1.iew.exec_refs 85720 # number of memory reference insts executed
system.cpu1.iew.exec_branches 40129 # Number of branches executed
system.cpu1.iew.exec_stores 26101 # Number of stores executed
system.cpu1.iew.exec_rate 1.060603 # Inst execution rate
system.cpu1.iew.wb_sent 188127 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 187814 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 102456 # num instructions producing a value
system.cpu1.iew.wb_consumers 107134 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 1.057029 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.956335 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 12618 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 8639 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 165161 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.286212 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.860966 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 85256 51.62% 51.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 38272 23.17% 74.79% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6084 3.68% 78.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 9527 5.77% 84.24% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1571 0.95% 85.20% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 22201 13.44% 98.64% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 436 0.26% 98.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 808 0.49% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 165161 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 212432 # Number of instructions committed
system.cpu1.commit.committedOps 212432 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 83673 # Number of memory references committed
system.cpu1.commit.loads 58239 # Number of loads committed
system.cpu1.commit.membars 7917 # Number of memory barriers committed
system.cpu1.commit.branches 39308 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 145097 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.bw_lim_events 808 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 388816 # The number of ROB reads
system.cpu1.rob.rob_writes 452512 # The number of ROB writes
system.cpu1.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 2375 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 43927 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 174425 # Number of Instructions Simulated
system.cpu1.committedOps 174425 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 174425 # Number of Instructions Simulated
system.cpu1.cpi 1.018667 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.018667 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.981675 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.981675 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 315718 # number of integer regfile reads
system.cpu1.int_regfile_writes 148477 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 87269 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.tags.replacements 318 # number of replacements
system.cpu1.icache.tags.tagsinuse 79.958659 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 25178 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 58.827103 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 79.958659 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.156169 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.156169 # Average percentage of cache occupancy
system.cpu1.icache.ReadReq_hits::cpu1.inst 25178 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 25178 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 25178 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 25178 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 25178 # number of overall hits
system.cpu1.icache.overall_hits::total 25178 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 478 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 478 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 478 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 478 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 478 # number of overall misses
system.cpu1.icache.overall_misses::total 478 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7224243 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 7224243 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 7224243 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 7224243 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 7224243 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 7224243 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 25656 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 25656 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 25656 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 25656 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 25656 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 25656 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018631 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.018631 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018631 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.018631 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018631 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.018631 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15113.479079 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15113.479079 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15113.479079 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15113.479079 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15113.479079 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 50 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 50 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 50 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5769006 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5769006 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5769006 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5769006 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5769006 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5769006 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016682 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.016682 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016682 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.016682 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13478.985981 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13478.985981 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13478.985981 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 24.742100 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 31558 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 1088.206897 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.742100 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.048324 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.048324 # Average percentage of cache occupancy
system.cpu1.dcache.ReadReq_hits::cpu1.data 37722 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 37722 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 25226 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 25226 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 62948 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 62948 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 62948 # number of overall hits
system.cpu1.dcache.overall_hits::total 62948 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 319 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 319 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 451 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 451 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 451 # number of overall misses
system.cpu1.dcache.overall_misses::total 451 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3919891 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3919891 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2617261 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 2617261 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 548504 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 548504 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6537152 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6537152 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6537152 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6537152 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 38041 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 38041 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 25358 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 25358 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 76 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 63399 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 63399 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 63399 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 63399 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008386 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.008386 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.005205 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.005205 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.789474 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.789474 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007114 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.007114 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007114 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.007114 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12288.059561 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12288.059561 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19827.734848 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 19827.734848 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9141.733333 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 9141.733333 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14494.793792 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14494.793792 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14494.793792 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 154 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 186 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 186 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 186 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 186 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 165 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 100 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 100 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1138770 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1138770 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1290739 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1290739 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 428496 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 428496 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2429509 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2429509 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2429509 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2429509 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004337 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004337 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003944 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003944 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.789474 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.789474 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.004180 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004180 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.004180 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6901.636364 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6901.636364 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12907.390000 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12907.390000 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7141.600000 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7141.600000 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9167.958491 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9167.958491 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.branchPred.lookups 51236 # Number of BP lookups
system.cpu2.branchPred.condPredicted 48519 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 1308 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 45052 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 44357 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 98.457338 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 684 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.numCycles 177316 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 28846 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 286216 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 51236 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 45041 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 100902 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 31210 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 19767 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 171898 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.665034 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.139289 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 70996 41.30% 41.30% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 51338 29.87% 71.17% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 6125 3.56% 74.73% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3190 1.86% 76.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 695 0.40% 76.99% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 34353 19.98% 96.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1162 0.68% 97.65% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 771 0.45% 98.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3268 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 171898 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.288953 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.614158 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 33770 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 27924 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 94988 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5055 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 2422 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 282690 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 2422 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 34480 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 14885 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 90190 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 9902 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 280450 # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups
system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 1237 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 12513 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 79191 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 37564 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 37796 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 32512 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 232563 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 6341 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 234561 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 11040 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 10888 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 602 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 171898 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.364536 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.313534 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 68441 39.81% 39.81% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 22472 13.07% 52.89% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 37788 21.98% 74.87% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 38389 22.33% 97.20% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 3254 1.89% 99.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1164 0.68% 99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 277 0.16% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 171898 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 17 6.14% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 50 18.05% 24.19% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 210 75.81% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 114217 48.69% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.69% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 83468 35.58% 84.28% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 36876 15.72% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 234561 # Type of FU issued
system.cpu2.iq.rate 1.322842 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 277 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 641380 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 249989 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 232740 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 234838 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 32248 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 1465 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 851 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 277610 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 79191 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 37564 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 1068 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 970 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1436 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 233403 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 78158 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 1158 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 38706 # number of nop insts executed
system.cpu2.iew.exec_refs 114950 # number of memory reference insts executed
system.cpu2.iew.exec_branches 47927 # Number of branches executed
system.cpu2.iew.exec_stores 36792 # Number of stores executed
system.cpu2.iew.exec_rate 1.316311 # Inst execution rate
system.cpu2.iew.wb_sent 233070 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 232740 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 131730 # num instructions producing a value
system.cpu2.iew.wb_consumers 136434 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.312572 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.965522 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 12692 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 5739 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1308 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 161737 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.637943 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.020354 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 66243 40.96% 40.96% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 46082 28.49% 69.45% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 6100 3.77% 73.22% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 6659 4.12% 77.34% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1556 0.96% 78.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 32794 20.28% 98.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 480 0.30% 98.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 161737 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 264916 # Number of instructions committed
system.cpu2.commit.committedOps 264916 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 112806 # Number of memory references committed
system.cpu2.commit.loads 76707 # Number of loads committed
system.cpu2.commit.membars 5024 # Number of memory barriers committed
system.cpu2.commit.branches 47088 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 182014 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 437936 # The number of ROB reads
system.cpu2.rob.rob_writes 557643 # The number of ROB writes
system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 5418 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 44292 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 222015 # Number of Instructions Simulated
system.cpu2.committedOps 222015 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 222015 # Number of Instructions Simulated
system.cpu2.cpi 0.798667 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.798667 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.252087 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.252087 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 403571 # number of integer regfile reads
system.cpu2.int_regfile_writes 188531 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 116514 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.tags.replacements 317 # number of replacements
system.cpu2.icache.tags.tagsinuse 82.351710 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 19274 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 45.350588 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.351710 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160843 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total 0.160843 # Average percentage of cache occupancy
system.cpu2.icache.ReadReq_hits::cpu2.inst 19274 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 19274 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 19274 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 19274 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 19274 # number of overall hits
system.cpu2.icache.overall_hits::total 19274 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 493 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 493 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 493 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 493 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 493 # number of overall misses
system.cpu2.icache.overall_misses::total 493 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521742 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 11521742 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 11521742 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 11521742 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 11521742 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 11521742 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 19767 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 19767 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 19767 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 19767 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 19767 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 19767 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024941 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.024941 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024941 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.024941 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024941 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.024941 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23370.673428 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23370.673428 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23370.673428 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23370.673428 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23370.673428 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9201754 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 9201754 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9201754 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 9201754 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9201754 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 9201754 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021500 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.021500 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021500 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.021500 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21651.185882 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21651.185882 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21651.185882 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 26.191522 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 42135 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1504.821429 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.191522 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051155 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total 0.051155 # Average percentage of cache occupancy
system.cpu2.dcache.ReadReq_hits::cpu2.data 45549 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 45549 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 35887 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 35887 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 81436 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 81436 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 81436 # number of overall hits
system.cpu2.dcache.overall_hits::total 81436 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 344 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 344 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 143 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 143 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 487 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 487 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 487 # number of overall misses
system.cpu2.dcache.overall_misses::total 487 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5599802 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 5599802 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3105260 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 3105260 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 575007 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 575007 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 8705062 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 8705062 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 8705062 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 8705062 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 45893 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 45893 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 36030 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 36030 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 81923 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 81923 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 81923 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 81923 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.007496 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.007496 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003969 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.003969 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.826087 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005945 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.005945 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005945 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.005945 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16278.494186 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 16278.494186 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21715.104895 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 21715.104895 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10087.842105 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 10087.842105 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 17874.870637 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17874.870637 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 17874.870637 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 182 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data 216 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data 216 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total 216 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526780 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526780 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1514240 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1514240 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 460993 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 460993 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3041020 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 3041020 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3041020 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 3041020 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003530 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003025 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003025 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.826087 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003308 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003308 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003308 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9424.567901 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9424.567901 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13892.110092 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13892.110092 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8087.596491 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8087.596491 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11221.476015 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11221.476015 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.branchPred.lookups 56317 # Number of BP lookups
system.cpu3.branchPred.condPredicted 53592 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 1257 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 50318 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 49441 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 98.257085 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 649 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.numCycles 176970 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles 26467 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 318235 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 56317 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 50090 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 110248 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 3629 # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles 28039 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 7739 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 790 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 18199 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 258 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples 175582 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.812458 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.180606 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 65334 37.21% 37.21% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 55610 31.67% 68.88% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 5389 3.07% 71.95% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3177 1.81% 73.76% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 669 0.38% 74.14% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 40119 22.85% 96.99% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1237 0.70% 97.70% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 753 0.43% 98.12% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 3294 1.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 175582 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.318229 # Number of branch fetches per cycle
system.cpu3.fetch.rate 1.798243 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 31057 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 25106 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 104911 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 4475 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2294 # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts 314540 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 2294 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 31713 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 12844 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 11527 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 100723 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 8742 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 312369 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups
system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1202 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 11332 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 90084 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 43367 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 42837 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 38342 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 260031 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 5573 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 261645 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 10424 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 10297 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 175582 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 1.490158 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.307816 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 62519 35.61% 35.61% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 20435 11.64% 47.25% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 43580 24.82% 72.07% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 44218 25.18% 97.25% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3288 1.87% 99.12% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1176 0.67% 99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 175582 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 17 6.25% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.25% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 45 16.54% 22.79% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 210 77.21% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 125105 47.81% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.81% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 93850 35.87% 83.68% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 42690 16.32% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 261645 # Type of FU issued
system.cpu3.iq.rate 1.478471 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 272 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001040 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 699206 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 276071 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 259793 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 261917 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 38112 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 2309 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 1414 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 2294 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 580 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 309373 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 90084 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 43367 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 904 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1369 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 260458 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 89199 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 43769 # number of nop insts executed
system.cpu3.iew.exec_refs 131812 # number of memory reference insts executed
system.cpu3.iew.exec_branches 53091 # Number of branches executed
system.cpu3.iew.exec_stores 42613 # Number of stores executed
system.cpu3.iew.exec_rate 1.471764 # Inst execution rate
system.cpu3.iew.wb_sent 260118 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 259793 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 148532 # num instructions producing a value
system.cpu3.iew.wb_consumers 153197 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate 1.468006 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.969549 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts 11915 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 5075 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1257 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 165549 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 1.796677 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 2.064793 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 59727 36.08% 36.08% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 51190 30.92% 67.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 6085 3.68% 70.68% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 6030 3.64% 74.32% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1572 0.95% 75.27% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 38600 23.32% 98.58% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 530 0.32% 98.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 1000 0.60% 99.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 815 0.49% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 165549 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 297438 # Number of instructions committed
system.cpu3.commit.committedOps 297438 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 129728 # Number of memory references committed
system.cpu3.commit.loads 87775 # Number of loads committed
system.cpu3.commit.membars 4366 # Number of memory barriers committed
system.cpu3.commit.branches 52284 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 204138 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.bw_lim_events 815 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads 473500 # The number of ROB reads
system.cpu3.rob.rob_writes 621006 # The number of ROB writes
system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1388 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 44638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 249993 # Number of Instructions Simulated
system.cpu3.committedOps 249993 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 249993 # Number of Instructions Simulated
system.cpu3.cpi 0.707900 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.707900 # CPI: Total CPI of All Threads
system.cpu3.ipc 1.412629 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 1.412629 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 453881 # number of integer regfile reads
system.cpu3.int_regfile_writes 211087 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 133368 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.tags.replacements 319 # number of replacements
system.cpu3.icache.tags.tagsinuse 77.348761 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 17724 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 41.218605 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.348761 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151072 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total 0.151072 # Average percentage of cache occupancy
system.cpu3.icache.ReadReq_hits::cpu3.inst 17724 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 17724 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 17724 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 17724 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 17724 # number of overall hits
system.cpu3.icache.overall_hits::total 17724 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
system.cpu3.icache.overall_misses::total 475 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6467995 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 6467995 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 6467995 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 6467995 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 6467995 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 6467995 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 18199 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 18199 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 18199 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 18199 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 18199 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 18199 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026100 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.026100 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026100 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.026100 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026100 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.026100 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13616.831579 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13616.831579 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13616.831579 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13616.831579 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13616.831579 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5219755 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5219755 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5219755 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 5219755 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5219755 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 5219755 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023628 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.023628 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023628 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.023628 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12138.965116 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12138.965116 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12138.965116 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 23.659946 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 47957 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1712.750000 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.659946 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.046211 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total 0.046211 # Average percentage of cache occupancy
system.cpu3.dcache.ReadReq_hits::cpu3.data 50723 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 50723 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 41752 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 41752 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 92475 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 92475 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 92475 # number of overall hits
system.cpu3.dcache.overall_hits::total 92475 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 346 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 346 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 51 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 51 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 484 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 484 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 484 # number of overall misses
system.cpu3.dcache.overall_misses::total 484 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4449419 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 4449419 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2879011 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 2879011 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 478509 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 478509 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 7328430 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 7328430 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 7328430 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 7328430 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 51069 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 51069 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 41890 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 41890 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 63 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 92959 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 92959 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 92959 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 92959 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.006775 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.006775 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003294 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.003294 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.809524 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.809524 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005207 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.005207 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005207 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.005207 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12859.592486 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 12859.592486 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20862.398551 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 20862.398551 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9382.529412 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 9382.529412 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 15141.384298 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 15141.384298 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 15141.384298 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 195 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data 227 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total 227 # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data 227 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total 227 # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data 257 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 257 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1003763 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1003763 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1322239 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1322239 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 376491 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 376491 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2326002 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 2326002 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2326002 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 2326002 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002957 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002957 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002530 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002530 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.809524 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.809524 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002765 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002765 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002765 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6647.437086 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6647.437086 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12473.952830 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12473.952830 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7382.176471 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7382.176471 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9050.591440 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9050.591440 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs.
2009-04-21 17:37:50 +02:00
---------- End Simulation Statistics ----------
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