gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.629535                       # Number of seconds simulated
sim_ticks                                629535413500                       # Number of ticks simulated
final_tick                               629535413500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 106173                       # Simulator instruction rate (inst/s)
host_op_rate                                   144593                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               48281629                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278772                       # Number of bytes of host memory used
host_seconds                                 13038.82                       # Real time elapsed on the host
sim_insts                                  1384370590                       # Number of instructions simulated
sim_ops                                    1885325342                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            155136                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          30242496                       # Number of bytes read from this memory
system.physmem.bytes_read::total             30397632                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       155136                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          155136                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2424                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             472539                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                474963                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               246429                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             48039388                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                48285817                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          246429                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             246429                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           6719673                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                6719673                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           6719673                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              246429                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            48039388                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               55005490                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        474963                       # Number of read requests accepted
system.physmem.writeReqs                        66098                       # Number of write requests accepted
system.physmem.readBursts                      474963                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 30390400                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7232                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4229888                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  30397632                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      113                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs           4262                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               29871                       # Per bank write bursts
system.physmem.perBankRdBursts::1               29675                       # Per bank write bursts
system.physmem.perBankRdBursts::2               29749                       # Per bank write bursts
system.physmem.perBankRdBursts::3               29712                       # Per bank write bursts
system.physmem.perBankRdBursts::4               29816                       # Per bank write bursts
system.physmem.perBankRdBursts::5               29834                       # Per bank write bursts
system.physmem.perBankRdBursts::6               29642                       # Per bank write bursts
system.physmem.perBankRdBursts::7               29444                       # Per bank write bursts
system.physmem.perBankRdBursts::8               29480                       # Per bank write bursts
system.physmem.perBankRdBursts::9               29489                       # Per bank write bursts
system.physmem.perBankRdBursts::10              29547                       # Per bank write bursts
system.physmem.perBankRdBursts::11              29649                       # Per bank write bursts
system.physmem.perBankRdBursts::12              29701                       # Per bank write bursts
system.physmem.perBankRdBursts::13              29813                       # Per bank write bursts
system.physmem.perBankRdBursts::14              29629                       # Per bank write bursts
system.physmem.perBankRdBursts::15              29799                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4174                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4102                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4138                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4148                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4226                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4093                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4095                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4140                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    629535350500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  474963                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    407876                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     66617                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       275                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        64                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        16                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3004                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     3005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     3006                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       190822                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      181.419082                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     122.160667                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     377.205430                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64             76972     40.34%     40.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128            49989     26.20%     66.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192            37639     19.72%     86.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256            19482     10.21%     96.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320              187      0.10%     96.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384              252      0.13%     96.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448               85      0.04%     96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512              218      0.11%     96.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576               85      0.04%     96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640              231      0.12%     97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704               52      0.03%     97.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768              225      0.12%     97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832               65      0.03%     97.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896              188      0.10%     97.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960               60      0.03%     97.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024             181      0.09%     97.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088              44      0.02%     97.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152             201      0.11%     97.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216              67      0.04%     97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280             181      0.09%     97.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344              66      0.03%     97.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408            3167      1.66%     99.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472              20      0.01%     99.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536              13      0.01%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600              12      0.01%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664              12      0.01%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728              13      0.01%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792              17      0.01%     99.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856              15      0.01%     99.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920              15      0.01%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984              19      0.01%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048              10      0.01%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112              18      0.01%     99.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176              13      0.01%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240              11      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304              14      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368              14      0.01%     99.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432              15      0.01%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496              21      0.01%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560              12      0.01%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624              17      0.01%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688              16      0.01%     99.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752              16      0.01%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816              13      0.01%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880              12      0.01%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944              12      0.01%     99.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008              14      0.01%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072               9      0.00%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136              19      0.01%     99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200              10      0.01%     99.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264              20      0.01%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328              10      0.01%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392              16      0.01%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456              12      0.01%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520              21      0.01%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584              13      0.01%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648              16      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712              15      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776              18      0.01%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840               7      0.00%     99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904              15      0.01%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968              17      0.01%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032              14      0.01%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096              12      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160              28      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224              16      0.01%     99.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288              14      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352               7      0.00%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416              17      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480              11      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544              14      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608              12      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672              19      0.01%     99.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736              10      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800              13      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864               9      0.00%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928              17      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992               8      0.00%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056              17      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120               7      0.00%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184               9      0.00%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248               9      0.00%     99.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312              13      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376              11      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440              14      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504              12      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568              15      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632              15      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696              31      0.02%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760              73      0.04%     99.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824              59      0.03%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888               4      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952               3      0.00%     99.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016               6      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080               8      0.00%     99.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144              53      0.03%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208               4      0.00%     99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272              19      0.01%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         190822                       # Bytes accessed per row activation
system.physmem.totQLat                     3804806750                       # Total ticks spent queuing
system.physmem.totMemAccLat               15248020500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   2374250000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  9068963750                       # Total ticks spent accessing banks
system.physmem.avgQLat                        8012.65                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    19098.59                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32111.24                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          48.27                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           6.72                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       48.29                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        6.72                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.43                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.05                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.02                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         6.84                       # Average write queue length when enqueuing
system.physmem.readRowHits                     300749                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     49371                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   63.34                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.69                       # Row buffer hit rate for writes
system.physmem.avgGap                      1163520.10                       # Average gap between requests
system.physmem.pageHitRate                      64.72                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              24.30                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                     55005389                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq              408886                       # Transaction distribution
system.membus.trans_dist::ReadResp             408885                       # Transaction distribution
system.membus.trans_dist::Writeback             66098                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4262                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            4262                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66077                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66077                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1024547                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                1024547                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     34627840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            34627840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               34627840                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy          1215457500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         4442862738                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.7                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups               438247722                       # Number of BP lookups
system.cpu.branchPred.condPredicted         350864471                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          30620817                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            248480162                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               229339460                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             92.296889                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                52915671                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect            2805331                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1411                       # Number of system calls
system.cpu.numCycles                       1259070828                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          354141020                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                     2279761292                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   438247722                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          282255131                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     601258233                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles               157188182                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles              134732573                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  615                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles         11340                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles          159                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 334734643                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes              11658358                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples         1216659303                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.575913                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.175897                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                615445842     50.58%     50.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 42369042      3.48%     54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 95794203      7.87%     61.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 57788183      4.75%     66.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                 71908380      5.91%     72.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                 44699403      3.67%     76.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                 31096366      2.56%     78.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                 31485891      2.59%     81.42% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                226071993     18.58%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1216659303                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.348072                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.810670                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                405371770                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             106745247                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 560687148                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              17351012                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles              126504126                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             44828011                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                 11498                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             3022924000                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                 26519                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles              126504126                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                441422956                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                38086039                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         457739                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 539750713                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              70437730                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             2941757147                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                    93                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                4808697                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents              54385461                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              740                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          2930215043                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups           14237570542                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups      12151139431                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups          84006834                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps            1993140090                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                937074953                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20556                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18072                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 179296103                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            971747851                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           485687926                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads          36754298                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores         38315968                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 2792666387                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               27976                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                2435151733                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued          13267287                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined       894813074                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined   2341267254                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           6592                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1216659303                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.001507                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.873340                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           380682463     31.29%     31.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           183043299     15.04%     46.33% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           204121257     16.78%     63.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3           169552429     13.94%     77.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4           132904836     10.92%     87.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5            92976040      7.64%     95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6            37964484      3.12%     98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7            12393775      1.02%     99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8             3020720      0.25%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1216659303                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  714585      0.82%      0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                  24381      0.03%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               55158409     62.92%     63.76% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              31764976     36.24%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu            1104245990     45.35%     45.35% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult             11223912      0.46%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   3      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.81% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd         1375289      0.06%     45.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.86% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp         6876479      0.28%     46.15% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt         5502438      0.23%     46.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               1      0.00%     46.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc       23399832      0.96%     47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            840060400     34.50%     81.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           442467389     18.17%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             2435151733                       # Type of FU issued
system.cpu.iq.rate                           1.934086                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    87662351                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.035999                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         6065394864                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        3604907210                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   2250139818                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads           122497543                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes           82667139                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses     56433103                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             2459502901                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                63311183                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads         84462690                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads    340360670                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         9529                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation      1430281                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores    208692629                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads            5                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           365                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles              126504126                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                16045638                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               1563592                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          2792706809                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts           1386483                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             971747851                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            485687926                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              17990                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                1559989                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  2525                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents        1430281                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect       32383306                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      1525297                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts             33908603                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            2359934527                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             794158761                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          75217206                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         12446                       # number of nop insts executed
system.cpu.iew.exec_refs                   1217435347                       # number of memory reference insts executed
system.cpu.iew.exec_branches                319532182                       # Number of branches executed
system.cpu.iew.exec_stores                  423276586                       # Number of stores executed
system.cpu.iew.exec_rate                     1.874346                       # Inst execution rate
system.cpu.iew.wb_sent                     2332318600                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    2306572921                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                1349155649                       # num instructions producing a value
system.cpu.iew.wb_consumers                2527421878                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.831964                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.533807                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts       907370579                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           21384                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts          30609580                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1090155177                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.729420                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.397089                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0    449868742     41.27%     41.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    288583282     26.47%     67.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     95106533      8.72%     76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     70222065      6.44%     82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     46473839      4.26%     87.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     22181225      2.03%     89.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6     15848509      1.45%     90.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7     10986576      1.01%     91.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     90884406      8.34%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1090155177                       # Number of insts commited each cycle
system.cpu.commit.committedInsts           1384381606                       # Number of instructions committed
system.cpu.commit.committedOps             1885336358                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      908382478                       # Number of memory references committed
system.cpu.commit.loads                     631387181                       # Number of loads committed
system.cpu.commit.membars                        9986                       # Number of memory barriers committed
system.cpu.commit.branches                  298259106                       # Number of branches committed
system.cpu.commit.fp_insts                   52289415                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                1653698867                       # Number of committed integer instructions.
system.cpu.commit.function_calls             41577833                       # Number of function calls committed.
system.cpu.commit.bw_lim_events              90884406                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                   3791959363                       # The number of ROB reads
system.cpu.rob.rob_writes                  5711929117                       # The number of ROB writes
system.cpu.timesIdled                          353184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        42411525                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                  1384370590                       # Number of Instructions Simulated
system.cpu.committedOps                    1885325342                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total            1384370590                       # Number of Instructions Simulated
system.cpu.cpi                               0.909490                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.909490                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.099518                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.099518                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads              11767673388                       # number of integer regfile reads
system.cpu.int_regfile_writes              2220511965                       # number of integer regfile writes
system.cpu.fp_regfile_reads                  68796181                       # number of floating regfile reads
system.cpu.fp_regfile_writes                 49544953                       # number of floating regfile writes
system.cpu.misc_regfile_reads              1678583418                       # number of misc regfile reads
system.cpu.misc_regfile_writes               13772902                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               169029894                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq        1493831                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp       1493830                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback        96313                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         4265                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         4265                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        72518                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        72518                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54300                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3178976                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           3233276                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1601152                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    104536256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total      106137408                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus         106137408                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus       272896                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      929776999                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      44342246                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    2368551488                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
system.cpu.icache.tags.replacements             23332                       # number of replacements
system.cpu.icache.tags.tagsinuse          1641.273486                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           334698554                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             25017                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs          13378.844546                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1641.273486                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.801403                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.801403                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1685                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           65                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1551                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.822754                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         669498564                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        669498564                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    334702534                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       334702534                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     334702534                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        334702534                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    334702534                       # number of overall hits
system.cpu.icache.overall_hits::total       334702534                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        32107                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         32107                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        32107                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          32107                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        32107                       # number of overall misses
system.cpu.icache.overall_misses::total         32107                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    545585992                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    545585992                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    545585992                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    545585992                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    545585992                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    545585992                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    334734641                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    334734641                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    334734641                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    334734641                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    334734641                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    334734641                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000096                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000096                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000096                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000096                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000096                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000096                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16992.742766                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16992.742766                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         2092                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                38                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    55.052632                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2825                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         2825                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         2825                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         2825                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         2825                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         2825                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        29282                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        29282                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        29282                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        29282                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        29282                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        29282                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    435718750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    435718750                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    435718750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    435718750                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    435718750                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    435718750                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           442179                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32678.084712                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1110777                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           474927                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             2.338837                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1317.536898                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    51.699719                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.040208                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001578                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.955470                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.997256                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32748                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          154                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          507                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5020                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26968                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999390                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13848752                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13848752                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        22592                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1058063                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1080655                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks        96313                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total        96313                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            3                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            3                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         6441                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         6441                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        22592                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1064504                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1087096                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        22592                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1064504                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1087096                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2426                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       406486                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       408912                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         4262                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         4262                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        66077                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66077                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2426                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       472563                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        474989                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2426                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       472563                       # number of overall misses
system.cpu.l2cache.overall_misses::total       474989                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    176218750                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  30746506500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  30922725250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4757394750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4757394750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    176218750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  35503901250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  35680120000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    176218750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  35503901250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  35680120000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        25018                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1464549                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1489567                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks        96313                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total        96313                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4265                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         4265                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        72518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        72518                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        25018                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1537067                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      1562085                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        25018                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1537067                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      1562085                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.096970                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.277550                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.274517                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999297                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.999297                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911181                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.911181                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.096970                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.307445                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.304074                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096970                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.307445                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.304074                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72637.572135                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75639.767421                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75621.955947                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71997.741272                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71997.741272                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72637.572135                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75130.514344                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75117.781675                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72637.572135                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75130.514344                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75117.781675                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           24                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           26                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           24                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           26                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           24                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           26                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2424                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       406462                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       408886                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4262                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         4262                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66077                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66077                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2424                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       472539                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       474963                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2424                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       472539                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       474963                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    145637750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  25686438000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  25832075750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     42624262                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     42624262                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3924978750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3924978750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    145637750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  29611416750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  29757054500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    145637750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  29611416750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  29757054500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.277534                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.274500                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999297                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.999297                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911181                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911181                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307429                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.304057                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096890                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307429                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.304057                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63195.176917                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63176.718572                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements           1532970                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4094.376677                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           971409331                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1537066                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            631.989343                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         400505250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4094.376677                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999604                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999604                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          977                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         2409                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4          402                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1949922120                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1949922120                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    695282746                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       695282746                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    276093049                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      276093049                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        10000                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        10000                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     971375795                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        971375795                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    971375795                       # number of overall hits
system.cpu.dcache.overall_hits::total       971375795                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1954115                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1954115                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       842629                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       842629                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      2796744                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2796744                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2796744                       # number of overall misses
system.cpu.dcache.overall_misses::total       2796744                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  80415220057                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  80415220057                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  58619966916                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  58619966916                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       211750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       211750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 139035186973                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 139035186973                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 139035186973                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 139035186973                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    697236861                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    697236861                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10003                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        10003                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    974172539                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    974172539                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    974172539                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    974172539                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002803                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002803                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003043                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003043                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000300                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002871                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002871                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002871                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002871                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 49713.233307                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 49713.233307                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         2265                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets          939                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                52                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              89                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    43.557692                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    10.550562                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        96313                       # number of writebacks
system.cpu.dcache.writebacks::total             96313                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       489564                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       489564                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       765848                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       765848                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1255412                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1255412                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1255412                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1255412                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1464551                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1464551                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        76781                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        76781                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      1541332                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      1541332                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      1541332                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      1541332                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  42792151524                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  42792151524                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4993494488                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   4993494488                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  47785646012                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  47785646012                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  47785646012                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  47785646012                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002101                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002101                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000277                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001582                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001582                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001582                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001582                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------