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gem5/src/arch/arm
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Nilay Vaish fc57ae6401 x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 
The changes made by the changeset 270c9a75e91f do not work well with switching
of cpus. The problem is that decoder for the old thread context holds state
that is not taken over by the new decoder.

This patch adds a takeOverFrom() function to Decoder class in each ISA. Except
for x86, functions in other ISAs are blank. For x86, the function copies state
from the old decoder to the new decoder.
2013-01-22 00:10:10 -06:00
..
insts arm: set movret_uop as conditional or unconditional control 2012-12-12 09:50:16 -06:00
isa arm: set uopSet_uop as conditional or unconditional control 2012-12-12 09:50:33 -06:00
linux arm: add access syscall for ARM SE mode 2013-01-08 08:54:07 -05:00
ArmInterrupts.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmISA.py arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
ArmNativeTrace.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ArmSystem.py arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
ArmTLB.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
decoder.cc Decoder: Remove the thread context get/set from the decoder. 2013-01-04 19:00:45 -06:00
decoder.hh x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch 2013-01-22 00:10:10 -06:00
faults.cc Implement Ali's review feedback. 2012-01-29 02:04:34 -08:00
faults.hh SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. 2011-11-02 01:25:15 -07:00
interrupts.cc ARM: Implement ARM CPU interrupts 2010-06-02 12:58:16 -05:00
interrupts.hh Fix bugs due to interaction between SEV instructions and O3 pipeline 2011-08-19 15:08:07 -05:00
intregs.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
isa.cc arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
isa.hh x86: Changes to decoder, corrects 9376 2013-01-12 22:09:48 -06:00
isa_traits.hh ISA: generic Linux thread info support 2012-11-02 11:32:00 -05:00
kernel_stats.hh Make commenting on close namespace brackets consistent. 2011-01-03 14:35:43 -08:00
locked_mem.hh o3: Fix issue with LLSC ordering and speculation 2013-01-07 13:05:33 -05:00
microcode_rom.hh arm: include missing file for arm 2009-04-21 15:40:26 -07:00
miscregs.cc gem5: Fix a number of incorrect case statements 2012-05-10 18:04:26 -05:00
miscregs.hh arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
mmapped_ipr.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
nativetrace.cc gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
nativetrace.hh ARM: Add vfpv3 support to native trace. 2011-05-04 20:38:26 -05:00
pagetable.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
process.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
process.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
registers.hh O3: Clean up the O3 structures and try to pack them a bit better. 2012-06-05 01:23:09 -04:00
remote_gdb.cc ARM: Keep a copy of the fpscr len and stride fields in the decoder. 2013-01-04 18:09:35 -06:00
remote_gdb.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SConscript arch: Make the ISA class inherit from SimObject 2013-01-07 13:05:35 -05:00
SConsopts arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
stacktrace.cc ARM: implement the ProcessInfo methods 2012-06-11 11:07:41 -04:00
stacktrace.hh trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
system.cc arm: Make ID registers ISA parameters 2013-01-07 13:05:35 -05:00
system.hh ARM: Fix MPIDR and MIDR register implementation. 2012-06-05 01:23:10 -04:00
table_walker.cc arm: Fix draining of the pagetable walker when squashing 2013-01-07 13:05:45 -05:00
table_walker.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
tlb.cc arm: Invalidate cached TLB configuration in drainResume 2013-01-07 13:05:45 -05:00
tlb.hh arm: Invalidate cached TLB configuration in drainResume 2013-01-07 13:05:45 -05:00
types.hh ARM: Fix issue with predicted next pc being wrong because of advance() ordering. 2012-06-29 11:18:28 -04:00
utility.cc arm: Remove the register mapping hack used when copying TCs 2013-01-07 13:05:44 -05:00
utility.hh Clock: Add a Cycles wrapper class and use where applicable 2012-08-28 14:30:33 -04:00
vtophys.cc MEM: Make port proxies use references rather than pointers 2012-02-24 11:45:30 -05:00
vtophys.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00