ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some bootloaders/kernels care that it's set right. You can have a single processor MP capable system, but you can't have a multi-processor UP only system. This change also fixes the initialization of the MIDR register.
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@ -55,6 +55,7 @@ class ArmSystem(System):
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# 0xc00 Primary part number ("c" or higher implies ARM v7)
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# 0x0 Revision
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midr_regval = Param.UInt32(0x350fc000, "MIDR value")
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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boot_loader = Param.String("", "File that contains the boot loader code if any")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
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@ -39,6 +39,7 @@
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*/
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#include "arch/arm/isa.hh"
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#include "arch/arm/system.hh"
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#include "cpu/checker/cpu.hh"
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#include "debug/Arm.hh"
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#include "debug/MiscRegs.hh"
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@ -72,7 +73,7 @@ ISA::clear()
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
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// Preserve MIDR accross reset
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// Preserve MIDR across reset
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miscRegs[MISCREG_MIDR] = midr;
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/* Start with an event in the mailbox */
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@ -102,8 +103,6 @@ ISA::clear()
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mvfr1.vfpHalfPrecision = 1;
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miscRegs[MISCREG_MVFR1] = mvfr1;
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miscRegs[MISCREG_MPIDR] = 0;
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// Reset values of PRRR and NMRR are implementation dependent
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miscRegs[MISCREG_PRRR] =
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@ -172,6 +171,8 @@ ISA::readMiscRegNoEffect(int misc_reg)
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MiscReg
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ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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{
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ArmSystem *arm_sys;
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if (misc_reg == MISCREG_CPSR) {
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CPSR cpsr = miscRegs[misc_reg];
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PCState pc = tc->pcState();
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@ -185,9 +186,17 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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switch (misc_reg) {
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case MISCREG_MPIDR:
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arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr());
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assert(arm_sys);
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return 0x80000000 | // multiprocessor extensions available
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tc->cpuId();
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if (arm_sys->multiProc) {
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return 0x80000000 | // multiprocessor extensions available
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tc->cpuId();
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} else {
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return 0x80000000 | // multiprocessor extensions available
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0x40000000 | // in up system
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tc->cpuId();
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}
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break;
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case MISCREG_ID_MMFR0:
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return 0x03; // VMSAv7 support
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@ -53,7 +53,7 @@ using namespace std;
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using namespace Linux;
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ArmSystem::ArmSystem(Params *p)
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: System(p), bootldr(NULL)
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: System(p), bootldr(NULL), multiProc(p->multi_proc)
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{
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if (p->boot_loader != "") {
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bootldr = createObjectFile(p->boot_loader);
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@ -107,10 +107,8 @@ ArmSystem::initState()
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}
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for (int i = 0; i < threadContexts.size(); i++) {
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if (p->midr_regval) {
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threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
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p->midr_regval);
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}
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threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
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p->midr_regval);
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}
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}
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@ -98,6 +98,9 @@ class ArmSystem : public System
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return addr & ~1;
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return addr;
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}
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/** true if this a multiprocessor system */
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bool multiProc;
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};
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#endif
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