arm: Invalidate cached TLB configuration in drainResume
Currently, we invalidate the cached miscregs in TLB::unserialize(). The intended use of the drainResume() method is to invalidate cached state and prepare the system to resume after a CPU handover or (un)serialization. This patch moves the TLB miscregs invalidation code to the drainResume() method to avoid surprising behavior.
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2 changed files with 12 additions and 3 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -252,6 +252,14 @@ TLB::flushMva(Addr mva)
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flushTlbMva++;
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}
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void
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TLB::drainResume()
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{
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// We might have unserialized something or switched CPUs, so make
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// sure to re-read the misc regs.
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miscRegValid = false;
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}
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void
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TLB::serialize(ostream &os)
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{
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@ -278,7 +286,6 @@ TLB::unserialize(Checkpoint *cp, const string §ion)
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for(int i = 0; i < min(size, num_entries); i++){
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table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
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}
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miscRegValid = false;
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}
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void
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010 ARM Limited
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -208,6 +208,8 @@ class TLB : public BaseTLB
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Fault translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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void drainResume();
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// Checkpointing
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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