sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/src/cpu
History
Curtis Dunham 567a9b0a08 arm, kvm: implement GIC state transfer 
This also allows checkpointing of a Kvm GIC via the Pl390 model.

Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2444
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03 16:51:46 +00:00
..
checker syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations 2017-02-27 14:10:15 -05:00
kvm arm, kvm: implement GIC state transfer 2017-04-03 16:51:46 +00:00
minor syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
nocpu arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
o3 syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations 2017-02-27 14:10:15 -05:00
pred cpu: implement an L-TAGE branch predictor 2016-12-21 15:25:13 -06:00
simple syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
testers style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
trace cpu: Print progress messages in Trace CPU 2017-03-16 13:52:40 +00:00
activity.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
activity.hh cpu: Useful getters for ActivityRecorder 2014-05-09 18:58:48 -04:00
base.cc syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
base.hh syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
base_dyn_inst.hh cpu, arch: fix the type used for the request flags 2016-08-15 12:00:35 +01:00
base_dyn_inst_impl.hh cpu, o3: consider split requests for LSQ checksnoop operations 2015-09-15 08:14:06 -05:00
BaseCPU.py syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
CheckerCPU.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
cpuevent.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
cpuevent.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
CPUTracers.py cpu: Put all CPU instruction tracers in a single file 2015-01-25 07:22:17 -05:00
decode_cache.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
dummy_checker.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
dummy_checker.hh cpu: Add header files for checker CPUs 2012-11-02 11:32:01 -05:00
DummyChecker.py cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy 2013-02-15 17:40:08 -05:00
exec_context.cc arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
exec_context.hh syscall_emul: [patch 13/22] add system call retry capability 2015-07-20 09:15:21 -05:00
exetrace.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
exetrace.hh base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
func_unit.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
func_unit.hh cpu: Fix issue identified by UBSan 2015-07-30 03:41:22 -04:00
FuncUnit.py cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
inst_pb_trace.cc base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
inst_pb_trace.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
inst_seq.hh build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
InstPBTrace.py cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
inteltrace.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
inteltrace.hh base: remove Trace::enabled flag 2015-09-30 15:21:55 -05:00
intr_control.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
intr_control.hh arch: Header clean up for NOISA resurrection 2013-09-04 13:22:55 -04:00
intr_control_noisa.cc arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00
IntrControl.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
nativetrace.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
nativetrace.hh style: fix missing spaces in control statements 2016-02-06 17:21:19 -08:00
op_class.hh cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass 2016-10-15 14:58:45 -05:00
pc_event.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
pc_event.hh arm: Enable support for triggering a sim panic on kernel panics 2013-04-22 13:20:31 -04:00
profile.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
profile.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
quiesce_event.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
quiesce_event.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
reg_class.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
reg_class.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
SConscript sim: add ExecMacro to Exec* compound debug flags 2015-10-06 17:26:50 -07:00
simple_thread.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
simple_thread.hh syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations 2017-02-27 14:10:15 -05:00
smt.hh includes: fix up code after sorting 2011-04-15 10:44:14 -07:00
static_inst.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
static_inst.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
static_inst_fwd.hh cpu: Don't forward declare RefCountingPtr 2014-08-13 06:57:26 -04:00
StaticInstFlags.py revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
thread_context.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
thread_context.hh syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations 2017-02-27 14:10:15 -05:00
thread_state.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
thread_state.hh syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations 2017-02-27 14:10:15 -05:00
timebuf.hh style: remove trailing whitespace 2016-02-06 17:21:18 -08:00
timing_expr.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
timing_expr.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
TimingExpr.py cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
translation.hh mem, cpu: Add a separate flag for strictly ordered memory 2015-05-05 03:22:33 -04:00