arm, kvm: implement GIC state transfer
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
This commit is contained in:
Curtis Dunham
Andreas Sandberg
parent
60075068ea
commit
567a9b0a08
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@ -43,6 +43,7 @@
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#include <linux/kvm.h>
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#include "arch/arm/kvm/base_cpu.hh"
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#include "debug/GIC.hh"
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#include "debug/Interrupt.hh"
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#include "params/MuxingKvmGic.hh"
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@ -104,6 +105,63 @@ KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
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vm.setIRQLine(line, high);
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}
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uint32_t
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KvmKernelGicV2::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
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{
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uint64_t reg;
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assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
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const uint32_t attr(
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(vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
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(offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
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kdev.getAttrPtr(group, attr, ®);
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return (uint32_t) reg;
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}
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void
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KvmKernelGicV2::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
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unsigned value)
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{
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uint64_t reg = value;
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assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
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const uint32_t attr(
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(vcpu << KVM_DEV_ARM_VGIC_CPUID_SHIFT) |
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(offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));
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kdev.setAttrPtr(group, attr, ®);
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}
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uint32_t
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KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
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}
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uint32_t
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KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
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}
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void
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KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
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}
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void
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KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
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{
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auto vcpu = vm.contextIdToVCpuId(ctx);
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setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
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}
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MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
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: Pl390(p),
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@ -121,21 +179,39 @@ MuxingKvmGic::~MuxingKvmGic()
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{
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}
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void
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MuxingKvmGic::loadState(CheckpointIn &cp)
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{
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Pl390::loadState(cp);
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}
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void
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MuxingKvmGic::startup()
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{
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Pl390::startup();
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usingKvm = (kernelGic != nullptr) && validKvmEnvironment();
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if (usingKvm)
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fromPl390ToKvm();
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}
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DrainState
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MuxingKvmGic::drain()
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{
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if (usingKvm)
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fromKvmToPl390();
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return Pl390::drain();
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}
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void
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MuxingKvmGic::drainResume()
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{
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Pl390::drainResume();
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bool use_kvm = (kernelGic != nullptr) && validKvmEnvironment();
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if (use_kvm != usingKvm) {
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// Should only occur due to CPU switches
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if (use_kvm) // from simulation to KVM emulation
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fromPl390ToKvm();
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else // from KVM emulation to simulation
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fromKvmToPl390();
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// otherwise, drain() already sync'd the state back to the Pl390
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usingKvm = use_kvm;
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}
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@ -144,19 +220,14 @@ MuxingKvmGic::drainResume()
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void
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MuxingKvmGic::serialize(CheckpointOut &cp) const
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{
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if (!usingKvm)
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return Pl390::serialize(cp);
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panic("Checkpointing unsupported\n");
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// drain() already ensured Pl390 updated with KvmGic state if necessary
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Pl390::serialize(cp);
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}
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void
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MuxingKvmGic::unserialize(CheckpointIn &cp)
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{
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if (!usingKvm)
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return Pl390::unserialize(cp);
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panic("Checkpointing unsupported\n");
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Pl390::unserialize(cp);
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}
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Tick
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@ -230,16 +301,150 @@ MuxingKvmGic::validKvmEnvironment() const
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return true;
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}
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void
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MuxingKvmGic::copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr)
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{
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auto val = from->readDistributor(ctx, daddr);
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DPRINTF(GIC, "copy dist 0x%x 0x%08x\n", daddr, val);
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to->writeDistributor(ctx, daddr, val);
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}
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void
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MuxingKvmGic::copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr)
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{
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auto val = from->readCpu(ctx, daddr);
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DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
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to->writeCpu(ctx, daddr, val);
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}
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void
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MuxingKvmGic::copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (int ctx = 0; ctx < system._numContexts; ++ctx)
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for (auto a = daddr; a < daddr + size; a += 4)
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copyDistRegister(from, to, ctx, a);
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}
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void
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MuxingKvmGic::clearBankedDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (int ctx = 0; ctx < system._numContexts; ++ctx)
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for (auto a = daddr; a < daddr + size; a += 4)
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to->writeDistributor(ctx, a, 0xFFFFFFFF);
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}
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void
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MuxingKvmGic::copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (auto a = daddr; a < daddr + size; a += 4)
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copyDistRegister(from, to, 0, a);
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}
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void
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MuxingKvmGic::clearDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size)
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{
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for (auto a = daddr; a < daddr + size; a += 4)
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to->writeDistributor(0, a, 0xFFFFFFFF);
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}
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void
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MuxingKvmGic::copyGicState(BaseGicRegisters* from, BaseGicRegisters* to)
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{
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Addr set, clear;
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size_t size;
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/// CPU state (GICC_*)
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// Copy CPU Interface Control Register (CTLR),
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// Interrupt Priority Mask Register (PMR), and
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// Binary Point Register (BPR)
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for (int ctx = 0; ctx < system._numContexts; ++ctx) {
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copyCpuRegister(from, to, ctx, GICC_CTLR);
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copyCpuRegister(from, to, ctx, GICC_PMR);
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copyCpuRegister(from, to, ctx, GICC_BPR);
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}
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/// Distributor state (GICD_*)
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// Copy Distributor Control Register (CTLR)
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copyDistRegister(from, to, 0, GICD_CTLR);
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// Copy interrupt-enabled statuses (I[CS]ENABLERn; R0 is per-CPU banked)
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set = Pl390::GICD_ISENABLER.start();
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clear = Pl390::GICD_ICENABLER.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy pending interrupts (I[CS]PENDRn; R0 is per-CPU banked)
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set = Pl390::GICD_ISPENDR.start();
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clear = Pl390::GICD_ICPENDR.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy active interrupts (I[CS]ACTIVERn; R0 is per-CPU banked)
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set = Pl390::GICD_ISACTIVER.start();
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clear = Pl390::GICD_ICACTIVER.start();
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size = Pl390::itLines / 8;
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clearBankedDistRange(to, clear, 4);
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copyBankedDistRange(from, to, set, 4);
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set += 4, clear += 4, size -= 4;
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clearDistRange(to, clear, size);
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copyDistRange(from, to, set, size);
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// Copy interrupt priorities (IPRIORITYRn; R0-7 are per-CPU banked)
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set = Pl390::GICD_IPRIORITYR.start();
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copyBankedDistRange(from, to, set, 32);
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set += 32;
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size = Pl390::itLines - 32;
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copyDistRange(from, to, set, size);
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// Copy interrupt processor target regs (ITARGETRn; R0-7 are read-only)
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set = Pl390::GICD_ITARGETSR.start() + 32;
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size = Pl390::itLines - 32;
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copyDistRange(from, to, set, size);
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// Copy interrupt configuration registers (ICFGRn)
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set = Pl390::GICD_ICFGR.start();
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size = Pl390::itLines / 4;
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copyDistRange(from, to, set, size);
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}
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void
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MuxingKvmGic::fromPl390ToKvm()
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{
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panic("Gic multiplexing not implemented.\n");
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copyGicState(static_cast<Pl390*>(this), kernelGic);
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}
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void
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MuxingKvmGic::fromKvmToPl390()
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{
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panic("Gic multiplexing not implemented.\n");
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copyGicState(kernelGic, static_cast<Pl390*>(this));
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// the values read for the Interrupt Priority Mask Register (PMR)
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// have been shifted by three bits due to its having been emulated by
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// a VGIC with only 5 PMR bits in its VMCR register. Presently the
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// Linux kernel does not repair this inaccuracy, so we correct it here.
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for (int cpu = 0; cpu < system._numContexts; ++cpu) {
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cpuPriority[cpu] <<= 3;
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assert((cpuPriority[cpu] & ~0xff) == 0);
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}
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}
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MuxingKvmGic *
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@ -54,7 +54,7 @@
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* model. It exposes an API that is similar to that of
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* software-emulated GIC models in gem5.
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*/
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class KvmKernelGicV2
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class KvmKernelGicV2 : public BaseGicRegisters
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{
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public:
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/**
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@ -117,6 +117,14 @@ class KvmKernelGicV2
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/** Address range for the distributor interface */
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const AddrRange distRange;
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/** BaseGicRegisters interface */
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uint32_t readDistributor(ContextID ctx, Addr daddr) override;
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uint32_t readCpu(ContextID ctx, Addr daddr) override;
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void writeDistributor(ContextID ctx, Addr daddr,
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uint32_t data) override;
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void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
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/* @} */
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protected:
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@ -130,6 +138,26 @@ class KvmKernelGicV2
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*/
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void setIntState(unsigned type, unsigned vcpu, unsigned irq, bool high);
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/**
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* Get value of GIC register "from" a cpu
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*
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* @param group Distributor or CPU (KVM_DEV_ARM_VGIC_GRP_{DIST,CPU}_REGS)
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* @param vcpu CPU id within KVM
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* @param offset register offset
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*/
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uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset);
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/**
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* Set value of GIC register "from" a cpu
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*
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* @param group Distributor or CPU (KVM_DEV_ARM_VGIC_GRP_{DIST,CPU}_REGS)
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* @param vcpu CPU id within KVM
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* @param offset register offset
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* @param value value to set register to
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*/
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void setGicReg(unsigned group, unsigned vcpu, unsigned offset,
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unsigned value);
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/** KVM VM in the parent system */
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KvmVM &vm;
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@ -146,7 +174,10 @@ class MuxingKvmGic : public Pl390
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MuxingKvmGic(const MuxingKvmGicParams *p);
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~MuxingKvmGic();
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void loadState(CheckpointIn &cp) override;
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void startup() override;
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DrainState drain() override;
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void drainResume() override;
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void serialize(CheckpointOut &cp) const override;
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@ -176,9 +207,25 @@ class MuxingKvmGic : public Pl390
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private:
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bool usingKvm;
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/** Multiplexing implementation: state transfer functions */
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/** Multiplexing implementation */
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void fromPl390ToKvm();
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void fromKvmToPl390();
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void copyGicState(BaseGicRegisters* from, BaseGicRegisters* to);
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void copyDistRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr);
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void copyCpuRegister(BaseGicRegisters* from, BaseGicRegisters* to,
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ContextID ctx, Addr daddr);
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void copyBankedDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size);
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void clearBankedDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size);
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void copyDistRange(BaseGicRegisters* from, BaseGicRegisters* to,
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Addr daddr, size_t size);
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void clearDistRange(BaseGicRegisters* to,
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Addr daddr, size_t size);
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};
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#endif // __ARCH_ARM_KVM_GIC_HH__
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@ -106,6 +106,7 @@ class BaseKvmCPU : public BaseCPU
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void deallocateContext(ThreadID thread_num);
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void haltContext(ThreadID thread_num) override;
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long getVCpuID() const { return vcpuID; }
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ThreadContext *getContext(int tn) override;
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Counter totalInsts() const override;
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@ -50,6 +50,7 @@
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#include <cerrno>
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#include <memory>
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#include "cpu/kvm/base.hh"
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#include "debug/Kvm.hh"
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#include "params/KvmVM.hh"
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#include "sim/system.hh"
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@ -528,12 +529,21 @@ KvmVM::createDevice(uint32_t type, uint32_t flags)
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}
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void
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KvmVM::setSystem(System *s) {
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KvmVM::setSystem(System *s)
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{
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panic_if(system != nullptr, "setSystem() can only be called once");
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panic_if(s == nullptr, "setSystem() called with null System*");
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system = s;
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}
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long
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KvmVM::contextIdToVCpuId(ContextID ctx) const
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{
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assert(system != nullptr);
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return dynamic_cast<BaseKvmCPU*>
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(system->getThreadContext(ctx)->getCpuPtr())->getVCpuID();
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}
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int
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KvmVM::createVCPU(long vcpuID)
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{
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@ -48,6 +48,7 @@
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// forward declarations
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struct KvmVMParams;
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class BaseKvmCPU;
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class System;
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/**
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@ -405,6 +406,11 @@ class KvmVM : public SimObject
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*/
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void setSystem(System *s);
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/**
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* Get the VCPUID for a given context
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*/
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long contextIdToVCpuId(ContextID ctx) const;
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#if defined(__aarch64__)
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public: // ARM-specific
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/**
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012-2013 ARM Limited
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* Copyright (c) 2012-2013, 2017 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@ -92,4 +92,15 @@ class BaseGic : public PioDevice
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Platform *platform;
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};
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class BaseGicRegisters
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{
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public:
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virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0;
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virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0;
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||||
virtual void writeDistributor(ContextID ctx, Addr daddr,
|
||||
uint32_t data) = 0;
|
||||
virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@
|
|||
#include "dev/platform.hh"
|
||||
#include "params/Pl390.hh"
|
||||
|
||||
class Pl390 : public BaseGic
|
||||
class Pl390 : public BaseGic, public BaseGicRegisters
|
||||
{
|
||||
protected:
|
||||
// distributor memory addresses
|
||||
|
|
@ -404,26 +404,34 @@ class Pl390 : public BaseGic
|
|||
* @param pkt packet to respond to
|
||||
*/
|
||||
Tick readDistributor(PacketPtr pkt);
|
||||
uint32_t readDistributor(ContextID ctx, Addr daddr, size_t resp_sz);
|
||||
uint32_t readDistributor(ContextID ctx, Addr daddr,
|
||||
size_t resp_sz);
|
||||
uint32_t readDistributor(ContextID ctx, Addr daddr) override {
|
||||
return readDistributor(ctx, daddr, 4);
|
||||
}
|
||||
|
||||
/** Handle a read to the cpu portion of the GIC
|
||||
* @param pkt packet to respond to
|
||||
*/
|
||||
Tick readCpu(PacketPtr pkt);
|
||||
uint32_t readCpu(ContextID ctx, Addr daddr);
|
||||
uint32_t readCpu(ContextID ctx, Addr daddr) override;
|
||||
|
||||
/** Handle a write to the distributor portion of the GIC
|
||||
* @param pkt packet to respond to
|
||||
*/
|
||||
Tick writeDistributor(PacketPtr pkt);
|
||||
void writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
|
||||
size_t data_sz);
|
||||
void writeDistributor(ContextID ctx, Addr daddr,
|
||||
uint32_t data, size_t data_sz);
|
||||
void writeDistributor(ContextID ctx, Addr daddr,
|
||||
uint32_t data) override {
|
||||
return writeDistributor(ctx, daddr, data, 4);
|
||||
}
|
||||
|
||||
/** Handle a write to the cpu portion of the GIC
|
||||
* @param pkt packet to respond to
|
||||
*/
|
||||
Tick writeCpu(PacketPtr pkt);
|
||||
void writeCpu(ContextID ctx, Addr daddr, uint32_t data);
|
||||
void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override;
|
||||
};
|
||||
|
||||
#endif //__DEV_ARM_GIC_H__
|
||||
|
|
|
|||
Loading…
Reference in a new issue