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Sascha Bischoff 9d23e6d323 dev: Add basic checkpoint support to VirtIO9PProxy device 
This patch adds very basic checkpoint support for the VirtIO9PProxy
device. Previously, attempts to checkpoint gem5 with a present 9P
device caused gem5 to fatal as none of the state is tracked. We still
do not track any state, but we replace the fatal with a warning which
is triggered if the device has been used by the guest system. In the
event that it has not been used, we assume that no state is lost
during checkpointing. The warning is triggered on both a serialize and
an unserialize to ensure maximum visibility for the user.
2015-11-05 09:40:12 +00:00
..
alpha misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
arm dev: Fix segfault in flash device 2015-10-29 08:48:25 -04:00
mips misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
sparc misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
virtio dev: Add basic checkpoint support to VirtIO9PProxy device 2015-11-05 09:40:12 +00:00
x86 x86: Add missing explicit overrides for X86 devices 2015-10-23 09:51:12 -04:00
baddev.cc dev: Include basic devices in NULL ISA build 2014-02-18 05:50:59 -05:00
baddev.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
BadDevice.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
copy_engine.cc dev: Don't access the platform directly in PCI devices 2015-11-09 13:44:04 +00:00
copy_engine.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
copy_engine_defs.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
CopyEngine.py config: Remove redundant explicit setting of default clocks 2013-06-27 05:49:49 -04:00
Device.py dev: Fix IsaFake's cxx_header setting 2014-03-23 11:11:37 -04:00
disk_image.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
disk_image.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
DiskImage.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
dma_device.cc dev: Add a simple DMA engine that can be used by devices 2015-08-07 09:59:23 +01:00
dma_device.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
etherbus.cc trace: reimplement the DTRACE function so it doesn't use a vector 2011-04-15 10:44:32 -07:00
etherbus.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherdevice.cc stats: only consider a formula initialized if there is a formula 2010-06-15 01:18:36 -07:00
etherdevice.hh dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
etherdump.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
etherdump.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.cc includes: sort all includes 2011-04-15 10:44:06 -07:00
etherint.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherlink.cc dev: Remove auto-serialization dependency in EtherLink 2015-09-01 15:28:44 +01:00
etherlink.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
Ethernet.py dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
etherobject.hh Devices: Make EtherInts connect in the same way memory ports currently do. 2007-08-16 16:49:02 -04:00
etherpkt.cc dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
etherpkt.hh dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
ethertap.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
ethertap.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
I2C.py dev: Add support for i2c devices 2015-04-23 13:37:48 -04:00
i2cbus.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
i2cbus.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
i2cdev.hh dev: Add support for i2c devices 2015-04-23 13:37:48 -04:00
i8254xGBe.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
i8254xGBe.hh dev: Don't access the platform directly in PCI devices 2015-11-09 13:44:04 +00:00
i8254xGBe_defs.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
Ide.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ide_atareg.h gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
ide_ctrl.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
ide_ctrl.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
ide_disk.cc dev: IDE Disk: Handle bad IDE image size 2015-09-15 08:14:07 -05:00
ide_disk.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
ide_wdcreg.h copyright: clean up copyright blocks 2011-06-02 14:36:35 -07:00
intel_8254_timer.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
intel_8254_timer.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
io_device.cc mem: Use the packet delays and do not just zero them out 2015-11-06 03:26:36 -05:00
io_device.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
isa_fake.cc mem: Remove redundant Packet::allocate calls 2014-12-02 06:07:41 -05:00
isa_fake.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
mc146818.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
mc146818.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
multi_etherlink.cc dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
multi_etherlink.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
multi_iface.cc dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
multi_iface.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
multi_packet.cc dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
multi_packet.hh dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
ns_gige.cc dev: Remove unused header includes 2015-11-09 13:44:15 +00:00
ns_gige.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
ns_gige_reg.h X86: Get X86_FS to compile. 2007-09-24 17:39:56 -07:00
Pci.py dev: seperate legacy io offsets from PCI offset 2014-09-03 07:43:06 -04:00
pciconfigall.cc mem: Remove redundant Packet::allocate calls 2014-12-02 06:07:41 -05:00
pciconfigall.hh dev: consistently end device classes in 'Device' 2013-07-11 21:56:50 -05:00
pcidev.cc dev: Remove unused header includes 2015-11-09 13:44:15 +00:00
pcidev.hh dev: Don't access the platform directly in PCI devices 2015-11-09 13:44:04 +00:00
pcireg.h dev: refactor pci config space for sysfs scanning 2014-10-16 05:49:57 -04:00
pixelpump.cc dev: Implement a simple display timing generator 2015-08-07 09:59:26 +01:00
pixelpump.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
pktfifo.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
pktfifo.hh dev: Make serialization in Sinic constant 2015-08-07 09:59:14 +01:00
platform.cc Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. 2011-02-23 15:10:49 -06:00
platform.hh dev: Remove unused system pointer in the Platform base class 2015-02-11 10:23:22 -05:00
Platform.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ps2.cc dev: Support translating left and right ALT keys. 2014-12-03 03:06:03 -08:00
ps2.hh ARM: PS2 encoding fix 2012-06-05 01:23:10 -04:00
rtcreg.h dev: Clean up MC146818 register (A & B) handling 2013-06-03 12:28:41 +02:00
SConscript dev: Implement a simple display timing generator 2015-08-07 09:59:26 +01:00
simple_disk.cc dev: use correct delete operation in SimpleDisk 2012-05-10 18:04:27 -05:00
simple_disk.hh includes: sort all includes 2011-04-15 10:44:06 -07:00
SimpleDisk.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
sinic.cc dev: Don't access the platform directly in PCI devices 2015-11-09 13:44:04 +00:00
sinic.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00
sinicreg.hh gcc: Clean-up of non-C++0x compliant code, first steps 2012-03-19 06:36:09 -04:00
tcp_iface.cc dev: add support for multi gem5 runs 2015-07-15 19:53:50 -05:00
tcp_iface.hh misc: Remove redundant compiler-specific defines 2015-10-12 04:07:59 -04:00
terminal.cc base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
terminal.hh base: Rewrite the CircleBuf to fix bugs and add serialization 2015-08-07 09:59:19 +01:00
Terminal.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart.cc dev: Refactor terminal<->UART interface to make it more generic 2014-09-20 17:17:50 -04:00
uart.hh dev: Refactor terminal<->UART interface to make it more generic 2014-09-20 17:17:50 -04:00
Uart.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart8250.cc sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
uart8250.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00