sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

Replace curTick global variable with accessor functions.

Browse source 
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
This commit is contained in:
Steve Reinhardt 2011-01-07 21:50:29 -08:00
parent c22be9f2f0
commit 6f1187943c
129 changed files with 515 additions and 509 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/arch/alpha/isa/decoder.isa
View file

@ -791,7 +791,7 @@ decode OPCODE default Unknown::unknown() {
Ra = xc->readMiscReg(IPR_CC) + (Rb & 0);
#else
Ra = curTick;
Ra = curTick();
#endif
}}, IsUnverifiable);

4
src/arch/alpha/kernel_stats.cc
View file

@ -143,9 +143,9 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
Linux::ThreadInfo(tc).curTaskPID());
_modeGood[newmode]++;
_modeTicks[themode] += curTick - lastModeTick;
_modeTicks[themode] += curTick() - lastModeTick;
lastModeTick = curTick;
lastModeTick = curTick();
themode = newmode;
}

2
src/arch/alpha/tru64/process.cc
View file

@ -184,7 +184,7 @@ tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr);
const int clk_hz = one_million;
elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz));
elp->si_user = htog(curTick() / (SimClock::Frequency / clk_hz));
elp->si_nice = htog(0);
elp->si_sys = htog(0);
elp->si_idle = htog(0);

2
src/arch/arm/table_walker.cc
View file

@ -713,7 +713,7 @@ void
TableWalker::nextWalk(ThreadContext *tc)
{
if (pendingQueue.size())
schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick+1));
schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1));
}

4
src/arch/mips/isa.cc
View file

@ -528,7 +528,7 @@ ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
//schedule UPDATE
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
cpu->schedule(cp0_event, curTick + cpu->ticks(delay));
cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
}
}
@ -585,7 +585,7 @@ ISA::CP0Event::description() const
void
ISA::CP0Event::scheduleEvent(int delay)
{
cpu->reschedule(this, curTick + cpu->ticks(delay), true);
cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
}
void

4
src/arch/mips/isa/formats/mt.isa
View file

@ -201,7 +201,7 @@ def format MT_Control(code, *opt_flags) {{
def format MT_MFTR(code, *flags) {{
flags += ('IsNonSpeculative', )
# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
code += 'if (MT_H == 1) {\n'
code += 'data = bits(data, top_bit, bottom_bit);\n'
@ -217,7 +217,7 @@ def format MT_MFTR(code, *flags) {{
def format MT_MTTR(code, *flags) {{
flags += ('IsNonSpeculative', )
# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)

2
src/arch/mips/locked_mem.hh
View file

@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req)
if (stCondFailures % 100000 == 0) {
warn("%i: context %d: %d consecutive "
"store conditional failures\n",
curTick, xc->contextId(), stCondFailures);
curTick(), xc->contextId(), stCondFailures);
}
if (!lock_flag){

6
src/arch/mips/mt.hh
View file

@ -81,7 +81,7 @@ haltThread(TC *tc)
tc->setMiscReg(MISCREG_TC_RESTART, pc.npc());
warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
curTick, tc->threadId(), tc->getCpuPtr()->name(),
curTick(), tc->threadId(), tc->getCpuPtr()->name(),
pc.pc(), pc.npc());
}
}
@ -99,7 +99,7 @@ restoreThread(TC *tc)
tc->activate(0);
warn("%i: Restoring thread %i in %s @ PC %x",
curTick, tc->threadId(), tc->getCpuPtr()->name(), restartPC);
curTick(), tc->threadId(), tc->getCpuPtr()->name(), restartPC);
}
}
@ -208,7 +208,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
tcStatus.a = 0;
tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
warn("%i: Deactivating Hardware Thread Context #%i",
curTick, tc->threadId());
curTick(), tc->threadId());
}
} else if (src_reg > 0) {
if (src_reg && !yield_mask != 0) {

10
src/arch/sparc/ua2005.cc
View file

@ -111,7 +111,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
cpu->deschedule(tickCompare);
cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
@ -127,7 +127,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
cpu->deschedule(sTickCompare);
cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@ -197,7 +197,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
cpu->deschedule(hSTickCompare);
cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@ -335,7 +335,7 @@ ISA::processSTickCompare(ThreadContext *tc)
setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
}
} else {
cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
}
}
@ -363,7 +363,7 @@ ISA::processHSTickCompare(ThreadContext *tc)
}
// Need to do something to cause interrupt to happen here !!! @todo
} else {
cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
}
}

8
src/arch/x86/interrupts.cc
View file

@ -394,7 +394,7 @@ X86ISA::Interrupts::readReg(ApicRegIndex reg)
uint64_t ticksPerCount = clock *
divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
// Compute how many m5 ticks are left.
uint64_t val = apicTimerEvent.when() - curTick;
uint64_t val = apicTimerEvent.when() - curTick();
// Turn that into a count.
val = (val + ticksPerCount - 1) / ticksPerCount;
return val;
@ -572,13 +572,13 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
uint64_t newCount = newVal *
(divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
// Schedule on the edge of the next tick plus the new count.
Tick offset = curTick % clock;
Tick offset = curTick() % clock;
if (offset) {
reschedule(apicTimerEvent,
curTick + (newCount + 1) * clock - offset, true);
curTick() + (newCount + 1) * clock - offset, true);
} else {
reschedule(apicTimerEvent,
curTick + newCount * clock, true);
curTick() + newCount * clock, true);
}
}
break;

12
src/base/cp_annotate.cc
View file

@ -161,7 +161,7 @@ CPA::swSmBegin(ThreadContext *tc)
StringWrap name(sys->name());
if (!sm[0])
warn("Got null SM at tick %d\n", curTick);
warn("Got null SM at tick %d\n", curTick());
int sysi = getSys(sys);
int smi = getSm(sysi, sm, args[1]);
@ -273,7 +273,7 @@ CPA::doSwSmEnd(System *sys, int cpuid, string sm, uint64_t frame)
DPRINTF(Annotate, "Ending machine: %s; end stack: %s\n", sm,
smMap[smib-1].second.first);
warn("State machine stack not unwinding correctly at %d\n", curTick);
warn("State machine stack not unwinding correctly at %d\n", curTick());
} else {
DPRINTF(Annotate,
"State machine ending:%s sysi:%d id:%#x back:%d getSm:%d\n",
@ -316,7 +316,7 @@ CPA::swExplictBegin(ThreadContext *tc)
DPRINTF(Annotate, "Explict begin of state %s\n", st);
uint32_t flags = args[0];
if (flags & FL_BAD)
warn("BAD state encountered: at cycle %d: %s\n", curTick, st);
warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
swBegin(tc->getSystemPtr(), tc->contextId(), st, getFrame(tc), true, args[0]);
}
@ -688,10 +688,10 @@ CPA::swAq(ThreadContext *tc)
warn("%d: Queue Assert: SW said there should be %d byte(s) in %s,"
"however there are %d byte(s)\n",
curTick, size, q, qBytes[qi-1]);
curTick(), size, q, qBytes[qi-1]);
DPRINTF(AnnotateQ, "%d: Queue Assert: SW said there should be %d"
" byte(s) in %s, however there are %d byte(s)\n",
curTick, size, q, qBytes[qi-1]);
curTick(), size, q, qBytes[qi-1]);
}
}
@ -813,7 +813,7 @@ CPA::AnnDataPtr
CPA::add(int t, int f, int c, int sm, int stq, int32_t d)
{
AnnDataPtr an = new AnnotateData;
an->time = curTick;
an->time = curTick();
an->data = d;
an->orig_data = d;
an->op = t;

2
src/base/cp_annotate.hh
View file

@ -408,7 +408,7 @@ class CPA : SimObject
int smi = getSm(sysi, sm, frame);
add(OP_BEGIN, FL_HW | f, 0, smi, getSt(sm, st));
if (f & FL_BAD)
warn("BAD state encountered: at cycle %d: %s\n", curTick, st);
warn("BAD state encountered: at cycle %d: %s\n", curTick(), st);
}
inline void hwQ(flags f, System *sys, uint64_t frame, std::string sm,

4
src/base/fast_alloc.cc
View file

@ -80,7 +80,7 @@ FastAlloc::moreStructs(int bucket)
#include <typeinfo>
#include "base/cprintf.hh"
#include "sim/core.hh" // for curTick
#include "sim/core.hh" // for curTick()
using namespace std;
@ -104,7 +104,7 @@ FastAlloc::FastAlloc()
{
// mark this object in use
inUse = true;
whenAllocated = curTick;
whenAllocated = curTick();
// update count
++numInUse;

4
src/base/misc.cc
View file

@ -76,7 +76,7 @@ __exit_message(const char *prefix, int code,
format += "Memory Usage: %ld KBytes\n";
format += "For more information see: http://www.m5sim.org/%s/%x\n";
args.push_back(curTick);
args.push_back(curTick());
args.push_back(func);
args.push_back(file);
args.push_back(line);
@ -114,7 +114,7 @@ __base_message(std::ostream &stream, const char *prefix, bool verbose,
if (verbose) {
format += " @ cycle %d\n[%s:%s, line %d]\n";
args.push_back(curTick);
args.push_back(curTick());
args.push_back(func);
args.push_back(file);
args.push_back(line);

4
src/base/remote_gdb.cc
View file

@ -217,10 +217,10 @@ GDBListener::listen()
#ifndef NDEBUG
ccprintf(cerr, "%d: %s: listening for remote gdb #%d on port %d\n",
curTick, name(), gdb->number, port);
curTick(), name(), gdb->number, port);
#else
ccprintf(cerr, "%d: %s: listening for remote gdb on port %d\n",
curTick, name(), port);
curTick(), name(), port);
#endif
}

20
src/base/statistics.hh
View file

@ -72,7 +72,7 @@
class Callback;
/** The current simulated tick. */
extern Tick curTick;
extern Tick curTick();
/* A namespace for all of the Statistics */
namespace Stats {
@ -530,8 +530,8 @@ class AvgStor
void
set(Counter val)
{
total += current * (curTick - last);
last = curTick;
total += current * (curTick() - last);
last = curTick();
current = val;
}
@ -560,8 +560,8 @@ class AvgStor
Result
result() const
{
assert(last == curTick);
return (Result)(total + current) / (Result)(curTick - lastReset + 1);
assert(last == curTick());
return (Result)(total + current) / (Result)(curTick() - lastReset + 1);
}
/**
@ -575,8 +575,8 @@ class AvgStor
void
prepare(Info *info)
{
total += current * (curTick - last);
last = curTick;
total += current * (curTick() - last);
last = curTick();
}
/**
@ -586,8 +586,8 @@ class AvgStor
reset(Info *info)
{
total = 0.0;
last = curTick;
lastReset = curTick;
last = curTick();
lastReset = curTick();
}
};
@ -1576,7 +1576,7 @@ class AvgSampleStor
data.type = params->type;
data.sum = sum;
data.squares = squares;
data.samples = curTick;
data.samples = curTick();
}
/**

2
src/base/stats/mysql.cc
View file

@ -613,7 +613,7 @@ MySql::output()
configure();
// store sample #
newdata.tick = curTick;
newdata.tick = curTick();
MySQL::Connection &mysql = run->conn();

6
src/base/stats/output.cc
View file

@ -45,10 +45,10 @@ list<Output *> OutputList;
void
dump()
{
assert(lastDump <= curTick);
if (lastDump == curTick)
assert(lastDump <= curTick());
if (lastDump == curTick())
return;
lastDump = curTick;
lastDump = curTick();
prepare();

10
src/base/trace.hh
View file

@ -89,17 +89,17 @@ inline const std::string &name() { return Trace::DefaultName; }
#define DDUMP(x, data, count) do { \
if (DTRACE(x)) \
Trace::dump(curTick, name(), data, count); \
Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTF(x, ...) do { \
if (DTRACE(x)) \
Trace::dprintf(curTick, name(), __VA_ARGS__); \
Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
#define DPRINTFS(x,s, ...) do { \
if (DTRACE(x)) \
Trace::dprintf(curTick, s->name(), __VA_ARGS__); \
Trace::dprintf(curTick(), s->name(), __VA_ARGS__); \
} while (0)
@ -109,11 +109,11 @@ inline const std::string &name() { return Trace::DefaultName; }
} while (0)
#define DDUMPN(data, count) do { \
Trace::dump(curTick, name(), data, count); \
Trace::dump(curTick(), name(), data, count); \
} while (0)
#define DPRINTFN(...) do { \
Trace::dprintf(curTick, name(), __VA_ARGS__); \
Trace::dprintf(curTick(), name(), __VA_ARGS__); \
} while (0)
#define DPRINTFNR(...) do { \

22
src/cpu/base.cc
View file

@ -66,7 +66,7 @@ CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
cpu(_cpu), _repeatEvent(true)
{
if (_interval)
cpu->schedule(this, curTick + _interval);
cpu->schedule(this, curTick() + _interval);
}
void
@ -82,13 +82,13 @@ CPUProgressEvent::process()
ipc = 0.0;
#else
cprintf("%lli: %s progress event, total committed:%i, progress insts "
"committed: %lli\n", curTick, cpu->name(), temp,
"committed: %lli\n", curTick(), cpu->name(), temp,
temp - lastNumInst);
#endif
lastNumInst = temp;
if (_repeatEvent)
cpu->schedule(this, curTick + _interval);
cpu->schedule(this, curTick() + _interval);
}
const char *
@ -110,7 +110,7 @@ BaseCPU::BaseCPU(Params *p)
phase(p->phase)
#endif
{
// currentTick = curTick;
// currentTick = curTick();
// if Python did not provide a valid ID, do it here
if (_cpuId == -1 ) {
@ -231,7 +231,7 @@ BaseCPU::startup()
{
#if FULL_SYSTEM
if (!params()->defer_registration && profileEvent)
schedule(profileEvent, curTick);
schedule(profileEvent, curTick());
#endif
if (params()->progress_interval) {
@ -270,7 +270,7 @@ BaseCPU::regStats()
Tick
BaseCPU::nextCycle()
{
Tick next_tick = curTick - phase + clock - 1;
Tick next_tick = curTick() - phase + clock - 1;
next_tick -= (next_tick % clock);
next_tick += phase;
return next_tick;
@ -284,7 +284,7 @@ BaseCPU::nextCycle(Tick begin_tick)
next_tick = next_tick - (next_tick % clock) + clock;
next_tick += phase;
assert(next_tick >= curTick);
assert(next_tick >= curTick());
return next_tick;
}
@ -390,7 +390,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
threadContexts[i]->profileClear();
if (profileEvent)
schedule(profileEvent, curTick);
schedule(profileEvent, curTick());
#endif
// Connect new CPU to old CPU's memory only if new CPU isn't
@ -424,7 +424,7 @@ BaseCPU::ProfileEvent::process()
tc->profileSample();
}
cpu->schedule(this, curTick + interval);
cpu->schedule(this, curTick() + interval);
}
void
@ -465,7 +465,7 @@ BaseCPU::traceFunctionsInternal(Addr pc)
}
ccprintf(*functionTraceStream, " (%d)\n%d: %s",
curTick - functionEntryTick, curTick, sym_str);
functionEntryTick = curTick;
curTick() - functionEntryTick, curTick(), sym_str);
functionEntryTick = curTick();
}
}

6
src/cpu/base.hh
View file

@ -100,20 +100,20 @@ class BaseCPU : public MemObject
// Tick currentTick;
inline Tick frequency() const { return SimClock::Frequency / clock; }
inline Tick ticks(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
inline Tick curCycle() const { return curTick() / clock; }
inline Tick tickToCycles(Tick val) const { return val / clock; }
// @todo remove me after debugging with legion done
Tick instCount() { return instCnt; }
/** The next cycle the CPU should be scheduled, given a cache
* access or quiesce event returning on this cycle. This function
* may return curTick if the CPU should run on the current cycle.
* may return curTick() if the CPU should run on the current cycle.
*/
Tick nextCycle();
/** The next cycle the CPU should be scheduled, given a cache
* access or quiesce event returning on the given Tick. This
* function may return curTick if the CPU should run on the
* function may return curTick() if the CPU should run on the
* current cycle.
* @param begin_tick The tick that the event is completing on.
*/

4
src/cpu/checker/cpu.cc
View file

@ -245,7 +245,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (data != inst_data) {
warn("%lli: Store value does not match value in memory! "
"Instruction: %#x, memory: %#x",
curTick, inst_data, data);
curTick(), inst_data, data);
handleError();
}
}
@ -327,6 +327,6 @@ void
CheckerCPU::dumpAndExit()
{
warn("%lli: Checker PC:%#x, next PC:%#x",
curTick, thread->readPC(), thread->readNextPC());
curTick(), thread->readPC(), thread->readNextPC());
panic("Checker found an error!");
}

18
src/cpu/checker/cpu_impl.hh
View file

@ -126,7 +126,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
} else {
warn("%lli: Changed PC does not match expected PC, "
"changed: %#x, expected: %#x",
curTick, thread->readPC(), newPC);
curTick(), thread->readPC(), newPC);
CheckerCPU::handleError();
}
willChangePC = false;
@ -166,7 +166,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
// translate this instruction; in the SMT case it's
// possible that its ITB entry was kicked out.
warn("%lli: Instruction PC %#x was not found in the ITB!",
curTick, thread->readPC());
curTick(), thread->readPC());
handleError(inst);
// go to the next instruction
@ -315,10 +315,10 @@ Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
{
if (inst->readPC() != thread->readPC()) {
warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
curTick, inst->readPC(), thread->readPC());
curTick(), inst->readPC(), thread->readPC());
if (changedPC) {
warn("%lli: Changed PCs recently, may not be an error",
curTick);
curTick());
} else {
handleError(inst);
}
@ -329,7 +329,7 @@ Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
if (mi != machInst) {
warn("%lli: Binary instructions do not match! Inst: %#x, "
"checker: %#x",
curTick, mi, machInst);
curTick(), mi, machInst);
handleError(inst);
}
}
@ -354,7 +354,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
if (result_mismatch) {
warn("%lli: Instruction results do not match! (Values may not "
"actually be integers) Inst: %#x, checker: %#x",
curTick, inst->readIntResult(), result.integer);
curTick(), inst->readIntResult(), result.integer);
// It's useful to verify load values from memory, but in MP
// systems the value obtained at execute may be different than
@ -371,7 +371,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
if (inst->readNextPC() != thread->readNextPC()) {
warn("%lli: Instruction next PCs do not match! Inst: %#x, "
"checker: %#x",
curTick, inst->readNextPC(), thread->readNextPC());
curTick(), inst->readNextPC(), thread->readNextPC());
handleError(inst);
}
@ -388,7 +388,7 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
thread->readMiscRegNoEffect(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
curTick, misc_reg_idx,
curTick(), misc_reg_idx,
inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
thread->readMiscRegNoEffect(misc_reg_idx));
handleError(inst);
@ -402,7 +402,7 @@ Checker<DynInstPtr>::validateState()
{
if (updateThisCycle) {
warn("%lli: Instruction PC %#x results didn't match up, copying all "
"registers from main CPU", curTick, unverifiedInst->readPC());
"registers from main CPU", curTick(), unverifiedInst->readPC());
// Heavy-weight copying of all registers
thread->copyArchRegs(unverifiedInst->tcBase());
// Also advance the PC. Hopefully no PC-based events happened.

28
src/cpu/inorder/cpu.cc
View file

@ -158,7 +158,7 @@ void
InOrderCPU::CPUEvent::scheduleEvent(int delay)
{
assert(!scheduled() || squashed());
cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
void
@ -337,7 +337,7 @@ InOrderCPU::InOrderCPU(Params *params)
dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyBufferInst->setSquashed();
lastRunningCycle = curTick;
lastRunningCycle = curTick();
// Reset CPU to reset state.
#if FULL_SYSTEM
@ -528,17 +528,17 @@ InOrderCPU::tick()
if (!tickEvent.scheduled()) {
if (_status == SwitchedOut) {
// increment stat
lastRunningCycle = curTick;
lastRunningCycle = curTick();
} else if (!activityRec.active()) {
DPRINTF(InOrderCPU, "sleeping CPU.\n");
lastRunningCycle = curTick;
lastRunningCycle = curTick();
timesIdled++;
} else {
//Tick next_tick = curTick + cycles(1);
//Tick next_tick = curTick() + cycles(1);
//tickEvent.schedule(next_tick);
schedule(&tickEvent, nextCycle(curTick + 1));
schedule(&tickEvent, nextCycle(curTick() + 1));
DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
nextCycle(curTick + 1));
nextCycle(curTick() + 1));
}
}
@ -693,10 +693,10 @@ InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
event_pri_offset);
Tick sked_tick = nextCycle(curTick + ticks(delay));
Tick sked_tick = nextCycle(curTick() + ticks(delay));
if (delay >= 0) {
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
eventNames[c_event], curTick + delay, tid);
eventNames[c_event], curTick() + delay, tid);
schedule(cpu_event, sked_tick);
} else {
cpu_event->process();
@ -791,7 +791,7 @@ InOrderCPU::activateThread(ThreadID tid)
activateThreadInPipeline(tid);
thread[tid]->lastActivate = curTick;
thread[tid]->lastActivate = curTick();
tcBase(tid)->setStatus(ThreadContext::Active);
@ -963,7 +963,7 @@ InOrderCPU::suspendThread(ThreadID tid)
tid);
deactivateThread(tid);
suspendedThreads.push_back(tid);
thread[tid]->lastSuspend = curTick;
thread[tid]->lastSuspend = curTick();
tcBase(tid)->setStatus(ThreadContext::Suspended);
}
@ -1124,7 +1124,7 @@ InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
// Finalize Trace Data For Instruction
if (inst->traceData) {
//inst->traceData->setCycle(curTick);
//inst->traceData->setCycle(curTick());
inst->traceData->setFetchSeq(inst->seqNum);
//inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
inst->traceData->dump();
@ -1390,7 +1390,7 @@ InOrderCPU::wakeCPU()
DPRINTF(Activity, "Waking up CPU\n");
Tick extra_cycles = tickToCycles((curTick - 1) - lastRunningCycle);
Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
idleCycles += extra_cycles;
for (int stage_num = 0; stage_num < NumStages; stage_num++) {
@ -1399,7 +1399,7 @@ InOrderCPU::wakeCPU()
numCycles += extra_cycles;
schedule(&tickEvent, nextCycle(curTick));
schedule(&tickEvent, nextCycle(curTick()));
}
#if FULL_SYSTEM

2
src/cpu/inorder/cpu.hh
View file

@ -157,7 +157,7 @@ class InOrderCPU : public BaseCPU
void scheduleTickEvent(int delay)
{
assert(!tickEvent.scheduled() || tickEvent.squashed());
reschedule(&tickEvent, nextCycle(curTick + ticks(delay)), true);
reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
}
/** Unschedule tick event, regardless of its current state. */

8
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -442,7 +442,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
"being set to %#x.\n", threadNumber, seqNum, idx, val);
@ -472,7 +472,7 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Int Reg. %i "
"being set to %#x (result-tick:%i).\n",
@ -485,7 +485,7 @@ InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
instResult[idx].val.dbl = val;
instResult[idx].type = Float;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",
@ -499,7 +499,7 @@ InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
instResult[idx].tick = curTick();
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Result Float Reg. %i "
"being set to %#x (result-tick:%i).\n",

10
src/cpu/inorder/pipeline_stage.cc
View file

@ -338,7 +338,7 @@ void
PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
if (cpu->squashSeqNum[tid] < inst->seqNum &&
cpu->lastSquashCycle[tid] == curTick){
cpu->lastSquashCycle[tid] == curTick()){
DPRINTF(Resource, "Ignoring [sn:%i] branch squash signal due to "
"another stage's squash signal for after [sn:%i].\n",
inst->seqNum, cpu->squashSeqNum[tid]);
@ -371,7 +371,7 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
// Save squash num for later stage use
cpu->squashSeqNum[tid] = squash_seq_num;
cpu->lastSquashCycle[tid] = curTick;
cpu->lastSquashCycle[tid] = curTick();
}
}
@ -969,7 +969,7 @@ PipelineStage::processInstSchedule(DynInstPtr inst,int &reqs_processed)
inst->popSchedEntry();
} else {
panic("%i: encountered %s fault!\n",
curTick, req->fault->name());
curTick(), req->fault->name());
}
reqs_processed++;
@ -1075,7 +1075,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
if (nextStageQueueValid(inst->nextStage - 1)) {
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, skipping "
"insertion into stage %i queue.\n", tid, inst->seqNum,
inst->nextStage);
@ -1107,7 +1107,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
// Take note of trace data for this inst & stage
if (inst->traceData) {
inst->traceData->setStageCycle(stageNum, curTick);
inst->traceData->setStageCycle(stageNum, curTick());
}
}

4
src/cpu/inorder/reg_dep_map.cc
View file

@ -181,14 +181,14 @@ RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst)
assert(dest_reg_idx != -1);
if (forward_inst->isExecuted() &&
forward_inst->readResultTime(dest_reg_idx) < curTick) {
forward_inst->readResultTime(dest_reg_idx) < curTick()) {
return forward_inst;
} else {
if (!forward_inst->isExecuted()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] has not been executed yet.\n",
inst->seqNum, forward_inst->seqNum);
} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick) {
} else if (forward_inst->readResultTime(dest_reg_idx) >= curTick()) {
DPRINTF(RegDepMap, "[sn:%i] Can't get value through "
"forwarding, [sn:%i] executed on tick:%i.\n",
inst->seqNum, forward_inst->seqNum,

4
src/cpu/inorder/resource.cc
View file

@ -366,7 +366,7 @@ Resource::scheduleEvent(int slot_idx, int delay)
DPRINTF(Resource, "[tid:%i]: Scheduling event for [sn:%i] on tick %i.\n",
reqMap[slot_idx]->inst->readTid(),
reqMap[slot_idx]->inst->seqNum,
cpu->ticks(delay) + curTick);
cpu->ticks(delay) + curTick());
resourceEvent[slot_idx].scheduleEvent(delay);
}
@ -504,5 +504,5 @@ ResourceEvent::scheduleEvent(int delay)
{
assert(!scheduled() || squashed());
resource->cpu->reschedule(this,
curTick + resource->ticks(delay), true);
curTick() + resource->ticks(delay), true);
}

20
src/cpu/inorder/resource_pool.9stage.cc
View file

@ -177,13 +177,13 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@ -192,7 +192,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case InOrderCPU::DeallocateThread:
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
@ -200,7 +200,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
inst->bdelaySeqNum,
tid);
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@ -208,14 +208,14 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->seqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@ -223,13 +223,13 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
res_pool_event->setEvent(e_type,
inst,
inst->squashingStage,
inst->bdelaySeqNum,
inst->readTid());
res_pool_event->schedule(curTick + cpu->cycles(delay));
res_pool_event->schedule(curTick() + cpu->cycles(delay));
}
break;
@ -345,9 +345,9 @@ void
ResourcePool::ResPoolEvent::scheduleEvent(int delay)
{
if (squashed())
reschedule(curTick + resPool->cpu->cycles(delay));
reschedule(curTick() + resPool->cpu->cycles(delay));
else if (!scheduled())
schedule(curTick + resPool->cpu->cycles(delay));
schedule(curTick() + resPool->cpu->cycles(delay));
}
/** Unschedule resource event, regardless of its current state. */

16
src/cpu/inorder/resource_pool.cc
View file

@ -244,14 +244,14 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
assert(delay >= 0);
Tick when = cpu->nextCycle(curTick + cpu->ticks(delay));
Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
switch (e_type)
{
case InOrderCPU::ActivateThread:
{
DPRINTF(Resource, "Scheduling Activate Thread Resource Pool Event "
"for tick %i, [tid:%i].\n", curTick + delay,
"for tick %i, [tid:%i].\n", curTick() + delay,
inst->readTid());
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
@ -269,7 +269,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling Deactivate Thread Resource Pool "
"Event for tick %i.\n", curTick + delay);
"Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,
e_type,
@ -304,7 +304,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::InstGraduated:
{
DPRINTF(Resource, "Scheduling Inst-Graduated Resource Pool "
"Event for tick %i.\n", curTick + delay);
"Event for tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@ -318,7 +318,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
case ResourcePool::SquashAll:
{
DPRINTF(Resource, "Scheduling Squash Resource Pool Event for "
"tick %i.\n", curTick + delay);
"tick %i.\n", curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@ -333,7 +333,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling Squash Due to Memory Stall Resource "
"Pool Event for tick %i.\n",
curTick + delay);
curTick() + delay);
ResPoolEvent *res_pool_event =
new ResPoolEvent(this,e_type,
inst,
@ -348,7 +348,7 @@ ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
{
DPRINTF(Resource, "Scheduling UpdatePC Resource Pool Event "
"for tick %i.\n",
curTick + delay);
curTick() + delay);
ResPoolEvent *res_pool_event = new ResPoolEvent(this,e_type,
inst,
inst->squashingStage,
@ -542,7 +542,7 @@ ResourcePool::ResPoolEvent::scheduleEvent(int delay)
{
InOrderCPU *cpu = resPool->cpu;
assert(!scheduled() || squashed());
cpu->reschedule(this, cpu->nextCycle(curTick + cpu->ticks(delay)), true);
cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
}
/** Unschedule resource event, regardless of its current state. */

4
src/cpu/inorder/resources/branch_predictor.cc
View file

@ -80,7 +80,7 @@ BranchPredictor::execute(int slot_num)
case PredictBranch:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping prediction \n", tid, inst->seqNum);
} else {
@ -125,7 +125,7 @@ BranchPredictor::execute(int slot_num)
case UpdatePredictor:
{
if (inst->seqNum > cpu->squashSeqNum[tid] &&
curTick == cpu->lastSquashCycle[tid]) {
curTick() == cpu->lastSquashCycle[tid]) {
DPRINTF(InOrderStage, "[tid:%u]: [sn:%i]: squashed, "
"skipping branch predictor update \n",
tid, inst->seqNum);

8
src/cpu/inorder/resources/cache_unit.cc
View file

@ -63,7 +63,7 @@ Tick
CacheUnit::CachePort::recvAtomic(PacketPtr pkt)
{
panic("CacheUnit::CachePort doesn't expect recvAtomic callback!");
return curTick;
return curTick();
}
void
@ -167,7 +167,7 @@ CacheUnit::getSlot(DynInstPtr inst)
if (new_slot == -1)
return -1;
inst->memTime = curTick;
inst->memTime = curTick();
setAddrDependency(inst);
return new_slot;
} else {
@ -343,7 +343,7 @@ CacheUnit::getRequest(DynInstPtr inst, int stage_num, int res_idx,
break;
default:
panic("%i: Unexpected request type (%i) to %s", curTick,
panic("%i: Unexpected request type (%i) to %s", curTick(),
sched_entry->cmd, name());
}
@ -482,7 +482,7 @@ CacheUnit::read(DynInstPtr inst, Addr addr,
if (secondAddr > addr && !inst->split2ndAccess) {
DPRINTF(InOrderCachePort, "%i: sn[%i] Split Read Access (1 of 2) for "
"(%#x, %#x).\n", curTick, inst->seqNum, addr, secondAddr);
"(%#x, %#x).\n", curTick(), inst->seqNum, addr, secondAddr);
// Save All "Total" Split Information
// ==============================

6
src/cpu/inorder/resources/execution_unit.cc
View file

@ -55,7 +55,7 @@ ExecutionUnit::regStats()
.name(name() + ".predictedNotTakenIncorrect")
.desc("Number of Branches Incorrectly Predicted As Not Taken).");
lastExecuteCycle = curTick;
lastExecuteCycle = curTick();
executions
.name(name() + ".executions")
@ -98,8 +98,8 @@ ExecutionUnit::execute(int slot_num)
{
case ExecuteInst:
{
if (curTick != lastExecuteCycle) {
lastExecuteCycle = curTick;
if (curTick() != lastExecuteCycle) {
lastExecuteCycle = curTick();
}

4
src/cpu/inorder/resources/fetch_seq_unit.cc
View file

@ -210,13 +210,13 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
}
if (squashSeqNum[tid] <= done_seq_num &&
lastSquashCycle[tid] == curTick) {
lastSquashCycle[tid] == curTick()) {
DPRINTF(InOrderFetchSeq, "[tid:%i]: Ignoring squash from stage %i, "
"since there is an outstanding squash that is older.\n",
tid, squash_stage);
} else {
squashSeqNum[tid] = done_seq_num;
lastSquashCycle[tid] = curTick;
lastSquashCycle[tid] = curTick();
// If The very next instruction number is the done seq. num,
// then we haven't seen the delay slot yet ... if it isn't

6
src/cpu/inorder/resources/graduation_unit.cc
View file

@ -64,8 +64,8 @@ GraduationUnit::execute(int slot_num)
// @TODO: Instructions should never really get to this point since
// this should be handled through the request interface. Check to
// make sure this happens and delete this code.
if (lastCycleGrad != curTick) {
lastCycleGrad = curTick;
if (lastCycleGrad != curTick()) {
lastCycleGrad = curTick();
numCycleGrad = 0;
} else if (numCycleGrad > width) {
DPRINTF(InOrderGraduation,
@ -91,7 +91,7 @@ GraduationUnit::execute(int slot_num)
}
if (inst->traceData) {
inst->traceData->setStageCycle(stage_num, curTick);
inst->traceData->setStageCycle(stage_num, curTick());
}
// Tell CPU that instruction is finished processing

4
src/cpu/inorder/resources/mult_div_unit.cc
View file

@ -163,7 +163,7 @@ MultDivUnit::getSlot(DynInstPtr inst)
}
}
if (lastMDUCycle + repeat_rate > curTick) {
if (lastMDUCycle + repeat_rate > curTick()) {
DPRINTF(InOrderMDU, "MDU not ready to process another inst. until %i, "
"denying request.\n", lastMDUCycle + repeat_rate);
return -1;
@ -173,7 +173,7 @@ MultDivUnit::getSlot(DynInstPtr inst)
rval);
if (rval != -1) {
lastMDUCycle = curTick;
lastMDUCycle = curTick();
lastOpType = inst->opClass();
lastInstName = inst->staticInst->getName();
}

2
src/cpu/o3/commit_impl.hh
View file

@ -475,7 +475,7 @@ DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
TrapEvent *trap = new TrapEvent(this, tid);
cpu->schedule(trap, curTick + trapLatency);
cpu->schedule(trap, curTick() + trapLatency);
trapInFlight[tid] = true;
}

20
src/cpu/o3/cpu.cc
View file

@ -334,7 +334,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
// Setup the ROB for whichever stages need it.
commit.setROB(&rob);
lastRunningCycle = curTick;
lastRunningCycle = curTick();
lastActivatedCycle = -1;
#if 0
@ -538,13 +538,13 @@ FullO3CPU<Impl>::tick()
getState() == SimObject::Drained) {
DPRINTF(O3CPU, "Switched out!\n");
// increment stat
lastRunningCycle = curTick;
lastRunningCycle = curTick();
} else if (!activityRec.active() || _status == Idle) {
DPRINTF(O3CPU, "Idle!\n");
lastRunningCycle = curTick;
lastRunningCycle = curTick();
timesIdled++;
} else {
schedule(tickEvent, nextCycle(curTick + ticks(1)));
schedule(tickEvent, nextCycle(curTick() + ticks(1)));
DPRINTF(O3CPU, "Scheduling next tick!\n");
}
}
@ -639,13 +639,13 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
// Needs to set each stage to running as well.
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
"on cycle %d\n", tid, curTick + ticks(delay));
"on cycle %d\n", tid, curTick() + ticks(delay));
scheduleActivateThreadEvent(tid, delay);
} else {
activateThread(tid);
}
if (lastActivatedCycle < curTick) {
if (lastActivatedCycle < curTick()) {
scheduleTickEvent(delay);
// Be sure to signal that there's some activity so the CPU doesn't
@ -653,7 +653,7 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
lastActivatedCycle = curTick;
lastActivatedCycle = curTick();
_status = Running;
}
@ -666,7 +666,7 @@ FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
// Schedule removal of thread data from CPU
if (delay){
DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
"on cycle %d\n", tid, curTick + ticks(delay));
"on cycle %d\n", tid, curTick() + ticks(delay));
scheduleDeallocateContextEvent(tid, remove, delay);
return false;
} else {
@ -1552,8 +1552,8 @@ FullO3CPU<Impl>::wakeCPU()
DPRINTF(Activity, "Waking up CPU\n");
idleCycles += tickToCycles((curTick - 1) - lastRunningCycle);
numCycles += tickToCycles((curTick - 1) - lastRunningCycle);
idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
schedule(tickEvent, nextCycle());
}

12
src/cpu/o3/cpu.hh
View file

@ -140,9 +140,9 @@ class FullO3CPU : public BaseO3CPU
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
reschedule(tickEvent, nextCycle(curTick + ticks(delay)));
reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
else if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle(curTick + ticks(delay)));
schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
}
/** Unschedule tick event, regardless of its current state. */
@ -182,10 +182,10 @@ class FullO3CPU : public BaseO3CPU
// Schedule thread to activate, regardless of its current state.
if (activateThreadEvent[tid].squashed())
reschedule(activateThreadEvent[tid],
nextCycle(curTick + ticks(delay)));
nextCycle(curTick() + ticks(delay)));
else if (!activateThreadEvent[tid].scheduled())
schedule(activateThreadEvent[tid],
nextCycle(curTick + ticks(delay)));
nextCycle(curTick() + ticks(delay)));
}
/** Unschedule actiavte thread event, regardless of its current state. */
@ -235,10 +235,10 @@ class FullO3CPU : public BaseO3CPU
// Schedule thread to activate, regardless of its current state.
if (deallocateContextEvent[tid].squashed())
reschedule(deallocateContextEvent[tid],
nextCycle(curTick + ticks(delay)));
nextCycle(curTick() + ticks(delay)));
else if (!deallocateContextEvent[tid].scheduled())
schedule(deallocateContextEvent[tid],
nextCycle(curTick + ticks(delay)));
nextCycle(curTick() + ticks(delay)));
}
/** Unschedule thread deallocation in CPU */

6
src/cpu/o3/fetch_impl.hh
View file

@ -68,7 +68,7 @@ Tick
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
{
panic("DefaultFetch doesn't expect recvAtomic callback!");
return curTick;
return curTick();
}
template<class Impl>
@ -625,7 +625,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, Fault &ret_fault, ThreadID tid,
DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
lastIcacheStall[tid] = curTick;
lastIcacheStall[tid] = curTick();
DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
"response.\n", tid);
@ -992,7 +992,7 @@ DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
#if TRACING_ON
if (trace) {
instruction->traceData =
cpu->getTracer()->getInstRecord(curTick, cpu->tcBase(tid),
cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
instruction->staticInst, thisPC, curMacroop);
}
#else

2
src/cpu/o3/inst_queue_impl.hh
View file

@ -754,7 +754,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
FUCompletion *execution = new FUCompletion(issuing_inst,
idx, this);
cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1));
cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
// @todo: Enforce that issue_latency == 1 or op_latency
if (issue_latency > 1) {

2
src/cpu/o3/lsq_impl.hh
View file

@ -55,7 +55,7 @@ Tick
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
{
panic("O3CPU model does not work with atomic mode!");
return curTick;
return curTick();
}
template <class Impl>

2
src/cpu/o3/lsq_unit.hh
View file

@ -624,7 +624,7 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// @todo: Need to make this a parameter.
cpu->schedule(wb, curTick);
cpu->schedule(wb, curTick());
// Don't need to do anything special for split loads.
if (TheISA::HasUnalignedMemAcc && sreqLow) {

2
src/cpu/o3/lsq_unit_impl.hh
View file

@ -783,7 +783,7 @@ LSQUnit<Impl>::writebackStores()
"Instantly completing it.\n",
inst->seqNum);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
cpu->schedule(wb, curTick + 1);
cpu->schedule(wb, curTick() + 1);
completeStore(storeWBIdx);
incrStIdx(storeWBIdx);
continue;

6
src/cpu/o3/thread_context_impl.hh
View file

@ -115,7 +115,7 @@ O3ThreadContext<Impl>::activate(int delay)
return;
#if FULL_SYSTEM
thread->lastActivate = curTick;
thread->lastActivate = curTick();
#endif
thread->setStatus(ThreadContext::Active);
@ -135,8 +135,8 @@ O3ThreadContext<Impl>::suspend(int delay)
return;
#if FULL_SYSTEM
thread->lastActivate = curTick;
thread->lastSuspend = curTick;
thread->lastActivate = curTick();
thread->lastSuspend = curTick();
#endif
/*
#if FULL_SYSTEM

8
src/cpu/ozone/back_end.hh
View file

@ -468,7 +468,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Read;
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->time = curTick();
memReq->flags &= ~INST_READ;
MemAccessResult result = dcacheInterface->access(memReq);
@ -481,7 +481,7 @@ BackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
--funcExeInst;
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");
@ -510,7 +510,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
memReq->cmd = Write;
memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->time = curTick();
memReq->flags &= ~INST_READ;
MemAccessResult result = dcacheInterface->access(memReq);
@ -519,7 +519,7 @@ BackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
// status = DcacheMissStall;
DPRINTF(OzoneCPU, "Dcache miss stall!\n");

4
src/cpu/ozone/cpu.hh
View file

@ -277,9 +277,9 @@ class OzoneCPU : public BaseCPU
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
tickEvent.reschedule(curTick + ticks(delay));
tickEvent.reschedule(curTick() + ticks(delay));
else if (!tickEvent.scheduled())
tickEvent.schedule(curTick + ticks(delay));
tickEvent.schedule(curTick() + ticks(delay));
}
/// Unschedule tick event, regardless of its current state.

4
src/cpu/ozone/cpu_impl.hh
View file

@ -301,7 +301,7 @@ OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
if (tc->status() == ThreadContext::Active &&
_status != Running) {
_status = Running;
tickEvent.schedule(curTick);
tickEvent.schedule(curTick());
}
}
// Nothing running, change status to reflect that we're no longer
@ -525,7 +525,7 @@ OzoneCPU<Impl>::tick()
comInstEventQueue[0]->serviceEvents(numInst);
if (!tickEvent.scheduled() && _status == Running)
tickEvent.schedule(curTick + ticks(1));
tickEvent.schedule(curTick() + ticks(1));
}
template <class Impl>

6
src/cpu/ozone/front_end_impl.hh
View file

@ -52,7 +52,7 @@ Tick
FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
{
panic("FrontEnd doesn't expect recvAtomic callback!");
return curTick;
return curTick();
}
template<class Impl>
@ -432,7 +432,7 @@ FrontEnd<Impl>::tick()
#if FULL_SYSTEM
if (inst->isQuiesce()) {
// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
status = QuiescePending;
break;
}
@ -894,7 +894,7 @@ FrontEnd<Impl>::getInstFromCacheline()
instruction->staticInst->disassemble(PC));
instruction->traceData =
Trace::getInstRecord(curTick, tc,
Trace::getInstRecord(curTick(), tc,
instruction->staticInst,
instruction->readPC());

18
src/cpu/ozone/inorder_back_end.hh
View file

@ -210,7 +210,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
if (fault == NoFault && dcacheInterface) {
memReq->cmd = Read;
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->time = curTick();
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
@ -220,7 +220,7 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
// Fix this hack for keeping funcExeInst correct with loads that
// are executed twice.
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss stall!\n");
@ -246,7 +246,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
memReq->cmd = Write;
// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
memReq->completionEvent = NULL;
memReq->time = curTick;
memReq->time = curTick();
MemAccessResult result = dcacheInterface->access(memReq);
// Ugly hack to get an event scheduled *only* if the access is
@ -254,7 +254,7 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
// at some point.
if (result != MA_HIT) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss stall!\n");
@ -280,7 +280,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Read;
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
Fault fault = cpu->read(req, data);
@ -295,7 +295,7 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
// at some point.
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissLoadStall;
DPRINTF(IBE, "Dcache miss load stall!\n");
@ -320,7 +320,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
req->cmd = Write;
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
memcpy(req->data, (uint8_t *)&data, req->size);
@ -347,7 +347,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
req->data = new uint8_t[64];
memcpy(req->data,(uint8_t *)&data,req->size);
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
MemAccessResult result = dcacheInterface->access(req);
// Ugly hack to get an event scheduled *only* if the access is
@ -355,7 +355,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
// at some point.
if (result != MA_HIT) {
req->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
lastDcacheStall = curTick();
// unscheduleTickEvent();
status = DcacheMissStoreStall;
DPRINTF(IBE, "Dcache miss store stall!\n");

2
src/cpu/ozone/inst_queue_impl.hh
View file

@ -673,7 +673,7 @@ InstQueue<Impl>::scheduleReadyInsts()
FUCompletion *execution = new FUCompletion(issuing_inst,
idx, this);
execution->schedule(curTick + issue_latency - 1);
execution->schedule(curTick() + issue_latency - 1);
} else {
i2e_info->insts[exec_queue_slot++] = issuing_inst;
i2e_info->size++;

8
src/cpu/ozone/lsq_unit.hh
View file

@ -485,7 +485,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
req->cmd = Read;
assert(!req->completionEvent);
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
@ -502,7 +502,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// FIXME - Need to make this a parameter.
wb->schedule(curTick);
wb->schedule(curTick());
// Should keep track of stat for forwarded data
return NoFault;
@ -562,7 +562,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
// Setup MemReq pointer
req->cmd = Read;
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
@ -585,7 +585,7 @@ OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
inst->seqNum);
lastDcacheStall = curTick;
lastDcacheStall = curTick();
_status = DcacheMissStall;

6
src/cpu/ozone/lsq_unit_impl.hh
View file

@ -557,7 +557,7 @@ OzoneLSQ<Impl>::writebackStores()
// Fault fault = cpu->translateDataReadReq(req);
req->cmd = Write;
req->completionEvent = NULL;
req->time = curTick;
req->time = curTick();
assert(!req->data);
req->data = new uint8_t[64];
memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
@ -615,7 +615,7 @@ OzoneLSQ<Impl>::writebackStores()
req->completionEvent = new
StoreCompletionEvent(storeWBIdx, wb, this);
lastDcacheStall = curTick;
lastDcacheStall = curTick();
_status = DcacheMissStall;
@ -637,7 +637,7 @@ OzoneLSQ<Impl>::writebackStores()
typename BackEnd::LdWritebackEvent *wb =
new typename BackEnd::LdWritebackEvent(storeQueue[storeWBIdx].inst,
be);
wb->schedule(curTick);
wb->schedule(curTick());
}
completeStore(storeWBIdx);

4
src/cpu/ozone/lw_back_end_impl.hh
View file

@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
TrapEvent *trap = new TrapEvent(this);
trap->schedule(curTick + cpu->ticks(latency));
trap->schedule(curTick() + cpu->ticks(latency));
thread->trapPending = true;
}
@ -1226,7 +1226,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
// Write the done sequence number here.
toIEW->doneSeqNum = inst->seqNum;
lastCommitCycle = curTick;
lastCommitCycle = curTick();
#if FULL_SYSTEM
int count = 0;

2
src/cpu/ozone/lw_lsq.hh
View file

@ -581,7 +581,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
// We'll say this has a 1 cycle load-store forwarding latency
// for now.
// @todo: Need to make this a parameter.
wb->schedule(curTick);
wb->schedule(curTick());
// Should keep track of stat for forwarded data
return NoFault;

4
src/cpu/ozone/lw_lsq_impl.hh
View file

@ -65,7 +65,7 @@ Tick
OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
{
panic("O3CPU model does not work with atomic mode!");
return curTick;
return curTick();
}
template <class Impl>
@ -677,7 +677,7 @@ OzoneLWLSQ<Impl>::writebackStores()
be->addDcacheMiss(inst);
lastDcacheStall = curTick;
lastDcacheStall = curTick();
_status = DcacheMissStall;

2
src/cpu/pc_event.cc
View file

@ -111,7 +111,7 @@ PCEventQueue::dump() const
const_iterator e = pc_map.end();
for (; i != e; ++i)
cprintf("%d: event at %#x: %s\n", curTick, (*i)->pc(),
cprintf("%d: event at %#x: %s\n", curTick(), (*i)->pc(),
(*i)->descr());
}

4
src/cpu/simple/atomic.cc
View file

@ -267,7 +267,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
//Make sure ticks are still on multiples of cycles
schedule(tickEvent, nextCycle(curTick + ticks(delay)));
schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
_status = Running;
}
@ -731,7 +731,7 @@ AtomicSimpleCPU::tick()
latency = ticks(1);
if (_status != Idle)
schedule(tickEvent, curTick + latency);
schedule(tickEvent, curTick() + latency);
}

2
src/cpu/simple/base.cc
View file

@ -330,7 +330,7 @@ BaseSimpleCPU::preExecute()
if(curStaticInst)
{
#if TRACING_ON
traceData = tracer->getInstRecord(curTick, tc,
traceData = tracer->getInstRecord(curTick(), tc,
curStaticInst, thread->pcState(), curMacroStaticInst);
DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",

40
src/cpu/simple/timing.cc
View file

@ -85,7 +85,7 @@ Tick
TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
return curTick();
}
void
@ -189,7 +189,7 @@ TimingSimpleCPU::switchOut()
{
assert(_status == Running || _status == Idle);
_status = SwitchedOut;
numCycles += tickToCycles(curTick - previousTick);
numCycles += tickToCycles(curTick() - previousTick);
// If we've been scheduled to resume but are then told to switch out,
// we'll need to cancel it.
@ -217,7 +217,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
_status = Idle;
}
assert(threadContexts.size() == 1);
previousTick = curTick;
previousTick = curTick();
}
@ -235,7 +235,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
_status = Running;
// kick things off by initiating the fetch of the next instruction
schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
}
@ -266,7 +266,7 @@ TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
if (req->isMmapedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, nextCycle(curTick + delay));
new IprEvent(pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(pkt)) {
@ -355,8 +355,8 @@ TimingSimpleCPU::translationFault(Fault fault)
{
// fault may be NoFault in cases where a fault is suppressed,
// for instance prefetches.
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
numCycles += tickToCycles(curTick() - previousTick);
previousTick = curTick();
if (traceData) {
// Since there was a fault, we shouldn't trace this instruction.
@ -538,7 +538,7 @@ TimingSimpleCPU::handleWritePacket()
if (req->isMmapedIpr()) {
Tick delay;
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
_status = DcacheWaitResponse;
dcache_pkt = NULL;
} else if (!dcachePort.sendTiming(dcache_pkt)) {
@ -726,8 +726,8 @@ TimingSimpleCPU::fetch()
_status = IcacheWaitResponse;
completeIfetch(NULL);
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
numCycles += tickToCycles(curTick() - previousTick);
previousTick = curTick();
}
}
@ -754,8 +754,8 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
advanceInst(fault);
}
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
numCycles += tickToCycles(curTick() - previousTick);
previousTick = curTick();
}
@ -787,8 +787,8 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
_status = Running;
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
numCycles += tickToCycles(curTick() - previousTick);
previousTick = curTick();
if (getState() == SimObject::Draining) {
if (pkt) {
@ -862,9 +862,9 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse() && !pkt->wasNacked()) {
// delay processing of returned data until next CPU clock edge
Tick next_tick = cpu->nextCycle(curTick);
Tick next_tick = cpu->nextCycle(curTick());
if (next_tick == curTick)
if (next_tick == curTick())
cpu->completeIfetch(pkt);
else
tickEvent.schedule(pkt, next_tick);
@ -906,8 +906,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
numCycles += tickToCycles(curTick() - previousTick);
previousTick = curTick();
if (pkt->senderState) {
SplitFragmentSenderState * send_state =
@ -994,9 +994,9 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
{
if (pkt->isResponse() && !pkt->wasNacked()) {
// delay processing of returned data until next CPU clock edge
Tick next_tick = cpu->nextCycle(curTick);
Tick next_tick = cpu->nextCycle(curTick());
if (next_tick == curTick) {
if (next_tick == curTick()) {
cpu->completeDataAccess(pkt);
} else {
if (!tickEvent.scheduled()) {

6
src/cpu/simple_thread.cc
View file

@ -234,7 +234,7 @@ SimpleThread::activate(int delay)
if (status() == ThreadContext::Active)
return;
lastActivate = curTick;
lastActivate = curTick();
// if (status() == ThreadContext::Unallocated) {
// cpu->activateWhenReady(_threadId);
@ -253,8 +253,8 @@ SimpleThread::suspend()
if (status() == ThreadContext::Suspended)
return;
lastActivate = curTick;
lastSuspend = curTick;
lastActivate = curTick();
lastSuspend = curTick();
/*
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts

2
src/cpu/static_inst.cc
View file

@ -51,7 +51,7 @@ StaticInst::~StaticInst()
void
StaticInst::dumpDecodeCacheStats()
{
cerr << "Decode hash table stats @ " << curTick << ":" << endl;
cerr << "Decode hash table stats @ " << curTick() << ":" << endl;
cerr << "\tnum entries = " << decodeCache.size() << endl;
cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl;
vector<int> hist(100, 0);

4
src/cpu/testers/directedtest/RubyDirectedTester.cc
View file

@ -114,7 +114,7 @@ RubyDirectedTester::hitCallback(NodeID proc, Addr addr)
addr);
generator->performCallback(proc, addr);
schedule(directedStartEvent, curTick);
schedule(directedStartEvent, curTick());
}
void
@ -122,7 +122,7 @@ RubyDirectedTester::wakeup()
{
if (m_requests_completed < m_requests_to_complete) {
if (!generator->initiate()) {
schedule(directedStartEvent, curTick + 1);
schedule(directedStartEvent, curTick() + 1);
}
} else {
exitSimLoop("Ruby DirectedTester completed");

12
src/cpu/testers/memtest/memtest.cc
View file

@ -69,14 +69,14 @@ MemTest::CpuPort::recvAtomic(PacketPtr pkt)
// must be snoop upcall
assert(pkt->isRequest());
assert(pkt->getDest() == Packet::Broadcast);
return curTick;
return curTick();
}
void
MemTest::CpuPort::recvFunctional(PacketPtr pkt)
{
//Do nothing if we see one come through
// if (curTick != 0)//Supress warning durring initialization
// if (curTick() != 0)//Supress warning durring initialization
// warn("Functional Writes not implemented in MemTester\n");
//Need to find any response values that intersect and update
return;
@ -220,7 +220,7 @@ MemTest::completeRequest(PacketPtr pkt)
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
panic("%s: read of %x (blk %x) @ cycle %d "
"returns %x, expected %x\n", name(),
req->getPaddr(), blockAddr(req->getPaddr()), curTick,
req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
*pkt_data, *data);
}
@ -229,7 +229,7 @@ MemTest::completeRequest(PacketPtr pkt)
if (numReads == (uint64_t)nextProgressMessage) {
ccprintf(cerr, "%s: completed %d read accesses @%d\n",
name(), numReads, curTick);
name(), numReads, curTick());
nextProgressMessage += progressInterval;
}
@ -272,13 +272,13 @@ void
MemTest::tick()
{
if (!tickEvent.scheduled())
schedule(tickEvent, curTick + ticks(1));
schedule(tickEvent, curTick() + ticks(1));
if (++noResponseCycles >= 500000) {
if (issueDmas) {
cerr << "DMA tester ";
}
cerr << name() << ": deadlocked at cycle " << curTick << endl;
cerr << name() << ": deadlocked at cycle " << curTick() << endl;
fatal("");
}

6
src/cpu/testers/rubytest/Check.cc
View file

@ -98,7 +98,7 @@ Check::initiatePrefetch()
}
// Prefetches are assumed to be 0 sized
Request *req = new Request(m_address.getAddress(), 0, flags, curTick,
Request *req = new Request(m_address.getAddress(), 0, flags, curTick(),
m_pc.getAddress());
PacketPtr pkt = new Packet(req, cmd, port->idx);
@ -139,7 +139,7 @@ Check::initiateAction()
Address writeAddr(m_address.getAddress() + m_store_count);
// Stores are assumed to be 1 byte-sized
Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick,
Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(),
m_pc.getAddress());
Packet::Command cmd;
@ -205,7 +205,7 @@ Check::initiateCheck()
// Checks are sized depending on the number of bytes written
Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
curTick, m_pc.getAddress());
curTick(), m_pc.getAddress());
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
uint8_t* dataArray = new uint8_t[CHECK_SIZE];

2
src/cpu/testers/rubytest/RubyTester.cc
View file

@ -160,7 +160,7 @@ RubyTester::wakeup()
checkForDeadlock();
schedule(checkStartEvent, curTick + m_wakeup_frequency);
schedule(checkStartEvent, curTick() + m_wakeup_frequency);
} else {
exitSimLoop("Ruby Tester completed");
}

8
src/cpu/trace/trace_cpu.cc
View file

@ -66,13 +66,13 @@ TraceCPU::tick()
int instReqs = 0;
int dataReqs = 0;
while (nextReq && curTick >= nextCycle) {
while (nextReq && curTick() >= nextCycle) {
assert(nextReq->thread_num < 4 && "Not enough threads");
if (nextReq->isInstFetch() && icacheInterface) {
if (icacheInterface->isBlocked())
break;
nextReq->time = curTick;
nextReq->time = curTick();
if (nextReq->cmd == Squash) {
icacheInterface->squash(nextReq->asid);
} else {
@ -91,7 +91,7 @@ TraceCPU::tick()
break;
++dataReqs;
nextReq->time = curTick;
nextReq->time = curTick();
if (dcacheInterface->doEvents()) {
nextReq->completionEvent =
new TraceCompleteEvent(nextReq, this);
@ -113,7 +113,7 @@ TraceCPU::tick()
tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
}
} else {
tickEvent.schedule(max(curTick + ticks(1), nextCycle));
tickEvent.schedule(max(curTick() + ticks(1), nextCycle));
}
}

2
src/dev/alpha/backdoor.cc
View file

@ -234,7 +234,7 @@ AlphaBackdoor::write(PacketPtr pkt)
default:
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
inform("Launching CPU %d @ %d", cpunum, curTick);
inform("Launching CPU %d @ %d", cpunum, curTick());
assert(val > 0 && "Must not access primary cpu");
if (cpunum >= 0 && cpunum < 64)
alphaAccess->cpuStack[cpunum] = val;

6
src/dev/arm/pl011.cc
View file

@ -187,7 +187,7 @@ Pl011::write(PacketPtr pkt)
DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
rawInt.txim = 1;
if (!intEvent.scheduled())
schedule(intEvent, curTick + intDelay);
schedule(intEvent, curTick() + intDelay);
}
break;
@ -217,7 +217,7 @@ Pl011::write(PacketPtr pkt)
DPRINTF(Uart, "Writing to IMSC: TX int enabled, scheduling interruptt\n");
rawInt.txim = 1;
if (!intEvent.scheduled())
schedule(intEvent, curTick + intDelay);
schedule(intEvent, curTick() + intDelay);
}
break;
@ -252,7 +252,7 @@ Pl011::dataAvailable()
DPRINTF(Uart, "Data available, scheduling interrupt\n");
if (!intEvent.scheduled())
schedule(intEvent, curTick + intDelay);
schedule(intEvent, curTick() + intDelay);
}
void

12
src/dev/arm/pl111.cc
View file

@ -355,7 +355,7 @@ Pl111::readFramebuffer()
startAddr = lcdUpbase;
}
curAddr = 0;
startTime = curTick;
startTime = curTick();
maxAddr = static_cast<Addr>(length*sizeof(uint32_t));
dmaPendingNum =0 ;
@ -388,9 +388,9 @@ Pl111::dmaDone()
DPRINTF(PL111, " -- DMA pending number %d\n", dmaPendingNum);
if (maxAddr == curAddr && !dmaPendingNum) {
if ((curTick - startTime) > maxFrameTime)
if ((curTick() - startTime) > maxFrameTime)
warn("CLCD controller buffer underrun, took %d cycles when should"
" have taken %d\n", curTick - startTime, maxFrameTime);
" have taken %d\n", curTick() - startTime, maxFrameTime);
// double buffering so the vnc server doesn't see a tear in the screen
memcpy(frameBuffer, dmaBuffer, maxAddr);
@ -400,7 +400,7 @@ Pl111::dmaDone()
writeBMP(frameBuffer);
DPRINTF(PL111, "-- schedule next dma read event at %d tick \n",
maxFrameTime + curTick);
maxFrameTime + curTick());
schedule(readEvent, nextCycle(startTime + maxFrameTime));
}
@ -415,7 +415,7 @@ Pl111::dmaDone()
Tick
Pl111::nextCycle()
{
Tick nextTick = curTick + clock - 1;
Tick nextTick = curTick() + clock - 1;
nextTick -= nextTick%clock;
return nextTick;
}
@ -427,7 +427,7 @@ Pl111::nextCycle(Tick beginTick)
if (nextTick%clock!=0)
nextTick = nextTick - (nextTick%clock) + clock;
assert(nextTick >= curTick);
assert(nextTick >= curTick());
return nextTick;
}

2
src/dev/arm/rv_ctrl.cc
View file

@ -62,7 +62,7 @@ RealViewCtrl::read(PacketPtr pkt)
break;
case Clock24:
Tick clk;
clk = (Tick)(curTick / (24 * SimClock::Float::MHz));
clk = (Tick)(curTick() / (24 * SimClock::Float::MHz));
pkt->set((uint32_t)(clk));
break;
case Flash:

6
src/dev/arm/timer_sp804.cc
View file

@ -93,7 +93,7 @@ Sp804::Timer::read(PacketPtr pkt, Addr daddr)
DPRINTF(Timer, "Event schedule for %d, clock=%d, prescale=%d\n",
zeroEvent.when(), clock, control.timerPrescale);
Tick time;
time = zeroEvent.when() - curTick;
time = zeroEvent.when() - curTick();
time = time / clock / power(16, control.timerPrescale);
DPRINTF(Timer, "-- returning counter at %d\n", time);
pkt->set<uint32_t>(time);
@ -188,8 +188,8 @@ Sp804::Timer::restartCounter(uint32_t val)
DPRINTF(Timer, "-- Event was already schedule, de-scheduling\n");
parent->deschedule(zeroEvent);
}
parent->schedule(zeroEvent, curTick + time);
DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick + time);
parent->schedule(zeroEvent, curTick() + time);
DPRINTF(Timer, "-- Scheduling new event for: %d\n", curTick() + time);
}
void

4
src/dev/etherbus.cc
View file

@ -87,7 +87,7 @@ bool
EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
{
if (busy()) {
DPRINTF(Ethernet, "ethernet packet not sent, bus busy\n", curTick);
DPRINTF(Ethernet, "ethernet packet not sent, bus busy\n", curTick());
return false;
}
@ -99,7 +99,7 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
int delay = (int)ceil(((double)pkt->length * ticksPerByte) + 1.0);
DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
delay, ticksPerByte);
schedule(event, curTick + delay);
schedule(event, curTick() + delay);
return true;
}

4
src/dev/etherdump.cc
View file

@ -94,8 +94,8 @@ void
EtherDump::dumpPacket(EthPacketPtr &packet)
{
pcap_pkthdr pkthdr;
pkthdr.seconds = curTick / SimClock::Int::s;
pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000);
pkthdr.seconds = curTick() / SimClock::Int::s;
pkthdr.microseconds = (curTick() / SimClock::Int::us) % ULL(1000000);
pkthdr.caplen = std::min(packet->length, maxlen);
pkthdr.len = packet->length;
stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr));

4
src/dev/etherlink.cc
View file

@ -154,7 +154,7 @@ EtherLink::Link::txDone()
if (linkDelay > 0) {
DPRINTF(Ethernet, "packet delayed: delay=%d\n", linkDelay);
Event *event = new LinkDelayEvent(this, packet);
parent->schedule(event, curTick + linkDelay);
parent->schedule(event, curTick() + linkDelay);
} else {
txComplete(packet);
}
@ -183,7 +183,7 @@ EtherLink::Link::transmit(EthPacketPtr pkt)
DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
delay, ticksPerByte);
parent->schedule(doneEvent, curTick + delay);
parent->schedule(doneEvent, curTick() + delay);
return true;
}

4
src/dev/ethertap.cc
View file

@ -246,7 +246,7 @@ EtherTap::process(int revent)
DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
packetBuffer.push(packet);
if (!txEvent.scheduled())
schedule(txEvent, curTick + retryTime);
schedule(txEvent, curTick() + retryTime);
} else if (dump) {
dump->dump(packet);
}
@ -269,7 +269,7 @@ EtherTap::retransmit()
}
if (!packetBuffer.empty() && !txEvent.scheduled())
schedule(txEvent, curTick + retryTime);
schedule(txEvent, curTick() + retryTime);
}
EtherInt*

30
src/dev/i8254xGBe.cc
View file

@ -695,11 +695,11 @@ IGbE::postInterrupt(IntTypes t, bool now)
Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(EthernetIntr,
"EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
curTick, regs.itr.interval(), itr_interval);
"EINT: postInterrupt() curTick(): %d itr: %d interval: %d\n",
curTick(), regs.itr.interval(), itr_interval);
if (regs.itr.interval() == 0 || now ||
lastInterrupt + itr_interval <= curTick) {
lastInterrupt + itr_interval <= curTick()) {
if (interEvent.scheduled()) {
deschedule(interEvent);
}
@ -763,7 +763,7 @@ IGbE::cpuPostInt()
intrPost();
lastInterrupt = curTick;
lastInterrupt = curTick();
}
void
@ -801,7 +801,7 @@ IGbE::chkInterrupt()
DPRINTF(Ethernet,
"Possibly scheduling interrupt because of imr write\n");
if (!interEvent.scheduled()) {
Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval();
Tick t = curTick() + SimClock::Int::ns * 256 * regs.itr.interval();
DPRINTF(Ethernet, "Scheduling for %d\n", t);
schedule(interEvent, t);
}
@ -888,7 +888,7 @@ IGbE::DescCache<T>::writeback(Addr aMask)
wbOut = max_to_wb;
assert(!wbDelayEvent.scheduled());
igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
igbe->anBegin(annSmWb, "Prepare Writeback Desc");
}
@ -898,7 +898,7 @@ IGbE::DescCache<T>::writeback1()
{
// If we're draining delay issuing this DMA
if (igbe->getState() != SimObject::Running) {
igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
igbe->schedule(wbDelayEvent, curTick() + igbe->wbDelay);
return;
}
@ -969,7 +969,7 @@ IGbE::DescCache<T>::fetchDescriptors()
curFetching = max_to_fetch;
assert(!fetchDelayEvent.scheduled());
igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
}
@ -979,7 +979,7 @@ IGbE::DescCache<T>::fetchDescriptors1()
{
// If we're draining delay issuing this DMA
if (igbe->getState() != SimObject::Running) {
igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
igbe->schedule(fetchDelayEvent, curTick() + igbe->fetchDelay);
return;
}
@ -1440,14 +1440,14 @@ IGbE::RxDescCache::pktComplete()
if (igbe->regs.rdtr.delay()) {
Tick delay = igbe->regs.rdtr.delay() * igbe->intClock();
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", delay);
igbe->reschedule(igbe->rdtrEvent, curTick + delay);
igbe->reschedule(igbe->rdtrEvent, curTick() + delay);
}
if (igbe->regs.radv.idv()) {
Tick delay = igbe->regs.radv.idv() * igbe->intClock();
DPRINTF(EthernetSM, "RXS: Scheduling ADV for %d\n", delay);
if (!igbe->radvEvent.scheduled()) {
igbe->schedule(igbe->radvEvent, curTick + delay);
igbe->schedule(igbe->radvEvent, curTick() + delay);
}
}
@ -1880,14 +1880,14 @@ IGbE::TxDescCache::pktComplete()
if (igbe->regs.tidv.idv()) {
Tick delay = igbe->regs.tidv.idv() * igbe->intClock();
DPRINTF(EthernetDesc, "setting tidv\n");
igbe->reschedule(igbe->tidvEvent, curTick + delay, true);
igbe->reschedule(igbe->tidvEvent, curTick() + delay, true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
Tick delay = igbe->regs.tadv.idv() * igbe->intClock();
DPRINTF(EthernetDesc, "setting tadv\n");
if (!igbe->tadvEvent.scheduled()) {
igbe->schedule(igbe->tadvEvent, curTick + delay);
igbe->schedule(igbe->tadvEvent, curTick() + delay);
}
}
}
@ -2039,7 +2039,7 @@ IGbE::restartClock()
{
if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
getState() == SimObject::Running)
schedule(tickEvent, (curTick / ticks(1)) * ticks(1) + ticks(1));
schedule(tickEvent, (curTick() / ticks(1)) * ticks(1) + ticks(1));
}
unsigned int
@ -2420,7 +2420,7 @@ IGbE::tick()
if (rxTick || txTick || txFifoTick)
schedule(tickEvent, curTick + ticks(1));
schedule(tickEvent, curTick() + ticks(1));
}
void

12
src/dev/ide_disk.cc
View file

@ -323,7 +323,7 @@ IdeDisk::doDmaTransfer()
dmaState, devState);
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
schedule(dmaTransferEvent, curTick + DMA_BACKOFF_PERIOD);
schedule(dmaTransferEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else
ctrl->dmaRead(curPrdAddr, sizeof(PrdEntry_t), &dmaPrdReadEvent,
@ -357,7 +357,7 @@ IdeDisk::doDmaDataRead()
DPRINTF(IdeDisk, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
diskDelay, totalDiskDelay);
schedule(dmaReadWaitEvent, curTick + totalDiskDelay);
schedule(dmaReadWaitEvent, curTick() + totalDiskDelay);
}
void
@ -403,7 +403,7 @@ IdeDisk::doDmaRead()
}
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
schedule(dmaReadWaitEvent, curTick + DMA_BACKOFF_PERIOD);
schedule(dmaReadWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaReadCG->done()) {
assert(dmaReadCG->complete() < MAX_DMA_SIZE);
@ -465,7 +465,7 @@ IdeDisk::doDmaDataWrite()
cmdBytesLeft -= SectorSize;
}
schedule(dmaWriteWaitEvent, curTick + totalDiskDelay);
schedule(dmaWriteWaitEvent, curTick() + totalDiskDelay);
}
void
@ -478,7 +478,7 @@ IdeDisk::doDmaWrite()
curPrd.getByteCount(), TheISA::PageBytes);
}
if (ctrl->dmaPending() || ctrl->getState() != SimObject::Running) {
schedule(dmaWriteWaitEvent, curTick + DMA_BACKOFF_PERIOD);
schedule(dmaWriteWaitEvent, curTick() + DMA_BACKOFF_PERIOD);
return;
} else if (!dmaWriteCG->done()) {
assert(dmaWriteCG->complete() < MAX_DMA_SIZE);
@ -553,7 +553,7 @@ IdeDisk::startDma(const uint32_t &prdTableBase)
dmaState = Dma_Transfer;
// schedule dma transfer (doDmaTransfer)
schedule(dmaTransferEvent, curTick + 1);
schedule(dmaTransferEvent, curTick() + 1);
}
void

6
src/dev/intel_8254_timer.cc
View file

@ -281,9 +281,9 @@ Intel8254Timer::Counter::CounterEvent::setTo(int clocks)
{
if (clocks == 0)
panic("Timer can't be set to go off instantly.\n");
DPRINTF(Intel8254Timer, "Timer set to curTick + %d\n",
DPRINTF(Intel8254Timer, "Timer set to curTick() + %d\n",
clocks * interval);
counter->parent->schedule(this, curTick + clocks * interval);
counter->parent->schedule(this, curTick() + clocks * interval);
}
int
@ -291,7 +291,7 @@ Intel8254Timer::Counter::CounterEvent::clocksLeft()
{
if (!scheduled())
return -1;
return (when() - curTick + interval - 1) / interval;
return (when() - curTick() + interval - 1) / interval;
}
const char *

14
src/dev/io_device.cc
View file

@ -121,7 +121,7 @@ DmaPort::recvTiming(PacketPtr pkt)
else if (backoffTime < maxBackoffDelay)
backoffTime <<= 1;
reschedule(backoffEvent, curTick + backoffTime, true);
reschedule(backoffEvent, curTick() + backoffTime, true);
DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime);
@ -144,7 +144,7 @@ DmaPort::recvTiming(PacketPtr pkt)
if (state->totBytes == state->numBytes) {
if (state->completionEvent) {
if (state->delay)
schedule(state->completionEvent, curTick + state->delay);
schedule(state->completionEvent, curTick() + state->delay);
else
state->completionEvent->process();
}
@ -212,9 +212,9 @@ DmaPort::recvRetry()
} while (!backoffTime && result && transmitList.size());
if (transmitList.size() && backoffTime && !inRetry) {
DPRINTF(DMA, "Scheduling backoff for %d\n", curTick+backoffTime);
DPRINTF(DMA, "Scheduling backoff for %d\n", curTick()+backoffTime);
if (!backoffEvent.scheduled())
schedule(backoffEvent, backoffTime + curTick);
schedule(backoffEvent, backoffTime + curTick());
}
DPRINTF(DMA, "TransmitList: %d, backoffTime: %d inRetry: %d es: %d\n",
transmitList.size(), backoffTime, inRetry,
@ -299,8 +299,8 @@ DmaPort::sendDma()
if (transmitList.size() && backoffTime && !inRetry &&
!backoffEvent.scheduled()) {
DPRINTF(DMA, "-- Scheduling backoff timer for %d\n",
backoffTime+curTick);
schedule(backoffEvent, backoffTime + curTick);
backoffTime+curTick());
schedule(backoffEvent, backoffTime + curTick());
}
} else if (state == Enums::atomic) {
transmitList.pop_front();
@ -322,7 +322,7 @@ DmaPort::sendDma()
if (state->totBytes == state->numBytes) {
if (state->completionEvent) {
assert(!state->completionEvent->scheduled());
schedule(state->completionEvent, curTick + lat + state->delay);
schedule(state->completionEvent, curTick() + lat + state->delay);
}
delete state;
delete pkt->req;

16
src/dev/mc146818.cc
View file

@ -214,9 +214,9 @@ MC146818::serialize(const string &base, ostream &os)
// save the timer tick and rtc clock tick values to correctly reschedule
// them during unserialize
//
Tick rtcTimerInterruptTickOffset = event.when() - curTick;
Tick rtcTimerInterruptTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
Tick rtcClockTickOffset = event.when() - curTick;
Tick rtcClockTickOffset = event.when() - curTick();
SERIALIZE_SCALAR(rtcClockTickOffset);
}
@ -234,30 +234,30 @@ MC146818::unserialize(const string &base, Checkpoint *cp,
//
Tick rtcTimerInterruptTickOffset;
UNSERIALIZE_SCALAR(rtcTimerInterruptTickOffset);
reschedule(event, curTick + rtcTimerInterruptTickOffset);
reschedule(event, curTick() + rtcTimerInterruptTickOffset);
Tick rtcClockTickOffset;
UNSERIALIZE_SCALAR(rtcClockTickOffset);
reschedule(tickEvent, curTick + rtcClockTickOffset);
reschedule(tickEvent, curTick() + rtcClockTickOffset);
}
MC146818::RTCEvent::RTCEvent(MC146818 * _parent, Tick i)
: parent(_parent), interval(i)
{
DPRINTF(MC146818, "RTC Event Initilizing\n");
parent->schedule(this, curTick + interval);
parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::scheduleIntr()
{
parent->schedule(this, curTick + interval);
parent->schedule(this, curTick() + interval);
}
void
MC146818::RTCEvent::process()
{
DPRINTF(MC146818, "RTC Timer Interrupt\n");
parent->schedule(this, curTick + interval);
parent->schedule(this, curTick() + interval);
parent->handleEvent();
}
@ -271,7 +271,7 @@ void
MC146818::RTCTickEvent::process()
{
DPRINTF(MC146818, "RTC clock tick\n");
parent->schedule(this, curTick + SimClock::Int::s);
parent->schedule(this, curTick() + SimClock::Int::s);
parent->tickClock();
}

2
src/dev/mc146818.hh
View file

@ -71,7 +71,7 @@ class MC146818 : public EventManager
RTCTickEvent(MC146818 * _parent) : parent(_parent)
{
parent->schedule(this, curTick + SimClock::Int::s);
parent->schedule(this, curTick() + SimClock::Int::s);
}
/** Event process to occur at interrupt*/

30
src/dev/ns_gige.cc
View file

@ -848,7 +848,7 @@ NSGigE::devIntrPost(uint32_t interrupts)
interrupts, regs.isr, regs.imr);
if ((regs.isr & regs.imr)) {
Tick when = curTick;
Tick when = curTick();
if ((regs.isr & regs.imr & ISR_NODELAY) == 0)
when += intrDelay;
postedInterrupts++;
@ -910,7 +910,7 @@ NSGigE::devIntrChangeMask()
regs.isr, regs.imr, regs.isr & regs.imr);
if (regs.isr & regs.imr)
cpuIntrPost(curTick);
cpuIntrPost(curTick());
else
cpuIntrClear();
}
@ -927,8 +927,8 @@ NSGigE::cpuIntrPost(Tick when)
* @todo this warning should be removed and the intrTick code should
* be fixed.
*/
assert(when >= curTick);
assert(intrTick >= curTick || intrTick == 0);
assert(when >= curTick());
assert(intrTick >= curTick() || intrTick == 0);
if (when > intrTick && intrTick != 0) {
DPRINTF(EthernetIntr, "don't need to schedule event...intrTick=%d\n",
intrTick);
@ -936,9 +936,9 @@ NSGigE::cpuIntrPost(Tick when)
}
intrTick = when;
if (intrTick < curTick) {
if (intrTick < curTick()) {
debug_break();
intrTick = curTick;
intrTick = curTick();
}
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
@ -953,7 +953,7 @@ NSGigE::cpuIntrPost(Tick when)
void
NSGigE::cpuInterrupt()
{
assert(intrTick == curTick);
assert(intrTick == curTick());
// Whether or not there's a pending interrupt, we don't care about
// it anymore
@ -1125,7 +1125,7 @@ NSGigE::rxKick()
next:
if (clock) {
if (rxKickTick > curTick) {
if (rxKickTick > curTick()) {
DPRINTF(EthernetSM, "receive kick exiting, can't run till %d\n",
rxKickTick);
@ -1133,7 +1133,7 @@ NSGigE::rxKick()
}
// Go to the next state machine clock tick.
rxKickTick = curTick + ticks(1);
rxKickTick = curTick() + ticks(1);
}
switch(rxDmaState) {
@ -1494,7 +1494,7 @@ NSGigE::transmit()
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
schedule(txEvent, curTick + retryTime);
schedule(txEvent, curTick() + retryTime);
}
}
@ -1573,14 +1573,14 @@ NSGigE::txKick()
next:
if (clock) {
if (txKickTick > curTick) {
if (txKickTick > curTick()) {
DPRINTF(EthernetSM, "transmit kick exiting, can't run till %d\n",
txKickTick);
goto exit;
}
// Go to the next state machine clock tick.
txKickTick = curTick + ticks(1);
txKickTick = curTick() + ticks(1);
}
switch(txDmaState) {
@ -2001,7 +2001,7 @@ NSGigE::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
reschedule(txEvent, curTick + ticks(1), true);
reschedule(txEvent, curTick() + ticks(1), true);
}
bool
@ -2259,7 +2259,7 @@ NSGigE::serialize(ostream &os)
* If there's a pending transmit, store the time so we can
* reschedule it later
*/
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
SERIALIZE_SCALAR(transmitTick);
/*
@ -2440,7 +2440,7 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
Tick transmitTick;
UNSERIALIZE_SCALAR(transmitTick);
if (transmitTick)
schedule(txEvent, curTick + transmitTick);
schedule(txEvent, curTick() + transmitTick);
/*
* unserialize receive address filter settings

26
src/dev/sinic.cc
View file

@ -618,7 +618,7 @@ Device::devIntrPost(uint32_t interrupts)
interrupts &= ~Regs::Intr_TxLow;
if (interrupts) {
Tick when = curTick;
Tick when = curTick();
if ((interrupts & Regs::Intr_NoDelay) == 0)
when += intrDelay;
cpuIntrPost(when);
@ -654,7 +654,7 @@ Device::devIntrChangeMask(uint32_t newmask)
regs.IntrStatus, regs.IntrMask, regs.IntrStatus & regs.IntrMask);
if (regs.IntrStatus & regs.IntrMask)
cpuIntrPost(curTick);
cpuIntrPost(curTick());
else
cpuIntrClear();
}
@ -671,8 +671,8 @@ Base::cpuIntrPost(Tick when)
* @todo this warning should be removed and the intrTick code should
* be fixed.
*/
assert(when >= curTick);
assert(intrTick >= curTick || intrTick == 0);
assert(when >= curTick());
assert(intrTick >= curTick() || intrTick == 0);
if (!cpuIntrEnable) {
DPRINTF(EthernetIntr, "interrupts not enabled.\n",
intrTick);
@ -686,9 +686,9 @@ Base::cpuIntrPost(Tick when)
}
intrTick = when;
if (intrTick < curTick) {
if (intrTick < curTick()) {
debug_break();
intrTick = curTick;
intrTick = curTick();
}
DPRINTF(EthernetIntr, "going to schedule an interrupt for intrTick=%d\n",
@ -703,7 +703,7 @@ Base::cpuIntrPost(Tick when)
void
Base::cpuInterrupt()
{
assert(intrTick == curTick);
assert(intrTick == curTick());
// Whether or not there's a pending interrupt, we don't care about
// it anymore
@ -759,7 +759,7 @@ Device::changeConfig(uint32_t newconf)
cpuIntrEnable = regs.Config & Regs::Config_IntEn;
if (cpuIntrEnable) {
if (regs.IntrStatus & regs.IntrMask)
cpuIntrPost(curTick);
cpuIntrPost(curTick());
} else {
cpuIntrClear();
}
@ -882,7 +882,7 @@ Device::rxKick()
DPRINTF(EthernetSM, "rxKick: rxState=%s (rxFifo.size=%d)\n",
RxStateStrings[rxState], rxFifo.size());
if (rxKickTick > curTick) {
if (rxKickTick > curTick()) {
DPRINTF(EthernetSM, "rxKick: exiting, can't run till %d\n",
rxKickTick);
return;
@ -1196,7 +1196,7 @@ Device::txKick()
DPRINTF(EthernetSM, "txKick: txState=%s (txFifo.size=%d)\n",
TxStateStrings[txState], txFifo.size());
if (txKickTick > curTick) {
if (txKickTick > curTick()) {
DPRINTF(EthernetSM, "txKick: exiting, can't run till %d\n",
txKickTick);
return;
@ -1317,7 +1317,7 @@ Device::transferDone()
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
reschedule(txEvent, curTick + ticks(1), true);
reschedule(txEvent, curTick() + ticks(1), true);
}
bool
@ -1573,7 +1573,7 @@ Device::serialize(std::ostream &os)
* If there's a pending transmit, store the time so we can
* reschedule it later
*/
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick : 0;
Tick transmitTick = txEvent.scheduled() ? txEvent.when() - curTick() : 0;
SERIALIZE_SCALAR(transmitTick);
}
@ -1708,7 +1708,7 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
Tick transmitTick;
UNSERIALIZE_SCALAR(transmitTick);
if (transmitTick)
schedule(txEvent, curTick + transmitTick);
schedule(txEvent, curTick() + transmitTick);
pioPort->sendStatusChange(Port::RangeChange);

14
src/dev/uart8250.cc
View file

@ -68,7 +68,7 @@ Uart8250::IntrEvent::process()
DPRINTF(Uart, "UART InterEvent, interrupting\n");
uart->platform->postConsoleInt();
uart->status |= intrBit;
uart->lastTxInt = curTick;
uart->lastTxInt = curTick();
}
else
DPRINTF(Uart, "UART InterEvent, not interrupting\n");
@ -92,11 +92,11 @@ Uart8250::IntrEvent::scheduleIntr()
{
static const Tick interval = 225 * SimClock::Int::ns;
DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit,
curTick + interval);
curTick() + interval);
if (!scheduled())
uart->schedule(this, curTick + interval);
uart->schedule(this, curTick() + interval);
else
uart->reschedule(this, curTick + interval);
uart->reschedule(this, curTick() + interval);
}
@ -218,13 +218,13 @@ Uart8250::write(PacketPtr pkt)
if (UART_IER_THRI & IER)
{
DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
if (curTick - lastTxInt > 225 * SimClock::Int::ns) {
if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
curTick, lastTxInt);
curTick(), lastTxInt);
txIntrEvent.process();
} else {
DPRINTF(Uart, "-- Delaying interrupt... %d,%d\n",
curTick, lastTxInt);
curTick(), lastTxInt);
txIntrEvent.scheduleIntr();
}
}

4
src/kern/kernel_stats.cc
View file

@ -120,8 +120,8 @@ Statistics::swpipl(int ipl)
return;
_iplGood[ipl]++;
_iplTicks[iplLast] += curTick - iplLastTick;
iplLastTick = curTick;
_iplTicks[iplLast] += curTick() - iplLastTick;
iplLastTick = curTick();
iplLast = ipl;
}

10
src/mem/bridge.cc
View file

@ -158,7 +158,7 @@ Bridge::BridgePort::nackRequest(PacketPtr pkt)
pkt->setNacked();
//put it on the list to send
Tick readyTime = curTick + nackDelay;
Tick readyTime = curTick() + nackDelay;
PacketBuffer *buf = new PacketBuffer(pkt, readyTime, true);
// nothing on the list, add it and we're done
@ -221,7 +221,7 @@ Bridge::BridgePort::queueForSendTiming(PacketPtr pkt)
Tick readyTime = curTick + delay;
Tick readyTime = curTick() + delay;
PacketBuffer *buf = new PacketBuffer(pkt, readyTime);
// If we're about to put this packet at the head of the queue, we
@ -241,7 +241,7 @@ Bridge::BridgePort::trySend()
PacketBuffer *buf = sendQueue.front();
assert(buf->ready <= curTick);
assert(buf->ready <= curTick());
PacketPtr pkt = buf->pkt;
@ -283,7 +283,7 @@ Bridge::BridgePort::trySend()
if (!sendQueue.empty()) {
buf = sendQueue.front();
DPRINTF(BusBridge, "Scheduling next send\n");
schedule(sendEvent, std::max(buf->ready, curTick + 1));
schedule(sendEvent, std::max(buf->ready, curTick() + 1));
}
} else {
DPRINTF(BusBridge, " unsuccessful\n");
@ -301,7 +301,7 @@ Bridge::BridgePort::recvRetry()
{
inRetry = false;
Tick nextReady = sendQueue.front()->ready;
if (nextReady <= curTick)
if (nextReady <= curTick())
trySend();
else
schedule(sendEvent, nextReady);

24
src/mem/bus.cc
View file

@ -142,10 +142,10 @@ Bus::calcPacketTiming(PacketPtr pkt)
// a cycle boundary to take up only the following cycle. Anything
// that happens later will have to "wait" for the end of that
// cycle, and then start using the bus after that.
if (tickNextIdle < curTick) {
tickNextIdle = curTick;
if (tickNextIdle < curTick()) {
tickNextIdle = curTick();
if (tickNextIdle % clock != 0)
tickNextIdle = curTick - (curTick % clock) + clock;
tickNextIdle = curTick() - (curTick() % clock) + clock;
}
Tick headerTime = tickNextIdle + headerCycles * clock;
@ -181,7 +181,7 @@ void Bus::occupyBus(Tick until)
reschedule(busIdle, tickNextIdle, true);
DPRINTF(Bus, "The bus is now occupied from tick %d to %d\n",
curTick, tickNextIdle);
curTick(), tickNextIdle);
}
/** Function called by the port when the bus is receiving a Timing
@ -205,7 +205,7 @@ Bus::recvTiming(PacketPtr pkt)
// If the bus is busy, or other devices are in line ahead of the current
// one, put this device on the retry list.
if (!pkt->isExpressSnoop() &&
(tickNextIdle > curTick ||
(tickNextIdle > curTick() ||
(retryList.size() && (!inRetry || src_port != retryList.front()))))
{
addToRetryList(src_port);
@ -295,7 +295,7 @@ void
Bus::recvRetry(int id)
{
// If there's anything waiting, and the bus isn't busy...
if (retryList.size() && curTick >= tickNextIdle) {
if (retryList.size() && curTick() >= tickNextIdle) {
//retryingPort = retryList.front();
inRetry = true;
DPRINTF(Bus, "Sending a retry to %s\n", retryList.front()->getPeer()->name());
@ -308,7 +308,7 @@ Bus::recvRetry(int id)
inRetry = false;
//Bring tickNextIdle up to the present
while (tickNextIdle < curTick)
while (tickNextIdle < curTick())
tickNextIdle += clock;
//Burn a cycle for the missed grant.
@ -318,7 +318,7 @@ Bus::recvRetry(int id)
}
}
//If we weren't able to drain before, we might be able to now.
if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle) {
if (drainEvent && retryList.size() == 0 && curTick() >= tickNextIdle) {
drainEvent->process();
// Clear the drain event once we're done with it.
drainEvent = NULL;
@ -435,7 +435,7 @@ Bus::recvAtomic(PacketPtr pkt)
}
// why do we have this packet field and the return value both???
pkt->finishTime = curTick + response_latency;
pkt->finishTime = curTick() + response_latency;
return response_latency;
}
@ -649,7 +649,7 @@ Bus::drain(Event * de)
//We should check that we're not "doing" anything, and that noone is
//waiting. We might be idle but have someone waiting if the device we
//contacted for a retry didn't actually retry.
if (retryList.size() || (curTick < tickNextIdle && busIdle.scheduled())) {
if (retryList.size() || (curTick() < tickNextIdle && busIdle.scheduled())) {
drainEvent = de;
return 1;
}
@ -659,8 +659,8 @@ Bus::drain(Event * de)
void
Bus::startup()
{
if (tickNextIdle < curTick)
tickNextIdle = (curTick / clock) * clock + clock;
if (tickNextIdle < curTick())
tickNextIdle = (curTick() / clock) * clock + clock;
}
Bus *

2
src/mem/cache/base.cc vendored
View file

@ -124,7 +124,7 @@ BaseCache::CachePort::clearBlocked()
mustSendRetry = false;
SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
schedule(ev, curTick + 1);
schedule(ev, curTick() + 1);
}
}

4
src/mem/cache/base.hh vendored
View file

@ -434,7 +434,7 @@ class BaseCache : public MemObject
uint8_t flag = 1 << cause;
if (blocked == 0) {
blocked_causes[cause]++;
blockedCycle = curTick;
blockedCycle = curTick();
cpuSidePort->setBlocked();
}
blocked |= flag;
@ -454,7 +454,7 @@ class BaseCache : public MemObject
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
blocked_cycles[cause] += curTick - blockedCycle;
blocked_cycles[cause] += curTick() - blockedCycle;
cpuSidePort->clearBlocked();
}
}

2
src/mem/cache/blk.hh vendored
View file

@ -89,7 +89,7 @@ class CacheBlk
/** The current status of this block. @sa CacheBlockStatusBits */
State status;
/** Which curTick will this block be accessable */
/** Which curTick() will this block be accessable */
Tick whenReady;
/**

18
src/mem/cache/cache_impl.hh vendored
View file

@ -412,7 +412,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
// MemDebug::cacheAccess(pkt);
// we charge hitLatency for doing just about anything here
Tick time = curTick + hitLatency;
Tick time = curTick() + hitLatency;
if (pkt->isResponse()) {
// must be cache-to-cache response from upper to lower level
@ -504,7 +504,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
if (satisfied) {
if (needsResponse) {
pkt->makeTimingResponse();
cpuSidePort->respond(pkt, curTick+lat);
cpuSidePort->respond(pkt, curTick()+lat);
} else {
delete pkt;
}
@ -532,7 +532,7 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
noTargetMSHR = mshr;
setBlocked(Blocked_NoTargets);
// need to be careful with this... if this mshr isn't
// ready yet (i.e. time > curTick_, we don't want to
// ready yet (i.e. time > curTick()_, we don't want to
// move it ahead of mshrs that are ready
// mshrQueue.moveToFront(mshr);
}
@ -816,7 +816,7 @@ template<class TagStore>
void
Cache<TagStore>::handleResponse(PacketPtr pkt)
{
Tick time = curTick + hitLatency;
Tick time = curTick() + hitLatency;
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
bool is_error = pkt->isError();
@ -848,7 +848,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
MSHR::Target *initial_tgt = mshr->getTarget();
BlkType *blk = tags->findBlock(pkt->getAddr());
int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
Tick miss_latency = curTick - initial_tgt->recvTime;
Tick miss_latency = curTick() - initial_tgt->recvTime;
PacketList writebacks;
if (pkt->req->isUncacheable()) {
@ -1159,7 +1159,7 @@ doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
// invalidate it.
pkt->cmd = MemCmd::ReadRespWithInvalidate;
}
memSidePort->respond(pkt, curTick + hitLatency);
memSidePort->respond(pkt, curTick() + hitLatency);
}
template<class TagStore>
@ -1430,7 +1430,7 @@ Cache<TagStore>::getNextMSHR()
// (hwpf_mshr_misses)
mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
// Don't request bus, since we already have it
return allocateMissBuffer(pkt, curTick, false);
return allocateMissBuffer(pkt, curTick(), false);
}
}
}
@ -1461,7 +1461,7 @@ Cache<TagStore>::getTimingPacket()
pkt = new Packet(tgt_pkt);
pkt->cmd = MemCmd::UpgradeFailResp;
pkt->senderState = mshr;
pkt->firstWordTime = pkt->finishTime = curTick;
pkt->firstWordTime = pkt->finishTime = curTick();
handleResponse(pkt);
return NULL;
} else if (mshr->isForwardNoResponse()) {
@ -1679,7 +1679,7 @@ Cache<TagStore>::MemSidePort::sendPacket()
// @TODO: need to facotr in prefetch requests here somehow
if (nextReady != MaxTick) {
DPRINTF(CachePort, "more packets to send @ %d\n", nextReady);
schedule(sendEvent, std::max(nextReady, curTick + 1));
schedule(sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send right now: if we're draining, we may be done
if (drainEvent && !sendEvent->scheduled()) {

4
src/mem/cache/mshr.cc vendored
View file

@ -333,7 +333,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order)
// Actual target device (typ. PhysicalMemory) will delete the
// packet on reception, so we need to save a copy here.
PacketPtr cp_pkt = new Packet(pkt, true);
targets->add(cp_pkt, curTick, _order, Target::FromSnoop,
targets->add(cp_pkt, curTick(), _order, Target::FromSnoop,
downstreamPending && targets->needsExclusive);
++ntargets;
@ -378,7 +378,7 @@ MSHR::promoteDeferredTargets()
deferredTargets->resetFlags();
order = targets->front().order;
readyTime = std::max(curTick, targets->front().readyTime);
readyTime = std::max(curTick(), targets->front().readyTime);
return true;
}

2
src/mem/cache/mshr.hh vendored
View file

@ -72,7 +72,7 @@ class MSHR : public Packet::SenderState, public Printable
Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
Source _source, bool _markedPending)
: recvTime(curTick), readyTime(_readyTime), order(_order),
: recvTime(curTick()), readyTime(_readyTime), order(_order),
pkt(_pkt), source(_source), markedPending(_markedPending)
{}
};

2
src/mem/cache/mshr_queue.hh vendored
View file

@ -199,7 +199,7 @@ class MSHRQueue
*/
MSHR *getNextMSHR() const
{
if (readyList.empty() || readyList.front()->readyTime > curTick) {
if (readyList.empty() || readyList.front()->readyTime > curTick()) {
return NULL;
}
return readyList.front();

2
src/mem/cache/tags/fa_lru.cc vendored
View file

@ -220,7 +220,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks)
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
warmupCycle = curTick;
warmupCycle = curTick();
}
}
//assert(check());

6
src/mem/cache/tags/iic.cc vendored
View file

@ -257,8 +257,8 @@ IIC::accessBlock(Addr addr, int &lat, int context_src)
hitDepthTotal += sets[set].depth;
tag_ptr->status |= BlkReferenced;
lat = set_lat;
if (tag_ptr->whenReady > curTick && tag_ptr->whenReady - curTick > set_lat) {
lat = tag_ptr->whenReady - curTick;
if (tag_ptr->whenReady > curTick() && tag_ptr->whenReady - curTick() > set_lat) {
lat = tag_ptr->whenReady - curTick();
}
tag_ptr->refCount += 1;
@ -437,7 +437,7 @@ IIC::getFreeTag(int set, PacketList & writebacks)
tagsInUse++;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
warmupCycle = curTick;
warmupCycle = curTick();
}
return tag_ptr;

8
src/mem/cache/tags/lru.cc vendored
View file

@ -126,9 +126,9 @@ LRU::accessBlock(Addr addr, int &lat, int context_src)
sets[set].moveToHead(blk);
DPRINTF(CacheRepl, "set %x: moving blk %x to MRU\n",
set, regenerateBlkAddr(tag, set));
if (blk->whenReady > curTick
&& blk->whenReady - curTick > hitLatency) {
lat = blk->whenReady - curTick;
if (blk->whenReady > curTick()
&& blk->whenReady - curTick() > hitLatency) {
lat = blk->whenReady - curTick();
}
blk->refCount += 1;
}
@ -180,7 +180,7 @@ LRU::insertBlock(Addr addr, BlkType *blk, int context_src)
blk->isTouched = true;
if (!warmedUp && tagsInUse.value() >= warmupBound) {
warmedUp = true;
warmupCycle = curTick;
warmupCycle = curTick();
}
}

72
src/mem/dram.cc
View file

@ -414,14 +414,14 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
int SD_BEST_T_WRITE_READ_OBANK = (war_lat -1); /* WAR, row miss/hit, another bank */
int SD_BEST_T_WRITE_WRITE_OBANK = 0; /* WAW, row miss/hit, another bank */
Tick time_since_last_access = curTick-time_last_access;
Tick time_since_last_access = curTick()-time_last_access;
Tick time_last_miss = 0; // used for keeping track of times between activations (page misses)
//int was_idle = (curTick > busy_until);
//int was_idle = (curTick() > busy_until);
bool srow_flag = false;
int timing_correction = 0;
int was_idle = (curTick > busy_until[current_bank]);
cycles_nCKE[0] += was_idle ? MIN(curTick-busy_until[current_bank], time_since_last_access) : 0;
int was_idle = (curTick() > busy_until[current_bank]);
cycles_nCKE[0] += was_idle ? MIN(curTick()-busy_until[current_bank], time_since_last_access) : 0;
// bank is precharged
//active_row[current_bank] == DR_NUM_ROWS
@ -441,7 +441,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if(all_precharged) {
if(was_idle) {
cycles_all_precharge_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access);
cycles_all_precharge_nCKE[0] += MIN(curTick()-busy_until[current_bank], time_since_last_access);
cycles_all_precharge_CKE[0] += MIN(0, busy_until[current_bank]-time_last_access);
}
else {
@ -449,7 +449,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
}
} else { // some bank is active
if(was_idle) {
cycles_bank_active_nCKE[0] += MIN(curTick-busy_until[current_bank], time_since_last_access);
cycles_bank_active_nCKE[0] += MIN(curTick()-busy_until[current_bank], time_since_last_access);
}
else {
}
@ -462,7 +462,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
}
time_last_access = curTick;
time_last_access = curTick();
////////////////////////////////////////////////////////////////////////////
if ((mem_type == "SDRAM") && (mem_actpolicy == "open"))
@ -516,7 +516,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (memctrlpipe_enable == true)
{
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
}
else overlap = 0;
@ -529,7 +529,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
corrected_overlap = (int) (overlap/cpu_ratio);
}
/*fprintf(stderr,"%10.0f %10.0f %4d %4d ",(double)busy_until, (double)curTick, overlap, corrected_overlap); debugging*/
/*fprintf(stderr,"%10.0f %10.0f %4d %4d ",(double)busy_until, (double)curTick(), overlap, corrected_overlap); debugging*/
if (cmdIsRead == lastCmdIsRead)/*same command*/
{
@ -889,25 +889,25 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
{
if (memctrlpipe_enable == true)
{
busy_until[current_bank]=curTick+lat+
busy_until[current_bank]=curTick()+lat+
timing_correction;
}
else
{
if (busy_until[current_bank] >= curTick)
if (busy_until[current_bank] >= curTick())
{
busy_until[current_bank]+=(lat+
timing_correction);
total_arb_latency += (busy_until[current_bank]
- curTick - lat
- curTick() - lat
- timing_correction);
lat=busy_until[current_bank] - curTick;
lat=busy_until[current_bank] - curTick();
}
else busy_until[current_bank]=curTick+lat+
else busy_until[current_bank]=curTick()+lat+
timing_correction;
}
}
else/*the memory request will be satisfied temp cycles after curTick*/
else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=(lat+
timing_correction);
@ -1001,7 +1001,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (memctrlpipe_enable == true)
{
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
}
else overlap=0;
@ -1014,7 +1014,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
corrected_overlap = (int) (overlap/cpu_ratio);
}
/*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick, overlap, corrected_overlap,precharge,adjacent);debugging*/
/*fprintf(stderr,"%10.0f %10.0f %6d %6d %2d %2d ",(double)busy_until, (double)curTick(), overlap, corrected_overlap,precharge,adjacent);debugging*/
if (cmdIsRead == lastCmdIsRead)/*same command*/
{
@ -2013,19 +2013,19 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
{
if (memctrlpipe_enable == true)
{
busy_until[current_bank] =curTick+lat;
busy_until[current_bank] =curTick()+lat;
}
else
{
if (busy_until[current_bank] >= curTick)
if (busy_until[current_bank] >= curTick())
{
busy_until[current_bank] +=lat;
lat=busy_until[current_bank] - curTick;
lat=busy_until[current_bank] - curTick();
}
else busy_until[current_bank] = curTick+lat;
else busy_until[current_bank] = curTick()+lat;
}
}
else/*the memory request will be satisfied temp cycles after curTick*/
else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
@ -2073,7 +2073,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
}
total_access++;
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
if (current_bank == last_bank)/*same bank*/
{
@ -2206,9 +2206,9 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (overlap <= 0) /*memory interface is not busy*/
{
busy_until[current_bank] = curTick+lat;
busy_until[current_bank] = curTick()+lat;
}
else /*the memory request will be satisfied temp cycles after curTick*/
else /*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
@ -2223,7 +2223,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
/*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);debug*/
/*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick(), overlap, lat);debug*/
// if((_cpu_num < num_cpus) && (_cpu_num >= 0))
// cout <<"cpu id = " << _cpu_num << "current_bank = " << current_bank << endl;
// bank_access_profile[_cpu_num][current_bank]++;
@ -2269,7 +2269,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
}
total_access++;
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
if (cpu_ratio < 1.0)
{
@ -2432,16 +2432,16 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (overlap <= 0) /*memory interface is not busy*/
{
busy_until[current_bank] = curTick+lat;
busy_until[current_bank] = curTick()+lat;
}
else/*the memory request will be satisfied temp cycles after curTick*/
else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
lat+=overlap;
}
/*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick, overlap, lat);*/
/*fprintf(stderr,"%10.0f %10.0f %4d %4d \n",(double)busy_until, (double)curTick(), overlap, lat);*/
if (cmdIsRead)
{
@ -2494,7 +2494,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
total_access++;
lat += chunks;
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
lastCmdIsRead=cmdIsRead;
if (cpu_ratio < 1.0)
@ -2509,9 +2509,9 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (overlap <= 0) /*memory interface is not busy*/
{
busy_until[current_bank] = curTick+lat;
busy_until[current_bank] = curTick()+lat;
}
else/*the memory request will be satisfied temp cycles after curTick*/
else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] +=lat;
command_overlapping++;
@ -2543,7 +2543,7 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
lat = DR_T_RCD + DR_T_CWD + DR_T_PACKET; /* DR_T_RP + */
}
total_access++;
overlap=(int)(busy_until[current_bank] - curTick);
overlap=(int)(busy_until[current_bank] - curTick());
lat += chunks * DR_T_PACKET; /*every 128 bit need DR_NUM_CYCLES*/
if (cpu_ratio < 1.0)
@ -2560,9 +2560,9 @@ DRAMMemory::calculateLatency(PacketPtr pkt)
if (overlap <= 0) /*memory interface is not busy*/
{
busy_until[current_bank] = curTick+lat;
busy_until[current_bank] = curTick()+lat;
}
else/*the memory request will be satisfied temp cycles after curTick*/
else/*the memory request will be satisfied temp cycles after curTick()*/
{
busy_until[current_bank] += lat;
command_overlapping++;

Some files were not shown because too many files have changed in this diff Show more