7eccb1b779
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
60 lines
2.5 KiB
Python
60 lines
2.5 KiB
Python
# Copyright (c) 2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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from m5.SimObject import SimObject
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from m5.params import *
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from m5.proxy import *
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from Pci import PciDevice
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class CopyEngine(PciDevice):
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type = 'CopyEngine'
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cxx_header = "dev/copy_engine.hh"
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dma = VectorMasterPort("Copy engine DMA port")
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VendorID = 0x8086
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DeviceID = 0x1a38
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Revision = 0xA2 # CM2 stepping (newest listed)
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SubsystemID = 0
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SubsystemVendorID = 0
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Status = 0x0000
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SubClassCode = 0x08
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ClassCode = 0x80
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ProgIF = 0x00
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MaximumLatency = 0x00
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MinimumGrant = 0xff
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InterruptLine = 0x20
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InterruptPin = 0x01
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BAR0Size = '1kB'
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ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
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XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
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latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
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latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
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